SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 775925 | 1 | T1 | 8 | T19 | 2 | T20 | 28 | |||
auto[1] | 14377 | 1 | T41 | 645 | T46 | 38 | T55 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 790099 | 1 | T1 | 8 | T19 | 2 | T20 | 28 | |||
values[1] | 26 | 1 | T39 | 2 | T87 | 4 | T91 | 2 | |||
values[2] | 3 | 1 | T39 | 1 | T104 | 1 | T149 | 1 | |||
values[3] | 110 | 1 | T38 | 4 | T39 | 6 | T40 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 790095 | 1 | T1 | 8 | T19 | 2 | T20 | 28 | |||
values[1] | 19 | 1 | T39 | 3 | T87 | 2 | T91 | 2 | |||
values[2] | 4 | 1 | T91 | 1 | T92 | 1 | T116 | 1 | |||
values[3] | 116 | 1 | T38 | 6 | T39 | 6 | T40 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 789992 | 1 | T1 | 8 | T19 | 2 | T20 | 28 | |||
auto[TlIntgErrCmd] | 103 | 1 | T38 | 3 | T39 | 7 | T40 | 4 | |||
auto[TlIntgErrData] | 107 | 1 | T38 | 4 | T39 | 4 | T40 | 2 | |||
auto[TlIntgErrBoth] | 100 | 1 | T38 | 3 | T39 | 9 | T40 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 27703 | 0 | T2 | 1 | T33 | 3 | T34 | 23 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 27507 | 1 | T2 | 1 | T33 | 3 | T34 | 23 | |||
values[1] | 24 | 1 | T39 | 4 | T40 | 1 | T87 | 4 | |||
values[2] | 3 | 1 | T104 | 1 | T150 | 1 | T149 | 1 | |||
values[3] | 97 | 1 | T38 | 4 | T39 | 5 | T40 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 27482 | 1 | T2 | 1 | T33 | 3 | T34 | 23 | |||
values[1] | 27 | 1 | T40 | 2 | T87 | 2 | T91 | 1 | |||
values[2] | 3 | 1 | T39 | 1 | T151 | 1 | T149 | 1 | |||
values[3] | 110 | 1 | T38 | 4 | T39 | 4 | T40 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 27393 | 1 | T2 | 1 | T33 | 3 | T34 | 23 | |||
auto[TlIntgErrCmd] | 89 | 1 | T38 | 2 | T39 | 8 | T40 | 2 | |||
auto[TlIntgErrData] | 114 | 1 | T38 | 6 | T39 | 6 | T40 | 3 | |||
auto[TlIntgErrBoth] | 107 | 1 | T38 | 2 | T39 | 6 | T40 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |