Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	227852	1		T1	2		T20	8		T7	45
full_word	562450	1		T1	6		T19	2		T20	20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	789992	1		T1	8		T19	2		T20	28
auto[TlIntgErrCmd]	103	1		T38	3		T39	7		T40	4
auto[TlIntgErrData]	107	1		T38	4		T39	4		T40	2
auto[TlIntgErrBoth]	100	1		T38	3		T39	9		T40	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	468803	1		T1	4		T20	14		T7	30
auto[1]	321499	1		T1	4		T19	2		T20	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	190270	1		T1	2		T20	8		T7	16
auto[TlIntgErrNone]	partial	auto[1]	37303	1		T7	29		T4	29		T5	72
auto[TlIntgErrNone]	full_word	auto[0]	278392	1		T1	2		T20	6		T7	14
auto[TlIntgErrNone]	full_word	auto[1]	284027	1		T1	4		T19	2		T20	14
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T38	1		T39	3		T40	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T38	2		T39	4		T87	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T40	1		T87	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T92	1		T104	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T38	1		T39	2		T40	1
auto[TlIntgErrData]	partial	auto[1]	49	1		T38	2		T39	2		T40	1
auto[TlIntgErrData]	full_word	auto[0]	9	1		T87	1		T92	1		T104	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T38	1		T116	1		T152	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1		T39	5		T40	2		T87	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T38	3		T39	3		T40	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T40	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T39	1		T87	2		T91	1