Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196473	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	561227	1		T1	6		T19	2		T20	20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	467351	1		T1	4		T20	14		T7	30
values[0x0]	143426	1		T1	2		T19	1		T20	5
values[0x1]	146923	1		T1	2		T19	1		T20	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151570	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	606130	1		T1	7		T19	2		T20	23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2672	1		T44	32		T45	47		T46	1
valid_sources[0x01]	2526	1		T44	12		T46	3		T38	15
valid_sources[0x02]	3275	1		T7	1		T44	31		T45	289
valid_sources[0x03]	3289	1		T44	27		T45	333		T46	1
valid_sources[0x04]	3588	1		T8	2		T16	1		T44	16
valid_sources[0x05]	3055	1		T8	1		T41	3		T44	14
valid_sources[0x06]	3229	1		T44	49		T42	20		T38	14
valid_sources[0x07]	3083	1		T44	23		T45	47		T46	5
valid_sources[0x08]	3056	1		T7	1		T97	1		T41	4
valid_sources[0x09]	2599	1		T41	3		T44	7		T45	47
valid_sources[0x0a]	2800	1		T44	17		T45	47		T46	1
valid_sources[0x0b]	2593	1		T4	2		T41	1		T45	7
valid_sources[0x0c]	3229	1		T41	2		T44	13		T46	3
valid_sources[0x0d]	3047	1		T19	1		T41	2		T44	69
valid_sources[0x0e]	3664	1		T7	2		T41	2		T44	61
valid_sources[0x0f]	2913	1		T41	4		T44	9		T45	47
valid_sources[0x10]	3189	1		T41	5		T45	285		T46	2
valid_sources[0x11]	3154	1		T97	1		T41	2		T44	8
valid_sources[0x12]	2826	1		T41	1		T44	8		T45	47
valid_sources[0x13]	3004	1		T8	1		T44	7		T45	21
valid_sources[0x14]	2618	1		T8	1		T44	56		T45	94
valid_sources[0x15]	3316	1		T7	1		T16	2		T41	3
valid_sources[0x16]	3080	1		T25	6		T97	2		T41	3
valid_sources[0x17]	2880	1		T41	2		T44	40		T46	7
valid_sources[0x18]	2699	1		T41	3		T44	14		T45	102
valid_sources[0x19]	2729	1		T44	80		T45	83		T46	4
valid_sources[0x1a]	3373	1		T8	1		T41	1		T44	31
valid_sources[0x1b]	2820	1		T16	3		T41	3		T44	51
valid_sources[0x1c]	3745	1		T4	1		T44	30		T45	330
valid_sources[0x1d]	2569	1		T44	10		T46	4		T38	9
valid_sources[0x1e]	3193	1		T7	2		T8	1		T41	1
valid_sources[0x1f]	3592	1		T41	1		T44	36		T45	94
valid_sources[0x20]	2798	1		T41	3		T44	33		T45	94
valid_sources[0x21]	2968	1		T41	10		T44	35		T45	324
valid_sources[0x22]	2382	1		T4	4		T44	7		T45	97
valid_sources[0x23]	3084	1		T8	1		T97	1		T41	5
valid_sources[0x24]	3105	1		T4	1		T44	6		T46	2
valid_sources[0x25]	2596	1		T7	1		T8	1		T41	2
valid_sources[0x26]	3277	1		T7	2		T41	1		T44	38
valid_sources[0x27]	2994	1		T44	26		T45	114		T46	3
valid_sources[0x28]	3056	1		T41	1		T44	89		T45	245
valid_sources[0x29]	2803	1		T25	4		T41	1		T44	20
valid_sources[0x2a]	2820	1		T7	1		T97	1		T41	7
valid_sources[0x2b]	2763	1		T41	6		T46	6		T38	26
valid_sources[0x2c]	2844	1		T41	2		T44	16		T45	90
valid_sources[0x2d]	2778	1		T4	1		T44	84		T55	1
valid_sources[0x2e]	2772	1		T8	1		T44	56		T46	2
valid_sources[0x2f]	3585	1		T7	1		T41	4		T44	8
valid_sources[0x30]	3005	1		T4	2		T97	1		T44	83
valid_sources[0x31]	2621	1		T41	6		T45	94		T46	1
valid_sources[0x32]	2896	1		T7	1		T97	2		T44	1
valid_sources[0x33]	2908	1		T6	1		T44	18		T46	5
valid_sources[0x34]	2579	1		T97	1		T41	1		T44	9
valid_sources[0x35]	2986	1		T44	10		T45	116		T46	5
valid_sources[0x36]	2612	1		T25	12		T97	1		T41	1
valid_sources[0x37]	3216	1		T7	1		T44	13		T45	176
valid_sources[0x38]	2936	1		T7	2		T44	27		T45	403
valid_sources[0x39]	2535	1		T41	4		T44	26		T45	47
valid_sources[0x3a]	2620	1		T97	3		T44	18		T45	67
valid_sources[0x3b]	2981	1		T41	2		T45	29		T46	1
valid_sources[0x3c]	2964	1		T8	2		T41	1		T44	3
valid_sources[0x3d]	2360	1		T4	2		T16	1		T97	2
valid_sources[0x3e]	2502	1		T44	35		T45	47		T46	2
valid_sources[0x3f]	3154	1		T7	1		T41	3		T44	37
valid_sources[0x40]	2857	1		T4	1		T41	1		T46	5
valid_sources[0x41]	3152	1		T19	1		T8	1		T41	1
valid_sources[0x42]	2734	1		T41	3		T44	20		T46	4
valid_sources[0x43]	2778	1		T1	2		T41	1		T44	30
valid_sources[0x44]	2231	1		T41	2		T44	52		T45	47
valid_sources[0x45]	2747	1		T7	1		T41	8		T44	57
valid_sources[0x46]	2588	1		T7	1		T41	1		T44	56
valid_sources[0x47]	2779	1		T44	39		T46	3		T38	26
valid_sources[0x48]	3533	1		T41	2		T44	42		T45	400
valid_sources[0x49]	3275	1		T7	1		T25	7		T41	3
valid_sources[0x4a]	3122	1		T1	3		T7	1		T8	1
valid_sources[0x4b]	2956	1		T41	4		T44	66		T45	14
valid_sources[0x4c]	3250	1		T8	1		T41	1		T45	175
valid_sources[0x4d]	2870	1		T44	14		T45	47		T46	3
valid_sources[0x4e]	2987	1		T41	1		T44	26		T45	47
valid_sources[0x4f]	2916	1		T41	5		T44	19		T45	10
valid_sources[0x50]	2820	1		T97	1		T44	3		T45	81
valid_sources[0x51]	2453	1		T7	1		T41	1		T44	45
valid_sources[0x52]	2799	1		T41	1		T44	2		T45	94
valid_sources[0x53]	3048	1		T6	1		T41	2		T44	17
valid_sources[0x54]	3675	1		T8	2		T41	1		T44	16
valid_sources[0x55]	2369	1		T41	1		T45	47		T46	2
valid_sources[0x56]	2678	1		T41	2		T44	31		T46	3
valid_sources[0x57]	3149	1		T6	2		T97	1		T41	3
valid_sources[0x58]	2803	1		T7	1		T44	26		T45	118
valid_sources[0x59]	2642	1		T16	12		T44	20		T46	4
valid_sources[0x5a]	3244	1		T8	1		T16	1		T44	22
valid_sources[0x5b]	3307	1		T44	19		T45	66		T38	38
valid_sources[0x5c]	2953	1		T44	18		T45	392		T46	1
valid_sources[0x5d]	2612	1		T4	1		T44	19		T45	220
valid_sources[0x5e]	2805	1		T8	1		T41	2		T44	12
valid_sources[0x5f]	3287	1		T41	1		T44	23		T46	5
valid_sources[0x60]	3139	1		T4	1		T16	3		T97	1
valid_sources[0x61]	2813	1		T4	1		T41	2		T44	15
valid_sources[0x62]	3288	1		T97	1		T41	1		T44	23
valid_sources[0x63]	2777	1		T97	2		T41	3		T44	25
valid_sources[0x64]	2804	1		T88	1		T41	2		T44	16
valid_sources[0x65]	2935	1		T97	1		T41	7		T44	14
valid_sources[0x66]	3112	1		T7	2		T4	2		T41	1
valid_sources[0x67]	2873	1		T41	5		T44	8		T45	140
valid_sources[0x68]	2930	1		T7	1		T44	25		T45	47
valid_sources[0x69]	2993	1		T44	4		T45	47		T46	1
valid_sources[0x6a]	2813	1		T7	1		T41	1		T44	49
valid_sources[0x6b]	2844	1		T45	47		T46	2		T38	28
valid_sources[0x6c]	3065	1		T8	1		T97	1		T41	2
valid_sources[0x6d]	2347	1		T4	2		T41	5		T45	47
valid_sources[0x6e]	3206	1		T44	31		T45	429		T38	20
valid_sources[0x6f]	3578	1		T44	32		T45	47		T46	3
valid_sources[0x70]	2626	1		T41	4		T44	65		T46	2
valid_sources[0x71]	2634	1		T7	2		T8	1		T41	1
valid_sources[0x72]	2975	1		T41	3		T44	11		T45	198
valid_sources[0x73]	2275	1		T44	5		T46	1		T38	23
valid_sources[0x74]	2748	1		T41	1		T44	5		T45	18
valid_sources[0x75]	3241	1		T7	2		T41	2		T44	33
valid_sources[0x76]	3307	1		T88	1		T8	1		T41	4
valid_sources[0x77]	3569	1		T44	8		T45	328		T46	4
valid_sources[0x78]	3016	1		T7	1		T45	188		T46	3
valid_sources[0x79]	2842	1		T41	2		T44	56		T45	79
valid_sources[0x7a]	3140	1		T44	9		T45	63		T46	4
valid_sources[0x7b]	2440	1		T41	2		T44	47		T45	118
valid_sources[0x7c]	3027	1		T41	2		T44	6		T45	72
valid_sources[0x7d]	2758	1		T4	1		T97	1		T41	2
valid_sources[0x7e]	3267	1		T41	8		T45	45		T38	30
valid_sources[0x7f]	2891	1		T41	2		T44	9		T46	3
valid_sources[0x80]	3297	1		T8	1		T41	5		T44	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

278270

1

T1

2

T20

6

T7

14

values[0x0]

all_enables

biggest_size

141773

1

T1

2

T19

1

T20

5

values[0x1]

all_enables

biggest_size

141184

1

T1

2

T19

1

T20

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2198	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15754	1		T34	4		T47	3		T48	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5588	1		T41	46		T44	12		T45	282
values[0x0]	6107	1		T33	2		T34	12		T47	4
values[0x1]	6257	1		T2	1		T33	1		T34	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1719	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	16233	1		T34	4		T47	3		T48	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	100	1		T153	4		T45	6		T55	1
valid_sources[0x01]	148	1		T45	2		T43	5		T104	1
valid_sources[0x02]	115	1		T41	1		T46	1		T61	1
valid_sources[0x03]	57	1		T154	1		T46	1		T43	1
valid_sources[0x04]	50	1		T53	1		T155	1		T45	1
valid_sources[0x05]	66	1		T46	1		T38	1		T61	6
valid_sources[0x06]	55	1		T156	1		T45	1		T38	1
valid_sources[0x07]	99	1		T89	8		T105	5		T113	2
valid_sources[0x08]	50	1		T47	1		T157	1		T158	2
valid_sources[0x09]	142	1		T85	1		T41	4		T46	2
valid_sources[0x0a]	38	1		T45	1		T43	3		T61	1
valid_sources[0x0b]	52	1		T50	1		T79	1		T41	5
valid_sources[0x0c]	74	1		T55	3		T61	1		T60	2
valid_sources[0x0d]	117	1		T45	1		T46	2		T61	2
valid_sources[0x0e]	47	1		T45	2		T61	1		T39	1
valid_sources[0x0f]	87	1		T41	1		T61	1		T89	8
valid_sources[0x10]	84	1		T46	4		T43	3		T105	5
valid_sources[0x11]	42	1		T45	3		T61	1		T99	1
valid_sources[0x12]	39	1		T154	1		T41	2		T45	1
valid_sources[0x13]	58	1		T154	1		T45	1		T46	1
valid_sources[0x14]	84	1		T53	1		T159	1		T160	5
valid_sources[0x15]	78	1		T41	8		T44	15		T46	2
valid_sources[0x16]	39	1		T161	1		T43	1		T90	1
valid_sources[0x17]	181	1		T41	2		T55	1		T104	1
valid_sources[0x18]	84	1		T46	2		T55	1		T61	3
valid_sources[0x19]	55	1		T79	1		T46	3		T55	1
valid_sources[0x1a]	83	1		T41	5		T42	27		T43	1
valid_sources[0x1b]	83	1		T41	2		T45	5		T46	2
valid_sources[0x1c]	67	1		T41	1		T46	1		T38	1
valid_sources[0x1d]	57	1		T33	2		T46	1		T55	1
valid_sources[0x1e]	146	1		T2	1		T41	1		T45	5
valid_sources[0x1f]	44	1		T46	9		T55	2		T61	1
valid_sources[0x20]	53	1		T45	1		T46	6		T99	2
valid_sources[0x21]	43	1		T162	1		T45	1		T55	1
valid_sources[0x22]	43	1		T49	2		T163	8		T164	1
valid_sources[0x23]	40	1		T50	1		T158	1		T61	1
valid_sources[0x24]	44	1		T45	2		T43	3		T61	7
valid_sources[0x25]	40	1		T50	1		T41	1		T105	1
valid_sources[0x26]	60	1		T79	1		T41	3		T45	2
valid_sources[0x27]	60	1		T50	1		T159	1		T46	1
valid_sources[0x28]	115	1		T55	1		T42	42		T43	7
valid_sources[0x29]	47	1		T41	1		T165	2		T104	1
valid_sources[0x2a]	49	1		T157	2		T45	1		T55	1
valid_sources[0x2b]	39	1		T47	1		T41	1		T43	1
valid_sources[0x2c]	57	1		T51	2		T79	1		T45	4
valid_sources[0x2d]	87	1		T41	1		T61	2		T100	4
valid_sources[0x2e]	49	1		T55	2		T61	1		T60	4
valid_sources[0x2f]	78	1		T61	1		T129	1		T166	1
valid_sources[0x30]	43	1		T154	1		T41	1		T55	1
valid_sources[0x31]	43	1		T167	8		T46	5		T61	1
valid_sources[0x32]	62	1		T45	4		T46	1		T55	1
valid_sources[0x33]	70	1		T45	3		T55	1		T113	1
valid_sources[0x34]	53	1		T45	4		T46	2		T91	3
valid_sources[0x35]	56	1		T55	2		T61	2		T58	8
valid_sources[0x36]	157	1		T168	8		T158	1		T67	1
valid_sources[0x37]	141	1		T41	4		T46	1		T42	91
valid_sources[0x38]	80	1		T158	1		T43	2		T61	1
valid_sources[0x39]	105	1		T75	2		T41	9		T61	5
valid_sources[0x3a]	79	1		T38	1		T43	3		T60	10
valid_sources[0x3b]	55	1		T169	1		T45	1		T165	1
valid_sources[0x3c]	95	1		T45	5		T46	3		T55	2
valid_sources[0x3d]	107	1		T170	1		T55	1		T42	59
valid_sources[0x3e]	323	1		T41	4		T45	1		T38	1
valid_sources[0x3f]	84	1		T46	1		T43	1		T61	3
valid_sources[0x40]	61	1		T49	4		T41	1		T46	2
valid_sources[0x41]	45	1		T41	2		T45	1		T55	1
valid_sources[0x42]	42	1		T45	2		T46	3		T55	1
valid_sources[0x43]	113	1		T45	3		T46	1		T43	1
valid_sources[0x44]	50	1		T45	1		T43	7		T61	1
valid_sources[0x45]	65	1		T155	1		T169	2		T45	3
valid_sources[0x46]	89	1		T162	1		T55	2		T43	2
valid_sources[0x47]	121	1		T67	1		T41	1		T43	20
valid_sources[0x48]	63	1		T41	5		T43	1		T61	2
valid_sources[0x49]	65	1		T43	9		T61	9		T65	13
valid_sources[0x4a]	88	1		T77	1		T154	1		T45	1
valid_sources[0x4b]	61	1		T157	3		T45	1		T46	3
valid_sources[0x4c]	47	1		T67	1		T41	2		T45	1
valid_sources[0x4d]	88	1		T45	1		T46	5		T43	9
valid_sources[0x4e]	75	1		T85	2		T41	8		T45	4
valid_sources[0x4f]	35	1		T50	1		T171	1		T41	3
valid_sources[0x50]	54	1		T162	1		T41	2		T45	3
valid_sources[0x51]	40	1		T46	1		T172	9		T104	2
valid_sources[0x52]	47	1		T162	2		T157	3		T45	1
valid_sources[0x53]	81	1		T155	1		T45	1		T46	3
valid_sources[0x54]	64	1		T162	1		T61	1		T123	2
valid_sources[0x55]	61	1		T85	2		T38	1		T43	5
valid_sources[0x56]	50	1		T45	1		T46	1		T43	6
valid_sources[0x57]	47	1		T46	6		T61	3		T87	1
valid_sources[0x58]	52	1		T153	1		T45	1		T46	1
valid_sources[0x59]	77	1		T41	2		T43	4		T61	3
valid_sources[0x5a]	35	1		T45	4		T43	1		T61	1
valid_sources[0x5b]	41	1		T173	1		T46	1		T55	2
valid_sources[0x5c]	88	1		T55	3		T43	2		T61	1
valid_sources[0x5d]	48	1		T162	1		T45	1		T90	1
valid_sources[0x5e]	39	1		T174	2		T45	1		T87	2
valid_sources[0x5f]	52	1		T46	4		T61	3		T60	10
valid_sources[0x60]	79	1		T43	2		T61	1		T60	9
valid_sources[0x61]	47	1		T85	1		T155	2		T55	1
valid_sources[0x62]	53	1		T85	1		T61	1		T60	7
valid_sources[0x63]	96	1		T145	10		T41	1		T46	1
valid_sources[0x64]	88	1		T55	4		T43	3		T61	4
valid_sources[0x65]	40	1		T41	5		T61	3		T105	3
valid_sources[0x66]	107	1		T53	1		T45	5		T46	2
valid_sources[0x67]	75	1		T48	3		T158	1		T41	3
valid_sources[0x68]	85	1		T79	1		T159	1		T45	3
valid_sources[0x69]	37	1		T45	2		T172	5		T105	1
valid_sources[0x6a]	71	1		T45	3		T46	5		T61	3
valid_sources[0x6b]	71	1		T157	1		T45	5		T43	1
valid_sources[0x6c]	62	1		T47	1		T175	6		T55	1
valid_sources[0x6d]	51	1		T159	1		T176	1		T169	1
valid_sources[0x6e]	73	1		T153	1		T170	1		T65	3
valid_sources[0x6f]	92	1		T85	1		T45	3		T55	2
valid_sources[0x70]	38	1		T41	1		T43	2		T61	2
valid_sources[0x71]	75	1		T41	1		T46	1		T61	1
valid_sources[0x72]	49	1		T85	1		T156	1		T45	2
valid_sources[0x73]	69	1		T45	2		T61	2		T39	6
valid_sources[0x74]	103	1		T173	1		T41	1		T45	3
valid_sources[0x75]	48	1		T77	2		T155	1		T177	6
valid_sources[0x76]	126	1		T45	1		T42	65		T61	2
valid_sources[0x77]	163	1		T161	1		T41	1		T46	2
valid_sources[0x78]	42	1		T77	1		T158	1		T45	6
valid_sources[0x79]	69	1		T85	1		T79	1		T41	2
valid_sources[0x7a]	85	1		T77	1		T178	3		T45	3
valid_sources[0x7b]	68	1		T45	4		T43	6		T57	9
valid_sources[0x7c]	52	1		T61	2		T172	3		T104	1
valid_sources[0x7d]	60	1		T45	1		T46	1		T38	1
valid_sources[0x7e]	82	1		T162	1		T41	1		T45	3
valid_sources[0x7f]	65	1		T179	3		T55	1		T38	1
valid_sources[0x80]	46	1		T45	1		T55	1		T43	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4498

1

T41

46

T44

12

T45

130

values[0x0]

all_enables

biggest_size

5630

1

T34

4

T47

1

T49

1

values[0x1]

all_enables

biggest_size

5626

1

T47

2

T48

1

T50

1