SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 726844 | 1 | T7 | 14 | T8 | 42 | T9 | 9 | |||
auto[1] | 13942 | 1 | T40 | 12 | T46 | 6 | T41 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 740595 | 1 | T7 | 14 | T8 | 42 | T9 | 9 | |||
values[1] | 21 | 1 | T40 | 2 | T87 | 3 | T88 | 2 | |||
values[2] | 6 | 1 | T88 | 2 | T148 | 2 | T119 | 1 | |||
values[3] | 99 | 1 | T40 | 3 | T41 | 1 | T42 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 740594 | 1 | T7 | 14 | T8 | 42 | T9 | 9 | |||
values[1] | 23 | 1 | T40 | 3 | T87 | 1 | T88 | 3 | |||
values[2] | 4 | 1 | T149 | 1 | T150 | 1 | T151 | 1 | |||
values[3] | 98 | 1 | T40 | 8 | T41 | 8 | T42 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 740486 | 1 | T7 | 14 | T8 | 42 | T9 | 9 | |||
auto[TlIntgErrCmd] | 108 | 1 | T40 | 8 | T41 | 1 | T42 | 1 | |||
auto[TlIntgErrData] | 109 | 1 | T40 | 9 | T41 | 6 | T42 | 5 | |||
auto[TlIntgErrBoth] | 83 | 1 | T40 | 3 | T41 | 3 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 24427 | 0 | T2 | 9 | T29 | 9 | T36 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 24215 | 1 | T2 | 9 | T29 | 9 | T36 | 12 | |||
values[1] | 22 | 1 | T87 | 1 | T152 | 1 | T148 | 2 | |||
values[2] | 8 | 1 | T42 | 1 | T88 | 2 | T153 | 1 | |||
values[3] | 109 | 1 | T40 | 12 | T41 | 4 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 24245 | 1 | T2 | 9 | T29 | 9 | T36 | 12 | |||
values[1] | 19 | 1 | T88 | 3 | T152 | 2 | T148 | 3 | |||
values[2] | 4 | 1 | T40 | 1 | T119 | 1 | T154 | 2 | |||
values[3] | 92 | 1 | T40 | 6 | T41 | 5 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 24127 | 1 | T2 | 9 | T29 | 9 | T36 | 12 | |||
auto[TlIntgErrCmd] | 118 | 1 | T40 | 7 | T41 | 3 | T42 | 4 | |||
auto[TlIntgErrData] | 88 | 1 | T40 | 6 | T41 | 5 | T42 | 1 | |||
auto[TlIntgErrBoth] | 94 | 1 | T40 | 7 | T41 | 2 | T42 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |