Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	226203	1		T7	9		T8	26		T9	8
full_word	514583	1		T7	5		T8	16		T9	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	740486	1		T7	14		T8	42		T9	9
auto[TlIntgErrCmd]	108	1		T40	8		T41	1		T42	1
auto[TlIntgErrData]	109	1		T40	9		T41	6		T42	5
auto[TlIntgErrBoth]	83	1		T40	3		T41	3		T42	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	456491	1		T8	18		T18	9		T5	36
auto[1]	284295	1		T7	14		T8	24		T9	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	186507	1		T8	7		T18	2		T5	16
auto[TlIntgErrNone]	partial	auto[1]	39420	1		T7	9		T8	19		T9	8
auto[TlIntgErrNone]	full_word	auto[0]	269843	1		T8	11		T18	7		T5	20
auto[TlIntgErrNone]	full_word	auto[1]	244716	1		T7	5		T8	5		T9	1
auto[TlIntgErrCmd]	partial	auto[0]	55	1		T40	3		T87	4		T88	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T40	4		T41	1		T42	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T87	1		T88	1		T119	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T40	1		T148	1		T150	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T40	4		T41	1		T42	3
auto[TlIntgErrData]	partial	auto[1]	55	1		T40	3		T41	5		T42	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T40	1		T149	1		T155	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T40	1		T152	1		T153	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T41	1		T42	2		T88	5
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T40	2		T41	2		T42	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T40	1		T148	1		T151	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T87	1		T153	1		T119	1