Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	193480	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	513478	1		T7	5		T8	16		T9	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	455161	1		T8	18		T18	9		T5	36
values[0x0]	123892	1		T7	12		T8	12		T9	6
values[0x1]	127905	1		T7	2		T8	12		T9	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147674	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	559284	1		T7	5		T8	21		T9	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2247	1		T7	1		T20	1		T40	35
valid_sources[0x01]	3227	1		T13	1		T21	1		T40	42
valid_sources[0x02]	2663	1		T40	30		T41	28		T55	2
valid_sources[0x03]	2576	1		T40	37		T46	1		T41	31
valid_sources[0x04]	2817	1		T5	43		T14	3		T93	1
valid_sources[0x05]	2311	1		T40	46		T46	1		T41	16
valid_sources[0x06]	2299	1		T5	33		T13	1		T40	35
valid_sources[0x07]	2391	1		T14	1		T21	1		T40	38
valid_sources[0x08]	2575	1		T40	44		T41	23		T55	3
valid_sources[0x09]	3113	1		T20	1		T14	1		T94	40
valid_sources[0x0a]	2693	1		T14	1		T93	3		T32	2
valid_sources[0x0b]	2703	1		T14	4		T40	32		T46	1
valid_sources[0x0c]	2354	1		T7	1		T21	3		T40	44
valid_sources[0x0d]	2420	1		T40	54		T46	4		T41	27
valid_sources[0x0e]	2905	1		T27	1		T14	3		T93	1
valid_sources[0x0f]	2709	1		T32	1		T33	1		T40	32
valid_sources[0x10]	2571	1		T7	1		T14	1		T40	37
valid_sources[0x11]	2945	1		T14	1		T40	42		T41	24
valid_sources[0x12]	2854	1		T32	1		T40	51		T46	2
valid_sources[0x13]	2760	1		T21	2		T32	1		T40	36
valid_sources[0x14]	2506	1		T27	1		T32	1		T40	51
valid_sources[0x15]	2803	1		T40	37		T41	35		T55	5
valid_sources[0x16]	3140	1		T40	42		T46	2		T41	19
valid_sources[0x17]	2348	1		T40	45		T46	1		T41	11
valid_sources[0x18]	2826	1		T20	1		T40	42		T46	2
valid_sources[0x19]	2550	1		T14	1		T40	44		T46	1
valid_sources[0x1a]	2529	1		T21	1		T40	38		T41	15
valid_sources[0x1b]	2391	1		T40	43		T46	1		T41	21
valid_sources[0x1c]	2524	1		T40	35		T46	1		T41	14
valid_sources[0x1d]	2527	1		T40	47		T41	20		T55	1
valid_sources[0x1e]	2766	1		T14	4		T40	40		T46	1
valid_sources[0x1f]	2826	1		T21	1		T40	25		T41	16
valid_sources[0x20]	2279	1		T21	1		T40	47		T41	22
valid_sources[0x21]	2756	1		T27	1		T20	1		T21	1
valid_sources[0x22]	2605	1		T40	47		T46	2		T41	19
valid_sources[0x23]	2322	1		T40	50		T41	18		T55	1
valid_sources[0x24]	2849	1		T40	36		T46	1		T41	19
valid_sources[0x25]	2417	1		T21	1		T32	1		T40	37
valid_sources[0x26]	2801	1		T40	44		T46	1		T41	17
valid_sources[0x27]	2465	1		T14	2		T40	44		T46	1
valid_sources[0x28]	2539	1		T27	1		T14	3		T40	43
valid_sources[0x29]	2255	1		T14	1		T21	1		T40	39
valid_sources[0x2a]	9690	1		T14	2		T33	1		T40	35
valid_sources[0x2b]	2730	1		T21	2		T40	52		T41	21
valid_sources[0x2c]	2499	1		T14	2		T21	1		T40	47
valid_sources[0x2d]	2432	1		T27	1		T40	45		T46	1
valid_sources[0x2e]	4319	1		T20	1		T14	3		T93	1
valid_sources[0x2f]	2794	1		T32	2		T40	37		T46	1
valid_sources[0x30]	2664	1		T9	2		T40	36		T46	3
valid_sources[0x31]	2793	1		T13	1		T14	1		T93	1
valid_sources[0x32]	2438	1		T32	1		T40	52		T46	3
valid_sources[0x33]	3098	1		T27	1		T40	45		T46	3
valid_sources[0x34]	2592	1		T21	1		T40	39		T46	1
valid_sources[0x35]	2436	1		T14	1		T40	42		T41	21
valid_sources[0x36]	2861	1		T8	42		T13	2		T21	1
valid_sources[0x37]	2497	1		T40	42		T46	2		T41	21
valid_sources[0x38]	2346	1		T14	3		T21	1		T40	41
valid_sources[0x39]	2389	1		T40	42		T46	1		T41	23
valid_sources[0x3a]	2405	1		T33	1		T40	43		T46	3
valid_sources[0x3b]	2705	1		T30	152		T40	48		T41	32
valid_sources[0x3c]	2861	1		T40	43		T46	2		T41	21
valid_sources[0x3d]	2650	1		T40	42		T41	21		T56	2
valid_sources[0x3e]	3428	1		T27	1		T21	1		T40	41
valid_sources[0x3f]	2522	1		T20	1		T146	1		T40	41
valid_sources[0x40]	2524	1		T14	4		T93	1		T40	42
valid_sources[0x41]	2939	1		T13	1		T40	43		T46	1
valid_sources[0x42]	2424	1		T14	3		T40	39		T46	3
valid_sources[0x43]	3840	1		T20	1		T40	46		T41	13
valid_sources[0x44]	2684	1		T40	53		T46	2		T41	17
valid_sources[0x45]	2711	1		T21	1		T40	48		T46	1
valid_sources[0x46]	2405	1		T146	3		T40	38		T41	17
valid_sources[0x47]	2383	1		T27	1		T14	7		T40	40
valid_sources[0x48]	2572	1		T40	47		T41	31		T55	2
valid_sources[0x49]	2195	1		T13	1		T93	2		T40	28
valid_sources[0x4a]	2590	1		T40	34		T46	1		T41	28
valid_sources[0x4b]	2507	1		T27	1		T14	1		T40	50
valid_sources[0x4c]	2717	1		T27	1		T14	1		T21	1
valid_sources[0x4d]	2753	1		T33	1		T40	29		T41	26
valid_sources[0x4e]	2428	1		T21	1		T40	38		T46	3
valid_sources[0x4f]	2797	1		T27	1		T14	1		T32	8
valid_sources[0x50]	2116	1		T40	38		T41	32		T55	5
valid_sources[0x51]	2820	1		T13	2		T14	3		T40	37
valid_sources[0x52]	2733	1		T32	2		T40	51		T41	7
valid_sources[0x53]	2548	1		T14	2		T40	32		T41	31
valid_sources[0x54]	2325	1		T20	1		T40	46		T41	19
valid_sources[0x55]	3235	1		T40	50		T46	4		T41	20
valid_sources[0x56]	2407	1		T21	1		T40	38		T41	18
valid_sources[0x57]	2381	1		T40	33		T46	3		T41	18
valid_sources[0x58]	2718	1		T40	53		T41	26		T56	1
valid_sources[0x59]	2693	1		T13	2		T157	1		T40	46
valid_sources[0x5a]	2632	1		T40	42		T46	2		T41	18
valid_sources[0x5b]	2895	1		T27	1		T21	2		T32	4
valid_sources[0x5c]	2915	1		T14	1		T40	50		T41	25
valid_sources[0x5d]	2513	1		T13	1		T40	34		T46	1
valid_sources[0x5e]	2988	1		T32	4		T40	31		T46	1
valid_sources[0x5f]	2805	1		T13	1		T14	1		T33	1
valid_sources[0x60]	2375	1		T40	37		T46	1		T41	19
valid_sources[0x61]	2746	1		T20	1		T93	2		T21	1
valid_sources[0x62]	2813	1		T14	2		T40	52		T46	2
valid_sources[0x63]	2508	1		T40	29		T46	2		T41	15
valid_sources[0x64]	2545	1		T7	1		T40	35		T41	16
valid_sources[0x65]	2289	1		T20	1		T21	1		T40	49
valid_sources[0x66]	2753	1		T27	1		T32	2		T158	2
valid_sources[0x67]	3212	1		T21	1		T32	1		T40	35
valid_sources[0x68]	2394	1		T32	1		T40	29		T46	1
valid_sources[0x69]	2496	1		T9	1		T13	1		T40	42
valid_sources[0x6a]	2526	1		T40	36		T41	24		T55	1
valid_sources[0x6b]	2684	1		T40	43		T46	2		T41	18
valid_sources[0x6c]	2713	1		T40	39		T46	5		T41	24
valid_sources[0x6d]	2285	1		T21	1		T40	45		T46	1
valid_sources[0x6e]	2470	1		T13	1		T14	3		T157	3
valid_sources[0x6f]	2621	1		T5	8		T14	1		T21	2
valid_sources[0x70]	2811	1		T14	5		T40	34		T41	24
valid_sources[0x71]	2543	1		T20	1		T93	3		T40	50
valid_sources[0x72]	2553	1		T27	1		T14	3		T21	1
valid_sources[0x73]	2325	1		T9	1		T14	1		T40	45
valid_sources[0x74]	2676	1		T13	1		T40	51		T41	26
valid_sources[0x75]	2651	1		T32	2		T40	43		T46	1
valid_sources[0x76]	2533	1		T27	1		T21	1		T40	39
valid_sources[0x77]	2753	1		T14	2		T40	43		T46	3
valid_sources[0x78]	3817	1		T13	1		T21	1		T40	37
valid_sources[0x79]	2516	1		T40	35		T46	1		T41	25
valid_sources[0x7a]	2763	1		T40	44		T46	1		T41	23
valid_sources[0x7b]	2720	1		T27	1		T20	1		T40	51
valid_sources[0x7c]	2949	1		T21	3		T40	42		T46	2
valid_sources[0x7d]	3018	1		T32	1		T40	48		T46	1
valid_sources[0x7e]	2273	1		T40	32		T46	1		T41	25
valid_sources[0x7f]	2552	1		T20	1		T40	48		T46	1
valid_sources[0x80]	2435	1		T32	2		T40	45		T46	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

269720

1

T8

11

T18

7

T5

20

values[0x0]

all_enables

biggest_size

122238

1

T7

4

T8

4

T9

1

values[0x1]

all_enables

biggest_size

121520

1

T7

1

T8

1

T27

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1850	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	13364	1		T2	3		T29	2		T36	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4646	1		T40	29		T46	6		T41	15
values[0x0]	5236	1		T2	3		T29	5		T36	6
values[0x1]	5332	1		T2	6		T29	4		T36	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1424	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	13790	1		T2	3		T29	2		T36	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32	1		T159	1		T160	1		T55	1
valid_sources[0x01]	48	1		T54	1		T161	1		T44	2
valid_sources[0x02]	33	1		T44	2		T42	1		T95	1
valid_sources[0x03]	43	1		T162	1		T163	2		T44	2
valid_sources[0x04]	105	1		T48	7		T55	1		T60	1
valid_sources[0x05]	83	1		T164	1		T44	3		T60	1
valid_sources[0x06]	70	1		T79	2		T165	1		T55	4
valid_sources[0x07]	47	1		T159	1		T166	2		T44	2
valid_sources[0x08]	45	1		T167	4		T44	1		T91	1
valid_sources[0x09]	36	1		T44	1		T42	1		T45	3
valid_sources[0x0a]	39	1		T162	1		T44	3		T60	3
valid_sources[0x0b]	47	1		T41	5		T44	2		T60	1
valid_sources[0x0c]	40	1		T168	1		T169	11		T45	1
valid_sources[0x0d]	29	1		T44	3		T60	1		T45	1
valid_sources[0x0e]	39	1		T170	1		T44	2		T45	1
valid_sources[0x0f]	56	1		T44	2		T60	1		T96	1
valid_sources[0x10]	237	1		T171	4		T44	2		T92	4
valid_sources[0x11]	32	1		T44	2		T42	1		T92	1
valid_sources[0x12]	76	1		T51	4		T159	1		T41	8
valid_sources[0x13]	54	1		T40	12		T44	2		T60	1
valid_sources[0x14]	43	1		T79	1		T44	3		T92	2
valid_sources[0x15]	42	1		T172	1		T44	3		T60	1
valid_sources[0x16]	85	1		T173	1		T40	2		T60	1
valid_sources[0x17]	233	1		T78	1		T174	6		T164	2
valid_sources[0x18]	68	1		T160	1		T40	10		T45	2
valid_sources[0x19]	32	1		T44	3		T105	4		T175	1
valid_sources[0x1a]	36	1		T55	2		T44	3		T60	1
valid_sources[0x1b]	52	1		T173	1		T60	1		T45	1
valid_sources[0x1c]	61	1		T159	1		T44	4		T60	1
valid_sources[0x1d]	32	1		T44	2		T45	3		T92	1
valid_sources[0x1e]	58	1		T53	3		T173	1		T44	1
valid_sources[0x1f]	27	1		T44	1		T92	2		T103	1
valid_sources[0x20]	33	1		T159	1		T44	1		T59	2
valid_sources[0x21]	69	1		T40	1		T44	3		T60	1
valid_sources[0x22]	52	1		T166	1		T44	1		T60	3
valid_sources[0x23]	48	1		T44	1		T95	1		T45	1
valid_sources[0x24]	61	1		T78	2		T159	1		T44	3
valid_sources[0x25]	55	1		T159	1		T55	1		T44	2
valid_sources[0x26]	41	1		T78	1		T44	2		T60	1
valid_sources[0x27]	60	1		T44	2		T60	1		T92	2
valid_sources[0x28]	45	1		T40	9		T44	1		T60	1
valid_sources[0x29]	62	1		T176	8		T45	3		T92	3
valid_sources[0x2a]	42	1		T51	2		T55	2		T95	1
valid_sources[0x2b]	51	1		T44	1		T45	1		T92	8
valid_sources[0x2c]	42	1		T54	1		T44	2		T60	2
valid_sources[0x2d]	86	1		T167	1		T40	1		T55	5
valid_sources[0x2e]	83	1		T163	1		T44	2		T60	1
valid_sources[0x2f]	77	1		T160	1		T44	2		T42	1
valid_sources[0x30]	60	1		T177	1		T178	1		T44	2
valid_sources[0x31]	51	1		T45	1		T92	3		T102	1
valid_sources[0x32]	64	1		T44	1		T95	1		T45	1
valid_sources[0x33]	46	1		T166	1		T41	2		T60	1
valid_sources[0x34]	37	1		T54	1		T159	1		T91	6
valid_sources[0x35]	68	1		T160	1		T44	1		T45	2
valid_sources[0x36]	38	1		T160	1		T44	1		T92	9
valid_sources[0x37]	38	1		T179	1		T170	1		T55	1
valid_sources[0x38]	30	1		T165	1		T164	1		T161	1
valid_sources[0x39]	30	1		T96	1		T92	3		T103	1
valid_sources[0x3a]	47	1		T44	1		T45	2		T92	3
valid_sources[0x3b]	42	1		T44	2		T91	3		T92	7
valid_sources[0x3c]	43	1		T160	1		T44	4		T42	3
valid_sources[0x3d]	72	1		T36	6		T54	1		T173	1
valid_sources[0x3e]	73	1		T95	1		T91	1		T45	2
valid_sources[0x3f]	37	1		T41	1		T92	3		T104	3
valid_sources[0x40]	85	1		T180	1		T46	18		T45	1
valid_sources[0x41]	44	1		T48	1		T161	1		T45	1
valid_sources[0x42]	33	1		T55	2		T44	1		T45	1
valid_sources[0x43]	48	1		T44	1		T60	1		T91	1
valid_sources[0x44]	44	1		T44	2		T60	3		T45	4
valid_sources[0x45]	54	1		T162	1		T40	8		T44	2
valid_sources[0x46]	37	1		T181	2		T44	2		T60	3
valid_sources[0x47]	35	1		T44	1		T60	1		T42	1
valid_sources[0x48]	52	1		T44	1		T60	1		T91	1
valid_sources[0x49]	69	1		T43	17		T44	1		T92	5
valid_sources[0x4a]	58	1		T160	1		T167	2		T55	1
valid_sources[0x4b]	37	1		T162	1		T60	1		T88	1
valid_sources[0x4c]	48	1		T173	1		T55	2		T44	1
valid_sources[0x4d]	76	1		T78	1		T159	1		T92	6
valid_sources[0x4e]	50	1		T159	1		T166	1		T55	4
valid_sources[0x4f]	45	1		T79	1		T40	1		T45	1
valid_sources[0x50]	45	1		T170	1		T44	2		T92	3
valid_sources[0x51]	66	1		T173	1		T160	1		T44	1
valid_sources[0x52]	39	1		T170	1		T163	1		T45	1
valid_sources[0x53]	48	1		T44	3		T92	5		T102	2
valid_sources[0x54]	53	1		T160	1		T162	1		T55	2
valid_sources[0x55]	35	1		T44	2		T42	1		T45	1
valid_sources[0x56]	92	1		T159	1		T182	9		T44	4
valid_sources[0x57]	59	1		T160	1		T167	3		T44	2
valid_sources[0x58]	60	1		T180	2		T44	4		T91	2
valid_sources[0x59]	45	1		T36	1		T51	4		T44	3
valid_sources[0x5a]	54	1		T183	2		T173	1		T44	1
valid_sources[0x5b]	51	1		T178	1		T44	5		T60	2
valid_sources[0x5c]	50	1		T48	1		T44	1		T42	1
valid_sources[0x5d]	154	1		T184	2		T55	2		T92	2
valid_sources[0x5e]	190	1		T161	1		T44	1		T45	2
valid_sources[0x5f]	40	1		T44	1		T60	1		T45	2
valid_sources[0x60]	59	1		T178	1		T44	2		T60	3
valid_sources[0x61]	48	1		T44	1		T97	2		T91	2
valid_sources[0x62]	72	1		T51	2		T159	1		T162	1
valid_sources[0x63]	126	1		T62	48		T44	1		T97	2
valid_sources[0x64]	101	1		T44	1		T97	9		T45	1
valid_sources[0x65]	34	1		T159	1		T60	1		T45	1
valid_sources[0x66]	47	1		T54	1		T178	1		T44	2
valid_sources[0x67]	32	1		T92	3		T102	1		T105	1
valid_sources[0x68]	45	1		T177	2		T55	1		T44	2
valid_sources[0x69]	43	1		T171	1		T55	1		T103	1
valid_sources[0x6a]	59	1		T185	1		T44	1		T91	1
valid_sources[0x6b]	66	1		T44	4		T60	1		T95	1
valid_sources[0x6c]	54	1		T170	1		T40	5		T60	1
valid_sources[0x6d]	59	1		T168	1		T55	1		T44	3
valid_sources[0x6e]	58	1		T55	2		T56	1		T91	2
valid_sources[0x6f]	36	1		T44	2		T42	1		T97	1
valid_sources[0x70]	38	1		T60	1		T97	1		T92	1
valid_sources[0x71]	34	1		T45	1		T92	8		T175	1
valid_sources[0x72]	33	1		T185	1		T55	3		T44	1
valid_sources[0x73]	68	1		T90	1		T44	1		T97	2
valid_sources[0x74]	24	1		T185	1		T160	1		T45	1
valid_sources[0x75]	50	1		T168	1		T163	1		T44	3
valid_sources[0x76]	47	1		T166	1		T55	3		T57	5
valid_sources[0x77]	38	1		T183	1		T44	1		T42	1
valid_sources[0x78]	56	1		T55	3		T44	3		T45	2
valid_sources[0x79]	37	1		T36	1		T178	1		T44	1
valid_sources[0x7a]	128	1		T177	7		T96	1		T45	2
valid_sources[0x7b]	39	1		T44	6		T92	1		T104	3
valid_sources[0x7c]	47	1		T161	1		T44	1		T60	3
valid_sources[0x7d]	42	1		T185	1		T60	2		T42	1
valid_sources[0x7e]	147	1		T185	1		T60	1		T42	1
valid_sources[0x7f]	44	1		T159	1		T180	2		T162	1
valid_sources[0x80]	31	1		T166	1		T44	3		T92	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3801

1

T40

4

T46

5

T41

3

values[0x0]

all_enables

biggest_size

4845

1

T2

1

T29

2

T36

2

values[0x1]

all_enables

biggest_size

4718

1

T2

2

T51

3

T52

1