Module Definition
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Module : debug_rom
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 75.00

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dm_top.i_dm_mem.gen_rom_snd_scratch.i_debug_rom 87.50 100.00 75.00



Module Instance : tb.dut.u_dm_top.i_dm_mem.gen_rom_snd_scratch.i_debug_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
73.98 78.42 50.00 100.00 67.50 i_dm_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : debug_rom
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS5322100.00
ALWAYS6133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
54 1 1
MISSING_ELSE
61 1 1
62 1 1
63 1 1
==> MISSING_ELSE


Branch Coverage for Module : debug_rom
Line No.TotalCoveredPercent
Branches 4 3 75.00
IF 53 2 2 100.00
IF 62 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 53 if (req_i)

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 62 if ((addr_q < 5'(RomSize)))

Branches:
-1-StatusTests
1 Covered T7,T8,T9
0 Not Covered

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