93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 0 | 2 | 0.00 | ||
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0 | 20 | 0.00 | ||
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 0 | 20 | 0.00 | ||
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 0 | 2 | 0.00 | ||
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0 | 2 | 0.00 | ||
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0 | 2 | 0.00 | ||
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0 | 2 | 0.00 | ||
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0 | 2 | 0.00 | ||
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0 | 2 | 0.00 | ||
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0 | 2 | 0.00 | ||
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0 | 2 | 0.00 | ||
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rv_dm_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | mem_walk | rv_dm_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 153 | 0.00 | |||
| V2 | idcode | rv_dm_smoke | 0 | 2 | 0.00 | ||
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0 | 2 | 0.00 | ||
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0 | 2 | 0.00 | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0 | 2 | 0.00 | ||
| V2 | sba | rv_dm_sba_tl_access | 0 | 20 | 0.00 | ||
| rv_dm_delayed_resp_sba_tl_access | 0 | 20 | 0.00 | ||||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 0 | 20 | 0.00 | ||
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 0 | 20 | 0.00 | ||
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0 | 2 | 0.00 | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0 | 2 | 0.00 | ||
| V2 | hart_unavail | rv_dm_hart_unavail | 0 | 5 | 0.00 | ||
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 0 | 1 | 0.00 | ||
| rv_dm_tap_fsm_rand_reset | 0 | 40 | 0.00 | ||||
| V2 | stress_all | rv_dm_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | rv_dm_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 276 | 0.00 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 0 | 5 | 0.00 | ||
| rv_dm_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 504 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 24 | 24 | 0 | 0.00 |
| V2 | 18 | 16 | 0 | 0.00 |
| V2S | 8 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 506 failures:
Test rv_dm_csr_aliasing has 5 failures.
0.rv_dm_csr_aliasing.39856635542070751172168270110148829945136874041284800583033305332914069547100
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log
1.rv_dm_csr_aliasing.54309197335252605799703834168499823561372754736641988662823619101234391764843
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest/run.log
... and 3 more failures.
Test rv_dm_smoke has 2 failures.
0.rv_dm_smoke.115616014147085317863890715670532656564079888968909883716529488012515672340763
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log
1.rv_dm_smoke.100868381763538581075761089181744938249281502708753125706816352436032760599250
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log
Test rv_dm_tap_fsm has 1 failures.
Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.
0.rv_dm_jtag_dtm_csr_hw_reset.97291568185653364925805994261211925369955729744184649514745487623275829013637
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
1.rv_dm_jtag_dtm_csr_hw_reset.115764802659063924137513388217284466937959822616400756832436128145817278329580
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
... and 3 more failures.
Test rv_dm_jtag_dtm_csr_rw has 20 failures.
0.rv_dm_jtag_dtm_csr_rw.96047988850628698047935601920841444898087468225945431510716618237856983186829
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log
1.rv_dm_jtag_dtm_csr_rw.90238181530960653662596069332595523600615130304384143861803445927676233253817
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest/run.log
... and 18 more failures.
... and 39 more tests.
Job rv_dm-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/build.log
Job ID: smart:fc09c3a4-d2b2-4e90-804c-6160204f0ee1
Job rv_dm-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/default/build.log
Job ID: smart:4056ad55-e11a-4e29-b4dc-4ed99aa19542