Unified Coverage Report :: Module :: rv_dm_regs_reg_top

Module : rv_dm_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.14	75.00	82.14			71.43	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	82.14	75.00	82.14			71.43	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.14	75.00	82.14			71.43	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.73	93.50	93.58	93.49		93.10	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.73	100.00	75.86	91.55			87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	97.78	100.00		93.33			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.66	97.10	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		24	18	75.00
ALWAYS	67	4	4	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	117	1	0	0.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
ALWAYS	150	2	0	0.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	158	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
ALWAYS	169	2	2	100.00
ALWAYS	175	3	0	0.00
CONT_ASSIGN	192	0	0
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
67	1	1
68	1	1
69	1	1
70	1	1
			MISSING_ELSE
76	1	1
88	1	1
89	1	1
117	0	1
118	1	1
130	1	1
144	1	1
150	0	1
151	0	1
154	1	1
158	1	1
163	1	1
165	1	1
169	1	1
170	1	1
175	0	1
176	0	1
178	0	1
192		unreachable
200	1	1
201	1	1

---

Cond Coverage for Module : rv_dm_regs_reg_top

	Total	Covered	Percent
Conditions	28	23	82.14
Logical	28	23	82.14
Non-Logical	0	0
Event	0	0

 LINE       57
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T33,T36

 LINE       69
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T37,T38,T39
1	0	Covered	T40,T41,T42

 LINE       76
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T37,T38,T39
0	1	0	Covered	T40,T41,T42
1	0	0	Covered	T37,T38,T39

 LINE       118
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T40,T41,T42
0	1	0	Covered	T43,T44,T45
1	0	0	Not Covered

 LINE       151
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       154
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T33,T36

 LINE       154
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T33,T36
1	0	Covered	T46,T47,T48

 LINE       158
 EXPRESSION (reg_we & addr_hit[0] & ((|(4'b1 & (~reg_be)))))
             ---1--   -----2-----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T49,T50
1	0	1	Not Covered
1	1	0	Covered	T2,T33,T36
1	1	1	Covered	T43,T40,T44

 LINE       163
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T43,T40,T44
1	1	1	Covered	T2,T33,T36

---

Branch Coverage for Module : rv_dm_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	154	2	2	100.00
IF	67	3	3	100.00
CASE	176	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	154	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T33,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	67	if ((!rst_ni))
-2-:	69	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T37,T38,T39
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Not Covered
default	Not Covered

---

Assert Coverage for Module : rv_dm_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	54072546	2697	0	0
reAfterRv	54072546	2697	0	0
rePulse	54072546	1139	0	0
wePulse	54072546	1558	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	54072546	2697	0	0
T2	1204	4	0	0
T3	24213	0	0	0
T4	274531	0	0	0
T9	2012	0	0	0
T11	66146	0	0	0
T14	133947	0	0	0
T17	36518	0	0	0
T23	2208	0	0	0
T31	0	16	0	0
T32	292839	0	0	0
T33	2301	10	0	0
T36	0	4	0	0
T51	0	2	0	0
T52	0	9	0	0
T53	0	3	0	0
T54	0	8	0	0
T55	0	20	0	0
T56	0	12	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	54072546	2697	0	0
T2	1204	4	0	0
T3	24213	0	0	0
T4	274531	0	0	0
T9	2012	0	0	0
T11	66146	0	0	0
T14	133947	0	0	0
T17	36518	0	0	0
T23	2208	0	0	0
T31	0	16	0	0
T32	292839	0	0	0
T33	2301	10	0	0
T36	0	4	0	0
T51	0	2	0	0
T52	0	9	0	0
T53	0	3	0	0
T54	0	8	0	0
T55	0	20	0	0
T56	0	12	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	54072546	1139	0	0
T40	50387	13	0	0
T41	39261	13	0	0
T44	201283	2	0	0
T46	484106	128	0	0
T47	4433	1	0	0
T48	5244	1	0	0
T57	9508	2	0	0
T58	6004	1	0	0
T59	7108	3	0	0
T60	14187	16	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	54072546	1558	0	0
T2	1204	4	0	0
T3	24213	0	0	0
T4	274531	0	0	0
T9	2012	0	0	0
T11	66146	0	0	0
T14	133947	0	0	0
T17	36518	0	0	0
T23	2208	0	0	0
T31	0	16	0	0
T32	292839	0	0	0
T33	2301	10	0	0
T36	0	4	0	0
T51	0	2	0	0
T52	0	9	0	0
T53	0	3	0	0
T54	0	8	0	0
T55	0	20	0	0
T56	0	12	0	0