Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.73 100.00 75.86 91.55 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 88.73 100.00 75.86 91.55 87.50



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.73 100.00 75.86 91.55 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.55 92.79 78.70 89.36 78.21 82.48 97.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 86.60 98.68 92.76 72.00 94.57 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 0.00 0.00
tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 94.54 100.00 85.71 97.90
tlul_assert_host_sba 94.30 100.00 85.71 97.18
u_dm_top 84.06 86.52 62.98 100.00 70.78 100.00
u_lc_en_sync 100.00 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
u_reg_regs 94.73 93.50 93.58 93.49 93.10 100.00
u_tlul_lc_gate_rom 83.22 93.94 57.50 100.00 77.14 87.50
u_tlul_lc_gate_sba 72.24 90.15 55.00 57.14 71.43 87.50


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN30811100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN38411100.00
CONT_ASSIGN41211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
109 1 1
110 1 1
115 1 1
118 1 1
141 1 1
206 1 1
207 1 1
211 1 1
294 1 1
300 1 1
302 1 1
308 1 1
309 1 1
384 1 1
412 1 1


Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions292275.86
Logical292275.86
Non-Logical00
Event00

 LINE       115
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT37,T38,T39

 LINE       118
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT2,T33,T36
10CoveredT2,T3,T11
11CoveredT2,T33,T36

 LINE       207
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T27,T25

 LINE       302
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T7,T26

 LINE       337
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T27,T25
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       412
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T27,T19
10CoveredT4,T7,T5

 LINE       428
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       428
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T27,T25
11CoveredT1,T2,T3

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 94 75 79.79
Total Bits 1112 1018 91.55
Total Bits 0->1 556 509 91.55
Total Bits 1->0 556 509 91.55

Ports 94 75 79.79
Port Bits 1112 1018 91.55
Port Bits 0->1 556 509 91.55
Port Bits 1->0 556 509 91.55

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T14 Yes T1,T2,T3 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T20,T34,T35 Yes T27,T20,T34 INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T20,T34,T35 Yes T27,T20,T34 INPUT
scanmode_i[0] No No Yes T4,T27,T25 INPUT
scanmode_i[2:1] No Yes T4,T27,T25 No INPUT
scanmode_i[3] No No Yes T4,T27,T25 INPUT
scan_rst_ni Yes Yes T1,T4,T14 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T26,T27,T25 Yes T26,T27,T25 OUTPUT
dmactive_o Yes Yes T1,T4,T14 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T4,T7,T26 Yes T4,T7,T26 OUTPUT
unavailable_i Yes Yes T4,T9,T10 Yes T4,T9,T10 INPUT
regs_tl_d_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T2,T3,T32 Yes T2,T33,T36 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T2,T33,T36 Yes T2,T33,T49 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T11,T33,T50 Yes T33,T49,T37 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T33,T37,T51 Yes T3,T11,T32 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T2,T11,T32 Yes T2,T33,T36 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T33,T50,T37 Yes T11,T33,T37 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T11,T33,T37 Yes T33,T37,T65 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T3,T33,T49 Yes T32,T33,T37 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T11,T33,T37 Yes T2,T33,T36 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T3,T33,T37 Yes T33,T37,T6 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T33,T49,T36 Yes T2,T33,T36 INPUT
regs_tl_d_i.a_valid Yes Yes T2,T33,T36 Yes T2,T33,T36 INPUT
regs_tl_d_o.a_ready Yes Yes T2,T33,T36 Yes T2,T33,T36 OUTPUT
regs_tl_d_o.d_error Yes Yes T40,T44,T41 Yes T43,T40,T44 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] No No No OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T33,*T36,*T31 Yes T2,T33,T36 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T46,T47,T48 Yes T2,T33,T36 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T33,T36,T52 Yes T2,T33,T36 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T33,T31,T52 Yes T2,T33,T36 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T46,*T43,*T40 Yes T46,T47,T48 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T2,T33,T36 Yes T2,T33,T36 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T1,T2,T10 Yes T1,T33,T5 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T4,T7 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T1,T2,T31 Yes T1,T66,T6 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T1,T33,T6 Yes T1,T2,T10 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T1,T10,T31 Yes T1,T5,T6 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T1,T10,T6 Yes T1,T6,T55 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T1,T66,T6 Yes T1,T2,T10 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T1,T2,T33 Yes T1,T4,T7 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T1,T4,T7 Yes T1,T2,T4 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T1,T33,T10 Yes T1,T31,T66 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T1,T2,T4 Yes T1,T4,T7 INPUT
mem_tl_d_i.a_valid Yes Yes T4,T7,T5 Yes T4,T7,T5 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T1,T4,T14 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T16,T27,T19 Yes T16,T27,T19 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes T4,*T7,*T6 Yes T4,T7,T5 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T4,T14 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T4,T7,T16 Yes T4,T7,T5 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T4,T7,T5 Yes T4,T7,T5 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T4,T14 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T4,T7,T5 Yes T4,T7,T5 OUTPUT
sba_tl_h_o.d_ready Yes Yes T1,T4,T14 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T1,T3,T11 Yes T1,T3,T11 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T1,T3,T11 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T1,*T4,*T14 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T1,T4,T14 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T1,T3,T11 Yes T1,T3,T11 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T1,T3,T11 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T1,T3,T11 Yes T1,T3,T11 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T1,T4,T14 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T1,*T3,*T11 Yes T1,T3,T11 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T1,T3,T11 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T1,T3,T11 Yes T1,T3,T11 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T1,T14,T17 Yes T1,T14,T15 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T1,T3,T11 Yes T1,T3,T11 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T11 Yes T1,T3,T11 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T1,T3,T11 Yes T1,T3,T11 INPUT
sba_tl_h_i.d_sink Yes Yes T1,T3,T11 Yes T1,T3,T11 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T14,T17,T15 Yes T14,T15,T67 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T1,T14,T15 Yes T1,T14,T15 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T14,T15,T67 Yes T14,T17,T15 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T1,T3,T11 Yes T1,T3,T11 INPUT
sba_tl_h_i.d_valid Yes Yes T1,T3,T11 Yes T1,T3,T11 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T33,T36 Yes T2,T33,T36 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T33,T36 Yes T2,T33,T36 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T1,T4,T14 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 30798732 30755436 0 0
DmactiveOKnown_A 30798732 30755436 0 0
FpvSecCmRegWeOnehotCheck_A 30798732 80 0 0
FpvSecCmRomTlLcGateFsm_A 30798732 0 0 0
FpvSecCmSbaTlLcGateFsm_A 30798732 0 0 0
JtagRspOTdoKnown_A 13230033 13229644 0 0
JtagRspOTdoOeKnown_A 13230033 13229644 0 0
NdmresetOKnown_A 30798732 30755436 0 0
RvDmLcEnDebugVal_A 30798732 30755436 0 0
TlMemAReadyKnown_A 30798732 30755436 0 0
TlMemDValidKnown_A 30798732 30755436 0 0
TlRegsAReadyKnown_A 30798732 30755436 0 0
TlRegsDValidKnown_A 30798732 30755436 0 0
TlSbaAValidKnown_A 30798732 30755436 0 0
TlSbaDReadyKnown_A 30798732 30755436 0 0
paramCheckNrHarts 166 166 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 80 0 0
T5 10835 0 0 0
T7 82173 0 0 0
T10 2598 0 0 0
T31 1206 0 0 0
T37 8149 20 0 0
T38 0 20 0 0
T39 0 20 0 0
T51 1247 0 0 0
T66 136718 0 0 0
T68 0 10 0 0
T69 0 10 0 0
T70 9450 0 0 0
T71 69826 0 0 0
T72 168518 0 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13230033 13229644 0 0
T1 901070 901001 0 0
T2 116 116 0 0
T3 180308 180308 0 0
T4 70749 70748 0 0
T9 1690 1690 0 0
T11 189086 189086 0 0
T14 176110 176095 0 0
T17 9502 9502 0 0
T32 180228 180228 0 0
T33 119 119 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13230033 13229644 0 0
T1 901070 901001 0 0
T2 116 116 0 0
T3 180308 180308 0 0
T4 70749 70748 0 0
T9 1690 1690 0 0
T11 189086 189086 0 0
T14 176110 176095 0 0
T17 9502 9502 0 0
T32 180228 180228 0 0
T33 119 119 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 30798732 30755436 0 0
T1 409098 404387 0 0
T2 1204 1124 0 0
T3 24213 24146 0 0
T4 274531 274125 0 0
T9 2012 1947 0 0
T11 66146 66054 0 0
T14 133947 132925 0 0
T17 36518 36434 0 0
T32 292839 292753 0 0
T33 2301 2229 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 166 166 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T17 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%