SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 664 | 664 | 0 | 0 |
OutputsKnown_A | 123194928 | 123021744 | 0 | 0 |
gen_flops.OutputDelay_A | 61597464 | 61506972 | 0 | 996 |
gen_no_flops.OutputDelay_A | 61597464 | 61510872 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 664 | 664 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T9 | 4 | 4 | 0 | 0 |
T11 | 4 | 4 | 0 | 0 |
T14 | 4 | 4 | 0 | 0 |
T17 | 4 | 4 | 0 | 0 |
T32 | 4 | 4 | 0 | 0 |
T33 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 123194928 | 123021744 | 0 | 0 |
T1 | 1636392 | 1617548 | 0 | 0 |
T2 | 4816 | 4496 | 0 | 0 |
T3 | 96852 | 96584 | 0 | 0 |
T4 | 1098124 | 1096500 | 0 | 0 |
T9 | 8048 | 7788 | 0 | 0 |
T11 | 264584 | 264216 | 0 | 0 |
T14 | 535788 | 531700 | 0 | 0 |
T17 | 146072 | 145736 | 0 | 0 |
T32 | 1171356 | 1171012 | 0 | 0 |
T33 | 9204 | 8916 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 61597464 | 61506972 | 0 | 996 |
T1 | 818196 | 808354 | 0 | 6 |
T2 | 2408 | 2242 | 0 | 6 |
T3 | 48426 | 48286 | 0 | 6 |
T4 | 549062 | 548214 | 0 | 6 |
T9 | 4024 | 3888 | 0 | 6 |
T11 | 132292 | 132102 | 0 | 6 |
T14 | 267894 | 265754 | 0 | 6 |
T17 | 73036 | 72862 | 0 | 6 |
T32 | 585678 | 585500 | 0 | 6 |
T33 | 4602 | 4452 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 61597464 | 61510872 | 0 | 0 |
T1 | 818196 | 808774 | 0 | 0 |
T2 | 2408 | 2248 | 0 | 0 |
T3 | 48426 | 48292 | 0 | 0 |
T4 | 549062 | 548250 | 0 | 0 |
T9 | 4024 | 3894 | 0 | 0 |
T11 | 132292 | 132108 | 0 | 0 |
T14 | 267894 | 265850 | 0 | 0 |
T17 | 73036 | 72868 | 0 | 0 |
T32 | 585678 | 585506 | 0 | 0 |
T33 | 4602 | 4458 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 30798732 | 30755436 | 0 | 0 |
gen_flops.OutputDelay_A | 30798732 | 30753486 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30755436 | 0 | 0 |
T1 | 409098 | 404387 | 0 | 0 |
T2 | 1204 | 1124 | 0 | 0 |
T3 | 24213 | 24146 | 0 | 0 |
T4 | 274531 | 274125 | 0 | 0 |
T9 | 2012 | 1947 | 0 | 0 |
T11 | 66146 | 66054 | 0 | 0 |
T14 | 133947 | 132925 | 0 | 0 |
T17 | 36518 | 36434 | 0 | 0 |
T32 | 292839 | 292753 | 0 | 0 |
T33 | 2301 | 2229 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30753486 | 0 | 498 |
T1 | 409098 | 404177 | 0 | 3 |
T2 | 1204 | 1121 | 0 | 3 |
T3 | 24213 | 24143 | 0 | 3 |
T4 | 274531 | 274107 | 0 | 3 |
T9 | 2012 | 1944 | 0 | 3 |
T11 | 66146 | 66051 | 0 | 3 |
T14 | 133947 | 132877 | 0 | 3 |
T17 | 36518 | 36431 | 0 | 3 |
T32 | 292839 | 292750 | 0 | 3 |
T33 | 2301 | 2226 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 30798732 | 30755436 | 0 | 0 |
gen_flops.OutputDelay_A | 30798732 | 30753486 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30755436 | 0 | 0 |
T1 | 409098 | 404387 | 0 | 0 |
T2 | 1204 | 1124 | 0 | 0 |
T3 | 24213 | 24146 | 0 | 0 |
T4 | 274531 | 274125 | 0 | 0 |
T9 | 2012 | 1947 | 0 | 0 |
T11 | 66146 | 66054 | 0 | 0 |
T14 | 133947 | 132925 | 0 | 0 |
T17 | 36518 | 36434 | 0 | 0 |
T32 | 292839 | 292753 | 0 | 0 |
T33 | 2301 | 2229 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30753486 | 0 | 498 |
T1 | 409098 | 404177 | 0 | 3 |
T2 | 1204 | 1121 | 0 | 3 |
T3 | 24213 | 24143 | 0 | 3 |
T4 | 274531 | 274107 | 0 | 3 |
T9 | 2012 | 1944 | 0 | 3 |
T11 | 66146 | 66051 | 0 | 3 |
T14 | 133947 | 132877 | 0 | 3 |
T17 | 36518 | 36431 | 0 | 3 |
T32 | 292839 | 292750 | 0 | 3 |
T33 | 2301 | 2226 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 30798732 | 30755436 | 0 | 0 |
gen_no_flops.OutputDelay_A | 30798732 | 30755436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30755436 | 0 | 0 |
T1 | 409098 | 404387 | 0 | 0 |
T2 | 1204 | 1124 | 0 | 0 |
T3 | 24213 | 24146 | 0 | 0 |
T4 | 274531 | 274125 | 0 | 0 |
T9 | 2012 | 1947 | 0 | 0 |
T11 | 66146 | 66054 | 0 | 0 |
T14 | 133947 | 132925 | 0 | 0 |
T17 | 36518 | 36434 | 0 | 0 |
T32 | 292839 | 292753 | 0 | 0 |
T33 | 2301 | 2229 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30755436 | 0 | 0 |
T1 | 409098 | 404387 | 0 | 0 |
T2 | 1204 | 1124 | 0 | 0 |
T3 | 24213 | 24146 | 0 | 0 |
T4 | 274531 | 274125 | 0 | 0 |
T9 | 2012 | 1947 | 0 | 0 |
T11 | 66146 | 66054 | 0 | 0 |
T14 | 133947 | 132925 | 0 | 0 |
T17 | 36518 | 36434 | 0 | 0 |
T32 | 292839 | 292753 | 0 | 0 |
T33 | 2301 | 2229 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 30798732 | 30755436 | 0 | 0 |
gen_no_flops.OutputDelay_A | 30798732 | 30755436 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30755436 | 0 | 0 |
T1 | 409098 | 404387 | 0 | 0 |
T2 | 1204 | 1124 | 0 | 0 |
T3 | 24213 | 24146 | 0 | 0 |
T4 | 274531 | 274125 | 0 | 0 |
T9 | 2012 | 1947 | 0 | 0 |
T11 | 66146 | 66054 | 0 | 0 |
T14 | 133947 | 132925 | 0 | 0 |
T17 | 36518 | 36434 | 0 | 0 |
T32 | 292839 | 292753 | 0 | 0 |
T33 | 2301 | 2229 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 30798732 | 30755436 | 0 | 0 |
T1 | 409098 | 404387 | 0 | 0 |
T2 | 1204 | 1124 | 0 | 0 |
T3 | 24213 | 24146 | 0 | 0 |
T4 | 274531 | 274125 | 0 | 0 |
T9 | 2012 | 1947 | 0 | 0 |
T11 | 66146 | 66054 | 0 | 0 |
T14 | 133947 | 132925 | 0 | 0 |
T17 | 36518 | 36434 | 0 | 0 |
T32 | 292839 | 292753 | 0 | 0 |
T33 | 2301 | 2229 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |