| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 87.56 | 92.86 | 79.29 | 89.36 | 75.64 | 82.65 | 97.75 | 95.34 |
| T275 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.396963255 | Feb 21 12:25:45 PM PST 24 | Feb 21 12:26:11 PM PST 24 | 576981767 ps | ||
| T104 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.229492191 | Feb 21 12:27:30 PM PST 24 | Feb 21 12:27:32 PM PST 24 | 70819148 ps | ||
| T276 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2730844823 | Feb 21 12:27:07 PM PST 24 | Feb 21 12:27:12 PM PST 24 | 4172740075 ps | ||
| T277 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1721875904 | Feb 21 12:28:04 PM PST 24 | Feb 21 12:28:11 PM PST 24 | 5317993906 ps | ||
| T278 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.782886878 | Feb 21 12:25:43 PM PST 24 | Feb 21 12:25:45 PM PST 24 | 2237576865 ps | ||
| T117 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2699186993 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:28 PM PST 24 | 279492582 ps | ||
| T279 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.253192276 | Feb 21 12:27:37 PM PST 24 | Feb 21 12:28:01 PM PST 24 | 26439997316 ps | ||
| T280 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4057853512 | Feb 21 12:25:59 PM PST 24 | Feb 21 12:26:02 PM PST 24 | 746394953 ps | ||
| T281 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3327473936 | Feb 21 12:28:04 PM PST 24 | Feb 21 12:28:06 PM PST 24 | 168476382 ps | ||
| T105 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.505323993 | Feb 21 12:26:20 PM PST 24 | Feb 21 12:27:12 PM PST 24 | 1455630972 ps | ||
| T118 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3108976179 | Feb 21 12:27:07 PM PST 24 | Feb 21 12:27:10 PM PST 24 | 87656192 ps | ||
| T126 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2406996535 | Feb 21 12:26:58 PM PST 24 | Feb 21 12:27:07 PM PST 24 | 738942936 ps | ||
| T282 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.708323563 | Feb 21 12:27:33 PM PST 24 | Feb 21 12:27:40 PM PST 24 | 4189690032 ps | ||
| T283 | /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.878663236 | Feb 21 12:27:06 PM PST 24 | Feb 21 12:27:24 PM PST 24 | 5263277179 ps | ||
| T109 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.344561576 | Feb 21 12:27:01 PM PST 24 | Feb 21 12:27:06 PM PST 24 | 214894441 ps | ||
| T284 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.249649087 | Feb 21 12:28:07 PM PST 24 | Feb 21 12:28:09 PM PST 24 | 196613934 ps | ||
| T285 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3993369607 | Feb 21 12:26:28 PM PST 24 | Feb 21 12:26:30 PM PST 24 | 91176231 ps | ||
| T96 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2234531784 | Feb 21 12:26:49 PM PST 24 | Feb 21 12:26:53 PM PST 24 | 78015075 ps | ||
| T286 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4205942804 | Feb 21 12:26:27 PM PST 24 | Feb 21 12:26:47 PM PST 24 | 4790055866 ps | ||
| T287 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2189608501 | Feb 21 12:26:51 PM PST 24 | Feb 21 12:26:53 PM PST 24 | 50785732 ps | ||
| T288 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1425989958 | Feb 21 12:27:46 PM PST 24 | Feb 21 12:27:47 PM PST 24 | 20180225 ps | ||
| T289 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3537862751 | Feb 21 12:26:44 PM PST 24 | Feb 21 12:26:46 PM PST 24 | 73450164 ps | ||
| T290 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.607915511 | Feb 21 12:25:25 PM PST 24 | Feb 21 12:25:28 PM PST 24 | 205453191 ps | ||
| T291 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4165021131 | Feb 21 12:26:27 PM PST 24 | Feb 21 12:26:35 PM PST 24 | 3141488731 ps | ||
| T292 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.560305656 | Feb 21 12:26:17 PM PST 24 | Feb 21 12:26:18 PM PST 24 | 26709051 ps | ||
| T293 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3823331310 | Feb 21 12:26:08 PM PST 24 | Feb 21 12:26:15 PM PST 24 | 83233388 ps | ||
| T294 | /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1871206468 | Feb 21 12:26:45 PM PST 24 | Feb 21 12:27:10 PM PST 24 | 10504816012 ps | ||
| T295 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.607548728 | Feb 21 12:26:10 PM PST 24 | Feb 21 12:26:13 PM PST 24 | 792387880 ps | ||
| T296 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.261480726 | Feb 21 12:27:37 PM PST 24 | Feb 21 12:27:38 PM PST 24 | 182441037 ps | ||
| T297 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4062850117 | Feb 21 12:28:14 PM PST 24 | Feb 21 12:28:19 PM PST 24 | 469015901 ps | ||
| T298 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3797720062 | Feb 21 12:26:44 PM PST 24 | Feb 21 12:26:50 PM PST 24 | 177523160 ps | ||
| T299 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3871474451 | Feb 21 12:26:46 PM PST 24 | Feb 21 12:26:48 PM PST 24 | 39307771 ps | ||
| T300 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3053217684 | Feb 21 12:26:32 PM PST 24 | Feb 21 12:26:35 PM PST 24 | 915695930 ps | ||
| T301 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3871406015 | Feb 21 12:26:11 PM PST 24 | Feb 21 12:26:16 PM PST 24 | 1625189824 ps | ||
| T106 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1371367811 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:26 PM PST 24 | 96891786 ps | ||
| T110 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1073442496 | Feb 21 12:28:19 PM PST 24 | Feb 21 12:28:26 PM PST 24 | 137586610 ps | ||
| T87 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.944327777 | Feb 21 12:27:47 PM PST 24 | Feb 21 12:27:49 PM PST 24 | 461631774 ps | ||
| T302 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1838614031 | Feb 21 12:26:45 PM PST 24 | Feb 21 12:26:49 PM PST 24 | 529634951 ps | ||
| T111 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.737595918 | Feb 21 12:26:49 PM PST 24 | Feb 21 12:26:53 PM PST 24 | 4135487834 ps | ||
| T112 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3279107080 | Feb 21 12:28:07 PM PST 24 | Feb 21 12:28:11 PM PST 24 | 736922838 ps | ||
| T303 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3108734433 | Feb 21 12:26:57 PM PST 24 | Feb 21 12:27:06 PM PST 24 | 3683185094 ps | ||
| T88 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.543751923 | Feb 21 12:26:17 PM PST 24 | Feb 21 12:26:22 PM PST 24 | 1089995950 ps | ||
| T304 | /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.268740186 | Feb 21 12:26:52 PM PST 24 | Feb 21 12:27:22 PM PST 24 | 15006789096 ps | ||
| T107 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2533476992 | Feb 21 12:26:51 PM PST 24 | Feb 21 12:26:53 PM PST 24 | 161671486 ps | ||
| T305 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1827369854 | Feb 21 12:27:51 PM PST 24 | Feb 21 12:27:54 PM PST 24 | 128001680 ps | ||
| T306 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1276635639 | Feb 21 12:26:41 PM PST 24 | Feb 21 12:27:18 PM PST 24 | 4974062055 ps | ||
| T307 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3424955123 | Feb 21 12:25:23 PM PST 24 | Feb 21 12:25:25 PM PST 24 | 45854621 ps | ||
| T308 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.998387183 | Feb 21 12:27:10 PM PST 24 | Feb 21 12:27:12 PM PST 24 | 86356693 ps | ||
| T309 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.502980350 | Feb 21 12:27:42 PM PST 24 | Feb 21 12:27:48 PM PST 24 | 1162841373 ps | ||
| T310 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.161984996 | Feb 21 12:26:03 PM PST 24 | Feb 21 12:26:05 PM PST 24 | 576052314 ps | ||
| T311 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1955281217 | Feb 21 12:27:05 PM PST 24 | Feb 21 12:27:13 PM PST 24 | 624896656 ps | ||
| T312 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1342498999 | Feb 21 12:25:57 PM PST 24 | Feb 21 12:25:58 PM PST 24 | 22544501 ps | ||
| T313 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2096804515 | Feb 21 12:27:04 PM PST 24 | Feb 21 12:27:07 PM PST 24 | 817482751 ps | ||
| T123 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2188956398 | Feb 21 12:26:54 PM PST 24 | Feb 21 12:27:05 PM PST 24 | 579746166 ps | ||
| T97 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.380340049 | Feb 21 12:27:37 PM PST 24 | Feb 21 12:27:42 PM PST 24 | 335303299 ps | ||
| T314 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3501643331 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:28 PM PST 24 | 269984079 ps | ||
| T315 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.487157586 | Feb 21 12:26:53 PM PST 24 | Feb 21 12:26:55 PM PST 24 | 88875788 ps | ||
| T316 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.938114130 | Feb 21 12:26:46 PM PST 24 | Feb 21 12:26:48 PM PST 24 | 539627778 ps | ||
| T317 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2427480831 | Feb 21 12:27:10 PM PST 24 | Feb 21 12:27:11 PM PST 24 | 59898745 ps | ||
| T98 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1546330644 | Feb 21 12:27:12 PM PST 24 | Feb 21 12:27:18 PM PST 24 | 792231571 ps | ||
| T318 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.445878532 | Feb 21 12:26:44 PM PST 24 | Feb 21 12:26:46 PM PST 24 | 78992387 ps | ||
| T319 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3016681186 | Feb 21 12:26:28 PM PST 24 | Feb 21 12:26:32 PM PST 24 | 686480554 ps | ||
| T320 | /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1496508211 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:41 PM PST 24 | 5155915439 ps | ||
| T321 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3126839211 | Feb 21 12:27:10 PM PST 24 | Feb 21 12:27:11 PM PST 24 | 56276676 ps | ||
| T322 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1083554888 | Feb 21 12:27:06 PM PST 24 | Feb 21 12:27:09 PM PST 24 | 153736957 ps | ||
| T323 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2419002868 | Feb 21 12:26:06 PM PST 24 | Feb 21 12:26:23 PM PST 24 | 1431849969 ps | ||
| T324 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1061580768 | Feb 21 12:27:42 PM PST 24 | Feb 21 12:27:46 PM PST 24 | 374409195 ps | ||
| T325 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2347932550 | Feb 21 12:25:59 PM PST 24 | Feb 21 12:26:14 PM PST 24 | 3765111403 ps | ||
| T99 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1647468464 | Feb 21 12:26:15 PM PST 24 | Feb 21 12:26:19 PM PST 24 | 163856062 ps | ||
| T326 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3475713730 | Feb 21 12:28:07 PM PST 24 | Feb 21 12:28:44 PM PST 24 | 48492330939 ps | ||
| T327 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4245320011 | Feb 21 12:27:55 PM PST 24 | Feb 21 12:27:56 PM PST 24 | 27566174 ps | ||
| T328 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3684990650 | Feb 21 12:25:57 PM PST 24 | Feb 21 12:25:58 PM PST 24 | 27995996 ps | ||
| T329 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.560825409 | Feb 21 12:28:07 PM PST 24 | Feb 21 12:28:10 PM PST 24 | 62310329 ps | ||
| T330 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4171410554 | Feb 21 12:25:40 PM PST 24 | Feb 21 12:26:04 PM PST 24 | 14125975430 ps | ||
| T331 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1634061267 | Feb 21 12:27:37 PM PST 24 | Feb 21 12:27:38 PM PST 24 | 169472352 ps | ||
| T332 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3563554179 | Feb 21 12:28:14 PM PST 24 | Feb 21 12:28:18 PM PST 24 | 14078704 ps | ||
| T333 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2932473662 | Feb 21 12:27:55 PM PST 24 | Feb 21 12:28:01 PM PST 24 | 376019710 ps | ||
| T334 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3222511109 | Feb 21 12:25:59 PM PST 24 | Feb 21 12:26:52 PM PST 24 | 1455983240 ps | ||
| T335 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3647481286 | Feb 21 12:25:13 PM PST 24 | Feb 21 12:25:14 PM PST 24 | 97697059 ps | ||
| T336 | /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3930175255 | Feb 21 12:27:25 PM PST 24 | Feb 21 12:27:40 PM PST 24 | 6615096752 ps | ||
| T337 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.686277968 | Feb 21 12:25:25 PM PST 24 | Feb 21 12:25:27 PM PST 24 | 29350809 ps | ||
| T338 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2922695128 | Feb 21 12:26:10 PM PST 24 | Feb 21 12:26:11 PM PST 24 | 241348447 ps | ||
| T339 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3973492459 | Feb 21 12:25:38 PM PST 24 | Feb 21 12:27:11 PM PST 24 | 28885362563 ps | ||
| T128 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.478632785 | Feb 21 12:28:06 PM PST 24 | Feb 21 12:28:23 PM PST 24 | 3872252485 ps | ||
| T340 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1272555745 | Feb 21 12:27:06 PM PST 24 | Feb 21 12:27:08 PM PST 24 | 277442841 ps | ||
| T341 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2182228203 | Feb 21 12:27:12 PM PST 24 | Feb 21 12:27:14 PM PST 24 | 102894440 ps | ||
| T342 | /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3988656670 | Feb 21 12:27:25 PM PST 24 | Feb 21 12:27:41 PM PST 24 | 8012798403 ps | ||
| T89 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2112574413 | Feb 21 12:25:17 PM PST 24 | Feb 21 12:25:22 PM PST 24 | 1268555589 ps | ||
| T343 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3599914582 | Feb 21 12:26:11 PM PST 24 | Feb 21 12:26:16 PM PST 24 | 311382074 ps | ||
| T344 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3199774872 | Feb 21 12:26:14 PM PST 24 | Feb 21 12:26:16 PM PST 24 | 72430208 ps | ||
| T345 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.688913489 | Feb 21 12:26:27 PM PST 24 | Feb 21 12:26:29 PM PST 24 | 111674079 ps | ||
| T346 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1174065782 | Feb 21 12:26:20 PM PST 24 | Feb 21 12:26:21 PM PST 24 | 282522958 ps | ||
| T347 | /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.3519493211 | Feb 21 12:27:07 PM PST 24 | Feb 21 12:27:31 PM PST 24 | 23718003506 ps | ||
| T58 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3513261822 | Feb 21 12:27:59 PM PST 24 | Feb 21 12:28:08 PM PST 24 | 2201044233 ps | ||
| T348 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2440884958 | Feb 21 12:26:10 PM PST 24 | Feb 21 12:26:13 PM PST 24 | 64938376 ps | ||
| T349 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2984985166 | Feb 21 12:26:02 PM PST 24 | Feb 21 12:26:03 PM PST 24 | 51380191 ps | ||
| T350 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2056098114 | Feb 21 12:28:06 PM PST 24 | Feb 21 12:28:07 PM PST 24 | 784634231 ps | ||
| T351 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.806361731 | Feb 21 12:27:46 PM PST 24 | Feb 21 12:27:51 PM PST 24 | 2545952903 ps | ||
| T100 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4176988013 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:32 PM PST 24 | 829844343 ps | ||
| T352 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.490168489 | Feb 21 12:27:01 PM PST 24 | Feb 21 12:27:04 PM PST 24 | 447799742 ps | ||
| T353 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2306857910 | Feb 21 12:28:19 PM PST 24 | Feb 21 12:29:31 PM PST 24 | 3356591614 ps | ||
| T354 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2290098934 | Feb 21 12:27:06 PM PST 24 | Feb 21 12:27:10 PM PST 24 | 3325048374 ps | ||
| T355 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.181150045 | Feb 21 12:25:59 PM PST 24 | Feb 21 12:26:01 PM PST 24 | 218072287 ps | ||
| T356 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3123649746 | Feb 21 12:27:55 PM PST 24 | Feb 21 12:27:56 PM PST 24 | 139232832 ps | ||
| T357 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.562060178 | Feb 21 12:27:59 PM PST 24 | Feb 21 12:28:01 PM PST 24 | 370356910 ps | ||
| T358 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2529863779 | Feb 21 12:27:12 PM PST 24 | Feb 21 12:27:13 PM PST 24 | 40817290 ps | ||
| T359 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4222438872 | Feb 21 12:26:28 PM PST 24 | Feb 21 12:26:31 PM PST 24 | 1471204642 ps | ||
| T129 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.239689353 | Feb 21 12:28:05 PM PST 24 | Feb 21 12:28:20 PM PST 24 | 835626613 ps | ||
| T360 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.343250349 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:30 PM PST 24 | 5849331556 ps | ||
| T124 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1377726830 | Feb 21 12:26:02 PM PST 24 | Feb 21 12:26:17 PM PST 24 | 1526739125 ps | ||
| T361 | /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1650693416 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:38 PM PST 24 | 8050127981 ps | ||
| T362 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2273565918 | Feb 21 12:28:14 PM PST 24 | Feb 21 12:28:21 PM PST 24 | 142155471 ps | ||
| T363 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3477408742 | Feb 21 12:27:34 PM PST 24 | Feb 21 12:27:35 PM PST 24 | 78197119 ps | ||
| T364 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1155431445 | Feb 21 12:27:08 PM PST 24 | Feb 21 12:27:10 PM PST 24 | 1404841861 ps | ||
| T365 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1160062904 | Feb 21 12:27:47 PM PST 24 | Feb 21 12:27:49 PM PST 24 | 130866649 ps | ||
| T366 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3555006266 | Feb 21 12:26:13 PM PST 24 | Feb 21 12:26:16 PM PST 24 | 151745811 ps | ||
| T367 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3522222421 | Feb 21 12:28:04 PM PST 24 | Feb 21 12:28:06 PM PST 24 | 48821149 ps | ||
| T368 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1762201245 | Feb 21 12:26:35 PM PST 24 | Feb 21 12:26:36 PM PST 24 | 115486742 ps | ||
| T369 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2086263182 | Feb 21 12:26:27 PM PST 24 | Feb 21 12:27:07 PM PST 24 | 18646931636 ps | ||
| T370 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2086840031 | Feb 21 12:27:24 PM PST 24 | Feb 21 12:27:29 PM PST 24 | 3131245807 ps | ||
| T371 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3964897625 | Feb 21 12:27:59 PM PST 24 | Feb 21 12:28:00 PM PST 24 | 210954776 ps | ||
| T372 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.21270018 | Feb 21 12:26:49 PM PST 24 | Feb 21 12:26:53 PM PST 24 | 168178808 ps | ||
| T373 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.831339795 | Feb 21 12:27:25 PM PST 24 | Feb 21 12:27:44 PM PST 24 | 3382136858 ps |
| Test location | /workspace/coverage/default/35.rv_dm_stress_all.4093902752 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4023361011 ps |
| CPU time | 5.26 seconds |
| Started | Feb 21 12:30:07 PM PST 24 |
| Finished | Feb 21 12:30:12 PM PST 24 |
| Peak memory | 204212 kb |
| Host | smart-7bfbd359-1258-4e6c-bcea-e1ead11d6c9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093902752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.4093902752 |
| Directory | /workspace/35.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.821885523 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8948692519 ps |
| CPU time | 10.49 seconds |
| Started | Feb 21 12:26:58 PM PST 24 |
| Finished | Feb 21 12:27:09 PM PST 24 |
| Peak memory | 220628 kb |
| Host | smart-6887f850-77a1-483c-a574-1bc61ece5ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821885523 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.821885523 |
| Directory | /workspace/15.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3166894989 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 16244099422 ps |
| CPU time | 34.67 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:49 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-16fbf831-73ab-4ac8-be90-c0af0bd5f0a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166894989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3166894989 |
| Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3344095559 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1572356525 ps |
| CPU time | 19.55 seconds |
| Started | Feb 21 12:25:42 PM PST 24 |
| Finished | Feb 21 12:26:02 PM PST 24 |
| Peak memory | 215320 kb |
| Host | smart-d34e042b-24fa-4793-ac37-a74d264cd3e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344095559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3344095559 |
| Directory | /workspace/2.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/default/47.rv_dm_alert_test.1641502413 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 40752614 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:30:00 PM PST 24 |
| Finished | Feb 21 12:30:02 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-889f479e-bf06-40c5-9175-b968ef1afa6b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641502413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1641502413 |
| Directory | /workspace/47.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/15.rv_dm_stress_all.2518633884 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3409430362 ps |
| CPU time | 6.34 seconds |
| Started | Feb 21 12:29:33 PM PST 24 |
| Finished | Feb 21 12:29:39 PM PST 24 |
| Peak memory | 204140 kb |
| Host | smart-915d6dc0-c354-4502-be5f-ef72f3cc996d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518633884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2518633884 |
| Directory | /workspace/15.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3138523646 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2077351083 ps |
| CPU time | 4.76 seconds |
| Started | Feb 21 12:27:10 PM PST 24 |
| Finished | Feb 21 12:27:15 PM PST 24 |
| Peak memory | 212352 kb |
| Host | smart-71fea1a4-dd64-4bca-97c3-bfc874f4b08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138523646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3138523646 |
| Directory | /workspace/17.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1704249777 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 18996053202 ps |
| CPU time | 43.08 seconds |
| Started | Feb 21 12:29:30 PM PST 24 |
| Finished | Feb 21 12:30:14 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-b3ac0242-572e-434c-b110-086bb2a4212d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704249777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1704249777 |
| Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/6.rv_dm_stress_all.3540821585 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1758198598 ps |
| CPU time | 5.46 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:25 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-4855685f-e533-4c23-8b18-b30df50630be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540821585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3540821585 |
| Directory | /workspace/6.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3919558365 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5943607248 ps |
| CPU time | 15.79 seconds |
| Started | Feb 21 12:26:46 PM PST 24 |
| Finished | Feb 21 12:27:03 PM PST 24 |
| Peak memory | 212728 kb |
| Host | smart-31cf7726-8309-49ad-9ab2-9b6570eabd5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919558365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 919558365 |
| Directory | /workspace/11.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4181505894 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 9483951239 ps |
| CPU time | 65.23 seconds |
| Started | Feb 21 12:26:01 PM PST 24 |
| Finished | Feb 21 12:27:06 PM PST 24 |
| Peak memory | 203172 kb |
| Host | smart-d5b32596-ef5e-4360-af9a-7c5dd1ae3b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181505894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.4181505894 |
| Directory | /workspace/3.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/default/44.rv_dm_stress_all.1540166683 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5035563106 ps |
| CPU time | 16.28 seconds |
| Started | Feb 21 12:29:51 PM PST 24 |
| Finished | Feb 21 12:30:08 PM PST 24 |
| Peak memory | 204148 kb |
| Host | smart-516a61ae-89b0-475a-9170-360b6cceed52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540166683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1540166683 |
| Directory | /workspace/44.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2046534041 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 158751439 ps |
| CPU time | 0.97 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:16 PM PST 24 |
| Peak memory | 220144 kb |
| Host | smart-14008ba9-b850-467e-97ef-9a17f1ae2628 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046534041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2046534041 |
| Directory | /workspace/0.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.2916233722 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 106968617 ps |
| CPU time | 0.86 seconds |
| Started | Feb 21 12:29:09 PM PST 24 |
| Finished | Feb 21 12:29:10 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-eeb9cc98-0f0e-46b4-9a94-31463c31d435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916233722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2916233722 |
| Directory | /workspace/0.rv_dm_cmderr_exception/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4091034712 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1839947611 ps |
| CPU time | 16.68 seconds |
| Started | Feb 21 12:27:09 PM PST 24 |
| Finished | Feb 21 12:27:26 PM PST 24 |
| Peak memory | 213476 kb |
| Host | smart-6935a14f-16a0-4c42-802b-acb5fa6f2ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091034712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4 091034712 |
| Directory | /workspace/17.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3275959929 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 795205114 ps |
| CPU time | 7.6 seconds |
| Started | Feb 21 12:26:53 PM PST 24 |
| Finished | Feb 21 12:27:01 PM PST 24 |
| Peak memory | 204328 kb |
| Host | smart-13cbc881-7bc1-4d12-abe3-3f03ffe18b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275959929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3275959929 |
| Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.215030208 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 271921383 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:15 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-6d6d1c64-00b4-4f84-8df0-ded9dff38356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215030208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.215030208 |
| Directory | /workspace/0.rv_dm_progbuf_busy/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3745902349 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 134999011 ps |
| CPU time | 4.67 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:26:03 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-853ad22a-2665-44c1-a138-21883492bf44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745902349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3745902349 |
| Directory | /workspace/1.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2188956398 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 579746166 ps |
| CPU time | 10.6 seconds |
| Started | Feb 21 12:26:54 PM PST 24 |
| Finished | Feb 21 12:27:05 PM PST 24 |
| Peak memory | 212328 kb |
| Host | smart-58a1d7f3-db68-4faf-9c7a-1da1ebe828ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188956398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 188956398 |
| Directory | /workspace/15.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3513261822 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2201044233 ps |
| CPU time | 7.99 seconds |
| Started | Feb 21 12:27:59 PM PST 24 |
| Finished | Feb 21 12:28:08 PM PST 24 |
| Peak memory | 211808 kb |
| Host | smart-107d5d86-37cf-4e54-b128-41167f3cb7c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513261822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3513261822 |
| Directory | /workspace/0.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1110590180 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 61298057 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:26:59 PM PST 24 |
| Finished | Feb 21 12:27:00 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-63477a66-9488-4953-a848-b6d7acaece2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110590180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 1110590180 |
| Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1650693416 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 8050127981 ps |
| CPU time | 13.91 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:38 PM PST 24 |
| Peak memory | 217684 kb |
| Host | smart-e31219bc-9012-4016-bbcb-93dde2a4020f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650693416 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.1650693416 |
| Directory | /workspace/16.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2112574413 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1268555589 ps |
| CPU time | 4.26 seconds |
| Started | Feb 21 12:25:17 PM PST 24 |
| Finished | Feb 21 12:25:22 PM PST 24 |
| Peak memory | 204236 kb |
| Host | smart-66162f2e-6f3b-4dcb-9b7d-2fbb5f3421c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112574413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2112574413 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3329686342 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 361313345 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:29:27 PM PST 24 |
| Finished | Feb 21 12:29:28 PM PST 24 |
| Peak memory | 203668 kb |
| Host | smart-557d6eaa-0509-4841-87b0-e38ee6b7ebb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329686342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3329686342 |
| Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.396963255 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 576981767 ps |
| CPU time | 26.43 seconds |
| Started | Feb 21 12:25:45 PM PST 24 |
| Finished | Feb 21 12:26:11 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-77419a6a-2707-4fdf-ab5b-ce49fe253de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396963255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.rv_dm_csr_aliasing.396963255 |
| Directory | /workspace/0.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1276635639 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 4974062055 ps |
| CPU time | 35.47 seconds |
| Started | Feb 21 12:26:41 PM PST 24 |
| Finished | Feb 21 12:27:18 PM PST 24 |
| Peak memory | 203956 kb |
| Host | smart-7fc8d9a3-5620-4bc9-a4f6-718b14a7bb25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276635639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1276635639 |
| Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1731107159 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 944458662 ps |
| CPU time | 2.48 seconds |
| Started | Feb 21 12:26:28 PM PST 24 |
| Finished | Feb 21 12:26:31 PM PST 24 |
| Peak memory | 211704 kb |
| Host | smart-7e9178bb-b9b8-4239-8ba3-345fe6605244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731107159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1731107159 |
| Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.180400896 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1442064699 ps |
| CPU time | 5.71 seconds |
| Started | Feb 21 12:25:28 PM PST 24 |
| Finished | Feb 21 12:25:34 PM PST 24 |
| Peak memory | 215872 kb |
| Host | smart-c6297334-209f-490e-bd11-fde8959a4bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180400896 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.180400896 |
| Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.607915511 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 205453191 ps |
| CPU time | 2.54 seconds |
| Started | Feb 21 12:25:25 PM PST 24 |
| Finished | Feb 21 12:25:28 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-b2973fd2-66ce-4056-b645-f0e6774331e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607915511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.607915511 |
| Directory | /workspace/0.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4205942804 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 4790055866 ps |
| CPU time | 19.22 seconds |
| Started | Feb 21 12:26:27 PM PST 24 |
| Finished | Feb 21 12:26:47 PM PST 24 |
| Peak memory | 201424 kb |
| Host | smart-87aae1f0-0379-48a5-94a1-1790b12db0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205942804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.4205942804 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2922695128 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 241348447 ps |
| CPU time | 0.93 seconds |
| Started | Feb 21 12:26:10 PM PST 24 |
| Finished | Feb 21 12:26:11 PM PST 24 |
| Peak memory | 203704 kb |
| Host | smart-4cc69809-bb0f-4dde-9c75-0bce555d7cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922695128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 922695128 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3964897625 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 210954776 ps |
| CPU time | 1.14 seconds |
| Started | Feb 21 12:27:59 PM PST 24 |
| Finished | Feb 21 12:28:00 PM PST 24 |
| Peak memory | 203496 kb |
| Host | smart-02900239-7740-4c6e-b2f4-a234e073a78a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964897625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3964897625 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4165021131 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3141488731 ps |
| CPU time | 6.89 seconds |
| Started | Feb 21 12:26:27 PM PST 24 |
| Finished | Feb 21 12:26:35 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-43773a56-1d1e-4201-bec0-3f5f555882c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165021131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.4165021131 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3647481286 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 97697059 ps |
| CPU time | 0.76 seconds |
| Started | Feb 21 12:25:13 PM PST 24 |
| Finished | Feb 21 12:25:14 PM PST 24 |
| Peak memory | 203424 kb |
| Host | smart-852fceb8-c272-4481-b47e-5f3db6cb7c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647481286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3647481286 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3424955123 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 45854621 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:25:23 PM PST 24 |
| Finished | Feb 21 12:25:25 PM PST 24 |
| Peak memory | 203544 kb |
| Host | smart-0d96db08-3b53-48b1-94c6-71e16feff528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424955123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 424955123 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.686277968 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 29350809 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:25:25 PM PST 24 |
| Finished | Feb 21 12:25:27 PM PST 24 |
| Peak memory | 203340 kb |
| Host | smart-6bab95e0-d752-440f-a5b4-9fbdbc57798c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686277968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.686277968 |
| Directory | /workspace/0.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2858968934 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 44473963 ps |
| CPU time | 0.62 seconds |
| Started | Feb 21 12:28:19 PM PST 24 |
| Finished | Feb 21 12:28:20 PM PST 24 |
| Peak memory | 203108 kb |
| Host | smart-d799b9b3-385b-42c4-bf87-ec1826b6a532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858968934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2858968934 |
| Directory | /workspace/0.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2932473662 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 376019710 ps |
| CPU time | 6.17 seconds |
| Started | Feb 21 12:27:55 PM PST 24 |
| Finished | Feb 21 12:28:01 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-411b5867-e088-4109-934d-00f07c246d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932473662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2932473662 |
| Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.253192276 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 26439997316 ps |
| CPU time | 23.01 seconds |
| Started | Feb 21 12:27:37 PM PST 24 |
| Finished | Feb 21 12:28:01 PM PST 24 |
| Peak memory | 219256 kb |
| Host | smart-abbb0623-9958-45c8-aa0c-7108de7b2127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253192276 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.253192276 |
| Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.269792936 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 309624853 ps |
| CPU time | 7.04 seconds |
| Started | Feb 21 12:26:02 PM PST 24 |
| Finished | Feb 21 12:26:09 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-4cb27450-3739-488c-a84d-59dc1b85e60c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269792936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.269792936 |
| Directory | /workspace/0.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2306857910 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3356591614 ps |
| CPU time | 71.39 seconds |
| Started | Feb 21 12:28:19 PM PST 24 |
| Finished | Feb 21 12:29:31 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-60a13807-8778-431e-b925-ebe2f63662d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306857910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.2306857910 |
| Directory | /workspace/1.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3222511109 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1455983240 ps |
| CPU time | 52.83 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:26:52 PM PST 24 |
| Peak memory | 203880 kb |
| Host | smart-ed0b543d-dc59-4ec1-a26c-f40e655fd2af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222511109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3222511109 |
| Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.77940812 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 839866301 ps |
| CPU time | 2.6 seconds |
| Started | Feb 21 12:25:43 PM PST 24 |
| Finished | Feb 21 12:25:46 PM PST 24 |
| Peak memory | 212528 kb |
| Host | smart-0b303774-2d5f-4e13-a9fa-aa9329ada865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77940812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.77940812 |
| Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.607548728 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 792387880 ps |
| CPU time | 3.48 seconds |
| Started | Feb 21 12:26:10 PM PST 24 |
| Finished | Feb 21 12:26:13 PM PST 24 |
| Peak memory | 220252 kb |
| Host | smart-cfdc7dcc-a5f3-46c9-8cb4-34089103f60c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607548728 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.607548728 |
| Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2986588952 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 453333820 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 12:27:58 PM PST 24 |
| Finished | Feb 21 12:28:00 PM PST 24 |
| Peak memory | 203832 kb |
| Host | smart-cfcb98da-ba22-4328-9dc3-728511c7957f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986588952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2986588952 |
| Directory | /workspace/1.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2086263182 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 18646931636 ps |
| CPU time | 39.2 seconds |
| Started | Feb 21 12:26:27 PM PST 24 |
| Finished | Feb 21 12:27:07 PM PST 24 |
| Peak memory | 201300 kb |
| Host | smart-078f2d1d-0c52-47c9-b749-a31204130611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086263182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2086263182 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3973492459 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 28885362563 ps |
| CPU time | 92.54 seconds |
| Started | Feb 21 12:25:38 PM PST 24 |
| Finished | Feb 21 12:27:11 PM PST 24 |
| Peak memory | 203860 kb |
| Host | smart-9c635403-9ba5-4b96-96ba-dbbba6457b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973492459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_bit_bash.3973492459 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1042011296 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 572334716 ps |
| CPU time | 2.36 seconds |
| Started | Feb 21 12:26:01 PM PST 24 |
| Finished | Feb 21 12:26:03 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-bb990eb2-e5db-4621-93cc-f1b28fbd8ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042011296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.1042011296 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2056098114 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 784634231 ps |
| CPU time | 1.16 seconds |
| Started | Feb 21 12:28:06 PM PST 24 |
| Finished | Feb 21 12:28:07 PM PST 24 |
| Peak memory | 202916 kb |
| Host | smart-78b6e280-f530-434f-925b-1e69547977f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056098114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 056098114 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3993369607 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 91176231 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:26:28 PM PST 24 |
| Finished | Feb 21 12:26:30 PM PST 24 |
| Peak memory | 203236 kb |
| Host | smart-5cfbf561-9f37-44b7-afbd-52a597e61a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993369607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3993369607 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4222438872 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1471204642 ps |
| CPU time | 2.32 seconds |
| Started | Feb 21 12:26:28 PM PST 24 |
| Finished | Feb 21 12:26:31 PM PST 24 |
| Peak memory | 203404 kb |
| Host | smart-01b2984b-797e-4085-ba0d-fce1e33ebbfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222438872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.4222438872 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2984985166 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 51380191 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:26:02 PM PST 24 |
| Finished | Feb 21 12:26:03 PM PST 24 |
| Peak memory | 203972 kb |
| Host | smart-50123894-f367-40ca-879a-3bbe88733b59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984985166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.2984985166 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3123649746 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 139232832 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:27:55 PM PST 24 |
| Finished | Feb 21 12:27:56 PM PST 24 |
| Peak memory | 203480 kb |
| Host | smart-afea73fe-f73d-4209-ab41-ab6a34a17eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123649746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 123649746 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4245320011 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 27566174 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:27:55 PM PST 24 |
| Finished | Feb 21 12:27:56 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-f5f0d1ef-94a6-490e-ba2c-ce63f07782bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245320011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.4245320011 |
| Directory | /workspace/1.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1196657637 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 133487201 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:25:44 PM PST 24 |
| Finished | Feb 21 12:25:45 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-a9cf18be-14b8-4217-b6bc-dca1c681109d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196657637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1196657637 |
| Directory | /workspace/1.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.380340049 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 335303299 ps |
| CPU time | 3.52 seconds |
| Started | Feb 21 12:27:37 PM PST 24 |
| Finished | Feb 21 12:27:42 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-5ca5b63b-d06b-4d64-a980-306bfd15bc19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380340049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c sr_outstanding.380340049 |
| Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.478632785 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3872252485 ps |
| CPU time | 17.42 seconds |
| Started | Feb 21 12:28:06 PM PST 24 |
| Finished | Feb 21 12:28:23 PM PST 24 |
| Peak memory | 215252 kb |
| Host | smart-9d0d8997-2b8c-4ff5-a10d-fd403876c08e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478632785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.478632785 |
| Directory | /workspace/1.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1838614031 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 529634951 ps |
| CPU time | 3.3 seconds |
| Started | Feb 21 12:26:45 PM PST 24 |
| Finished | Feb 21 12:26:49 PM PST 24 |
| Peak memory | 219552 kb |
| Host | smart-3f2b3517-e57c-4b60-a75f-03efceebe73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838614031 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1838614031 |
| Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.699538589 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 106355934 ps |
| CPU time | 1.48 seconds |
| Started | Feb 21 12:26:49 PM PST 24 |
| Finished | Feb 21 12:26:51 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-386aa04c-550c-4c5a-a88c-9e8c244c7f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699538589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.699538589 |
| Directory | /workspace/10.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3053217684 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 915695930 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 12:26:32 PM PST 24 |
| Finished | Feb 21 12:26:35 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-afb47553-6492-4013-8ae4-568819c36415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053217684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3053217684 |
| Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1762201245 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 115486742 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:26:35 PM PST 24 |
| Finished | Feb 21 12:26:36 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-0ae90d5c-1836-4871-a94e-24e15363cf54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762201245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1762201245 |
| Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.737595918 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4135487834 ps |
| CPU time | 4.2 seconds |
| Started | Feb 21 12:26:49 PM PST 24 |
| Finished | Feb 21 12:26:53 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-6be23283-1300-447d-8751-b6566158c95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737595918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_ csr_outstanding.737595918 |
| Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3797720062 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 177523160 ps |
| CPU time | 4.27 seconds |
| Started | Feb 21 12:26:44 PM PST 24 |
| Finished | Feb 21 12:26:50 PM PST 24 |
| Peak memory | 204004 kb |
| Host | smart-6e57c86d-a2ca-4b85-8de2-050ec2310895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797720062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3797720062 |
| Directory | /workspace/10.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2191525462 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2020959381 ps |
| CPU time | 18.59 seconds |
| Started | Feb 21 12:26:41 PM PST 24 |
| Finished | Feb 21 12:27:01 PM PST 24 |
| Peak memory | 214388 kb |
| Host | smart-7572fbce-6f85-4f9c-88c2-7322ae48c48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191525462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 191525462 |
| Directory | /workspace/10.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1913726303 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4373001117 ps |
| CPU time | 5.61 seconds |
| Started | Feb 21 12:26:51 PM PST 24 |
| Finished | Feb 21 12:26:57 PM PST 24 |
| Peak memory | 220592 kb |
| Host | smart-fabaf1de-6f7e-4f38-9606-f0ac704986b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913726303 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1913726303 |
| Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2189608501 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 50785732 ps |
| CPU time | 2.11 seconds |
| Started | Feb 21 12:26:51 PM PST 24 |
| Finished | Feb 21 12:26:53 PM PST 24 |
| Peak memory | 203988 kb |
| Host | smart-936b7d86-dfe9-4315-8202-e22e50fa327e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189608501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2189608501 |
| Directory | /workspace/11.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2441558663 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 733525178 ps |
| CPU time | 1.22 seconds |
| Started | Feb 21 12:26:45 PM PST 24 |
| Finished | Feb 21 12:26:48 PM PST 24 |
| Peak memory | 203472 kb |
| Host | smart-e6ae56f5-58b3-4520-9355-ef57cf3381ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441558663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 2441558663 |
| Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3871474451 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 39307771 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:26:46 PM PST 24 |
| Finished | Feb 21 12:26:48 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-93cd8eee-e455-45e0-a4ea-5173aad6ad74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871474451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3871474451 |
| Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2952469714 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 264091870 ps |
| CPU time | 6.51 seconds |
| Started | Feb 21 12:26:51 PM PST 24 |
| Finished | Feb 21 12:26:58 PM PST 24 |
| Peak memory | 204108 kb |
| Host | smart-7e08d765-bd7c-4a3e-b7eb-71eaedb4a330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952469714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.2952469714 |
| Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.2376592227 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 12208735607 ps |
| CPU time | 40.01 seconds |
| Started | Feb 21 12:26:49 PM PST 24 |
| Finished | Feb 21 12:27:29 PM PST 24 |
| Peak memory | 214636 kb |
| Host | smart-df5a571d-c961-436d-8b16-b61187e47fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376592227 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.2376592227 |
| Directory | /workspace/11.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.21270018 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 168178808 ps |
| CPU time | 3.41 seconds |
| Started | Feb 21 12:26:49 PM PST 24 |
| Finished | Feb 21 12:26:53 PM PST 24 |
| Peak memory | 212148 kb |
| Host | smart-6ca61346-4bdc-470a-b9ec-38aa2ba1b012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21270018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.21270018 |
| Directory | /workspace/11.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.211120847 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 64817602 ps |
| CPU time | 4.5 seconds |
| Started | Feb 21 12:26:52 PM PST 24 |
| Finished | Feb 21 12:26:56 PM PST 24 |
| Peak memory | 216728 kb |
| Host | smart-8b30ba5b-9e67-4db5-b2d0-d5e88e76e5cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211120847 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.211120847 |
| Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4216514494 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 190645050 ps |
| CPU time | 2.26 seconds |
| Started | Feb 21 12:26:46 PM PST 24 |
| Finished | Feb 21 12:26:49 PM PST 24 |
| Peak memory | 212108 kb |
| Host | smart-b377cb0e-3986-4852-abff-fe74c8ba5f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216514494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4216514494 |
| Directory | /workspace/12.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.938114130 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 539627778 ps |
| CPU time | 1.3 seconds |
| Started | Feb 21 12:26:46 PM PST 24 |
| Finished | Feb 21 12:26:48 PM PST 24 |
| Peak memory | 203484 kb |
| Host | smart-39f81b47-cc1a-4f6e-bb53-e28b81bcfa3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938114130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.938114130 |
| Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3537862751 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 73450164 ps |
| CPU time | 0.88 seconds |
| Started | Feb 21 12:26:44 PM PST 24 |
| Finished | Feb 21 12:26:46 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-6de5501d-234a-40d6-a914-ca93dec51121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537862751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 3537862751 |
| Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2234531784 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 78015075 ps |
| CPU time | 3.26 seconds |
| Started | Feb 21 12:26:49 PM PST 24 |
| Finished | Feb 21 12:26:53 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-e32f86b5-110a-4fea-aaca-54073876beb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234531784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2234531784 |
| Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1871206468 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 10504816012 ps |
| CPU time | 24.07 seconds |
| Started | Feb 21 12:26:45 PM PST 24 |
| Finished | Feb 21 12:27:10 PM PST 24 |
| Peak memory | 223152 kb |
| Host | smart-8382b4a6-6002-4f6d-b461-d37742f3d049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871206468 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.1871206468 |
| Directory | /workspace/12.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3568384903 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 59351766 ps |
| CPU time | 3.76 seconds |
| Started | Feb 21 12:26:49 PM PST 24 |
| Finished | Feb 21 12:26:53 PM PST 24 |
| Peak memory | 212608 kb |
| Host | smart-6d3a0329-b6b1-4125-a4af-cd67bf8af9d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568384903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3568384903 |
| Directory | /workspace/12.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4084062813 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1567303484 ps |
| CPU time | 11.45 seconds |
| Started | Feb 21 12:26:51 PM PST 24 |
| Finished | Feb 21 12:27:03 PM PST 24 |
| Peak memory | 212676 kb |
| Host | smart-e7245d8a-e4cb-4db3-bdb3-564a614a41fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084062813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.4 084062813 |
| Directory | /workspace/12.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3108734433 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3683185094 ps |
| CPU time | 8.09 seconds |
| Started | Feb 21 12:26:57 PM PST 24 |
| Finished | Feb 21 12:27:06 PM PST 24 |
| Peak memory | 212264 kb |
| Host | smart-c29a325c-d3f9-4ffd-a186-1b94f10c0575 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108734433 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3108734433 |
| Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.487157586 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 88875788 ps |
| CPU time | 2.36 seconds |
| Started | Feb 21 12:26:53 PM PST 24 |
| Finished | Feb 21 12:26:55 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-43c92551-f58d-473d-8591-80367241ce2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487157586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.487157586 |
| Directory | /workspace/13.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.445878532 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 78992387 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:26:44 PM PST 24 |
| Finished | Feb 21 12:26:46 PM PST 24 |
| Peak memory | 203140 kb |
| Host | smart-a2d3f8e0-90e1-4f84-bbc3-52460a41b332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445878532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.445878532 |
| Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.344561576 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 214894441 ps |
| CPU time | 3.93 seconds |
| Started | Feb 21 12:27:01 PM PST 24 |
| Finished | Feb 21 12:27:06 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-fda15032-7762-49f9-b569-e3e2d47b9591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344561576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.344561576 |
| Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.268740186 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 15006789096 ps |
| CPU time | 30.06 seconds |
| Started | Feb 21 12:26:52 PM PST 24 |
| Finished | Feb 21 12:27:22 PM PST 24 |
| Peak memory | 220868 kb |
| Host | smart-748d2f89-9699-4c7d-a550-f04e8c307285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268740186 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.268740186 |
| Directory | /workspace/13.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4110741977 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 101859550 ps |
| CPU time | 2.71 seconds |
| Started | Feb 21 12:27:01 PM PST 24 |
| Finished | Feb 21 12:27:05 PM PST 24 |
| Peak memory | 204012 kb |
| Host | smart-4c24c078-dde2-4e95-b68f-1032687170c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110741977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4110741977 |
| Directory | /workspace/13.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3888417332 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 912318586 ps |
| CPU time | 9.17 seconds |
| Started | Feb 21 12:27:01 PM PST 24 |
| Finished | Feb 21 12:27:11 PM PST 24 |
| Peak memory | 212460 kb |
| Host | smart-dce47d00-f3d5-49be-9079-5987a775330c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888417332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3 888417332 |
| Directory | /workspace/13.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4278386733 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 6461112534 ps |
| CPU time | 5.69 seconds |
| Started | Feb 21 12:26:54 PM PST 24 |
| Finished | Feb 21 12:27:00 PM PST 24 |
| Peak memory | 220396 kb |
| Host | smart-236729d0-8df0-4366-afb1-8bf176760c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278386733 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4278386733 |
| Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3949563733 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 59066963 ps |
| CPU time | 1.6 seconds |
| Started | Feb 21 12:26:58 PM PST 24 |
| Finished | Feb 21 12:27:00 PM PST 24 |
| Peak memory | 203956 kb |
| Host | smart-ba2abb20-b373-49af-87e0-82e292c26e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949563733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3949563733 |
| Directory | /workspace/14.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.490168489 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 447799742 ps |
| CPU time | 2.15 seconds |
| Started | Feb 21 12:27:01 PM PST 24 |
| Finished | Feb 21 12:27:04 PM PST 24 |
| Peak memory | 203708 kb |
| Host | smart-456be0ea-c3b6-4789-8257-9e5f65085239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490168489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.490168489 |
| Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1530124061 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 362486830 ps |
| CPU time | 3.11 seconds |
| Started | Feb 21 12:26:58 PM PST 24 |
| Finished | Feb 21 12:27:02 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-688e2e66-c326-437f-9b61-fde990b41687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530124061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1530124061 |
| Directory | /workspace/14.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2406996535 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 738942936 ps |
| CPU time | 8.87 seconds |
| Started | Feb 21 12:26:58 PM PST 24 |
| Finished | Feb 21 12:27:07 PM PST 24 |
| Peak memory | 212216 kb |
| Host | smart-223a283b-a35f-4b51-b712-25a2424d1b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406996535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 406996535 |
| Directory | /workspace/14.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.343250349 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5849331556 ps |
| CPU time | 6.15 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:30 PM PST 24 |
| Peak memory | 220308 kb |
| Host | smart-2da4ce91-ad3a-40ec-80a4-732cd28ca4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343250349 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.343250349 |
| Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2533476992 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 161671486 ps |
| CPU time | 2.19 seconds |
| Started | Feb 21 12:26:51 PM PST 24 |
| Finished | Feb 21 12:26:53 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-c7b55ad6-dbbc-4774-bcda-16cc8a31be7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533476992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2533476992 |
| Directory | /workspace/15.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1155431445 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1404841861 ps |
| CPU time | 1.86 seconds |
| Started | Feb 21 12:27:08 PM PST 24 |
| Finished | Feb 21 12:27:10 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-cb32dd12-61ce-43b5-b456-6fc3c9c20027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155431445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 1155431445 |
| Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2427480831 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 59898745 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:27:10 PM PST 24 |
| Finished | Feb 21 12:27:11 PM PST 24 |
| Peak memory | 203516 kb |
| Host | smart-7ea6954f-c86d-4e35-9990-bef8cbb775f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427480831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 2427480831 |
| Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1955281217 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 624896656 ps |
| CPU time | 7.26 seconds |
| Started | Feb 21 12:27:05 PM PST 24 |
| Finished | Feb 21 12:27:13 PM PST 24 |
| Peak memory | 203952 kb |
| Host | smart-fb4dd837-8647-4a0e-8e50-959c719bc60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955281217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.1955281217 |
| Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4063036437 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 133525359 ps |
| CPU time | 2.24 seconds |
| Started | Feb 21 12:27:01 PM PST 24 |
| Finished | Feb 21 12:27:04 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-111c3eab-42f5-494b-a37b-aab636643436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063036437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4063036437 |
| Directory | /workspace/15.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2290098934 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3325048374 ps |
| CPU time | 3.29 seconds |
| Started | Feb 21 12:27:06 PM PST 24 |
| Finished | Feb 21 12:27:10 PM PST 24 |
| Peak memory | 212148 kb |
| Host | smart-c3a69bb2-c6c7-4952-a561-4892515457b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290098934 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2290098934 |
| Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1083554888 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 153736957 ps |
| CPU time | 2.18 seconds |
| Started | Feb 21 12:27:06 PM PST 24 |
| Finished | Feb 21 12:27:09 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-ef02d212-ce79-42ba-a391-ad6182b03c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083554888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1083554888 |
| Directory | /workspace/16.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2096804515 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 817482751 ps |
| CPU time | 1.99 seconds |
| Started | Feb 21 12:27:04 PM PST 24 |
| Finished | Feb 21 12:27:07 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-332652c7-89df-4d43-8789-579eb212ade4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096804515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2096804515 |
| Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3920126700 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 55416263 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:27:32 PM PST 24 |
| Finished | Feb 21 12:27:33 PM PST 24 |
| Peak memory | 203380 kb |
| Host | smart-098c0431-a9aa-4e63-a148-239d2ea3413e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920126700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 3920126700 |
| Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2509290598 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 855577212 ps |
| CPU time | 7.35 seconds |
| Started | Feb 21 12:27:43 PM PST 24 |
| Finished | Feb 21 12:27:51 PM PST 24 |
| Peak memory | 203868 kb |
| Host | smart-b03a8f3f-c66e-4f15-b915-972a0f14e049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509290598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2509290598 |
| Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2699186993 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 279492582 ps |
| CPU time | 4.36 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:28 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-dd26a56f-659e-4186-b633-72780bc2be7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699186993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2699186993 |
| Directory | /workspace/16.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.610226716 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3192121975 ps |
| CPU time | 19.88 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:44 PM PST 24 |
| Peak memory | 215580 kb |
| Host | smart-c773aa2a-1c51-4769-a787-97d7e8af3f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610226716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.610226716 |
| Directory | /workspace/16.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.483407634 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3351756933 ps |
| CPU time | 3.56 seconds |
| Started | Feb 21 12:27:01 PM PST 24 |
| Finished | Feb 21 12:27:06 PM PST 24 |
| Peak memory | 212224 kb |
| Host | smart-45f98c78-de3e-41e8-96ee-583ad76dd1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483407634 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.483407634 |
| Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.998387183 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 86356693 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:27:10 PM PST 24 |
| Finished | Feb 21 12:27:12 PM PST 24 |
| Peak memory | 204032 kb |
| Host | smart-73943df6-5fa9-4fa8-b2e3-f102175b2839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998387183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.998387183 |
| Directory | /workspace/17.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1272555745 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 277442841 ps |
| CPU time | 1.82 seconds |
| Started | Feb 21 12:27:06 PM PST 24 |
| Finished | Feb 21 12:27:08 PM PST 24 |
| Peak memory | 203776 kb |
| Host | smart-092d9506-3bc4-4a7e-ae0e-0027db5cacf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272555745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 1272555745 |
| Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3126839211 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 56276676 ps |
| CPU time | 0.73 seconds |
| Started | Feb 21 12:27:10 PM PST 24 |
| Finished | Feb 21 12:27:11 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-c5cc392d-5670-4c9a-8a29-3c2e0a9c210f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126839211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 3126839211 |
| Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3501643331 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 269984079 ps |
| CPU time | 4.05 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:28 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-bcbec7ca-3dfb-467c-a8ff-89a388d1c409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501643331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.3501643331 |
| Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2086840031 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3131245807 ps |
| CPU time | 4.91 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:29 PM PST 24 |
| Peak memory | 219408 kb |
| Host | smart-bc709a09-2a25-437f-974f-c87aebe3906d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086840031 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2086840031 |
| Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.229492191 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 70819148 ps |
| CPU time | 1.41 seconds |
| Started | Feb 21 12:27:30 PM PST 24 |
| Finished | Feb 21 12:27:32 PM PST 24 |
| Peak memory | 202960 kb |
| Host | smart-e1aacb48-ce28-4da8-bcb1-ac4d732c8f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229492191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.229492191 |
| Directory | /workspace/18.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.117625130 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 363231747 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:27:43 PM PST 24 |
| Finished | Feb 21 12:27:45 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-fef39704-2db8-4451-b25c-d13a3e506e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117625130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.117625130 |
| Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2182228203 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 102894440 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:27:12 PM PST 24 |
| Finished | Feb 21 12:27:14 PM PST 24 |
| Peak memory | 202328 kb |
| Host | smart-40c6089e-5f39-41f9-8c5f-b21e124a5b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182228203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 2182228203 |
| Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4176988013 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 829844343 ps |
| CPU time | 7.65 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:32 PM PST 24 |
| Peak memory | 203920 kb |
| Host | smart-d7d0025f-2974-4af1-bb94-5515a762aba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176988013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.4176988013 |
| Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1462069181 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 167311441 ps |
| CPU time | 5.09 seconds |
| Started | Feb 21 12:27:09 PM PST 24 |
| Finished | Feb 21 12:27:15 PM PST 24 |
| Peak memory | 203976 kb |
| Host | smart-a1b090c8-a6ab-4774-8dc4-4d94b235538e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462069181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1462069181 |
| Directory | /workspace/18.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.831339795 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3382136858 ps |
| CPU time | 18.09 seconds |
| Started | Feb 21 12:27:25 PM PST 24 |
| Finished | Feb 21 12:27:44 PM PST 24 |
| Peak memory | 212896 kb |
| Host | smart-ebdaae5d-b6ea-44b1-aeb5-723109772733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831339795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.831339795 |
| Directory | /workspace/18.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2730844823 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4172740075 ps |
| CPU time | 3.51 seconds |
| Started | Feb 21 12:27:07 PM PST 24 |
| Finished | Feb 21 12:27:12 PM PST 24 |
| Peak memory | 212700 kb |
| Host | smart-578e3ff6-c1af-4d47-98d3-5c3b5944ff1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730844823 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2730844823 |
| Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1371367811 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 96891786 ps |
| CPU time | 2.04 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:26 PM PST 24 |
| Peak memory | 211680 kb |
| Host | smart-51f8170b-2379-4014-8fb1-5b38e71f04f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371367811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1371367811 |
| Directory | /workspace/19.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2529863779 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 40817290 ps |
| CPU time | 0.88 seconds |
| Started | Feb 21 12:27:12 PM PST 24 |
| Finished | Feb 21 12:27:13 PM PST 24 |
| Peak memory | 202668 kb |
| Host | smart-fb46a800-c8fd-4f03-99f7-67908f920025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529863779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2529863779 |
| Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1546330644 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 792231571 ps |
| CPU time | 6.11 seconds |
| Started | Feb 21 12:27:12 PM PST 24 |
| Finished | Feb 21 12:27:18 PM PST 24 |
| Peak memory | 203764 kb |
| Host | smart-0cc11e61-9d0b-49a5-9d89-deb7fa1cf6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546330644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1546330644 |
| Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3108976179 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 87656192 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 12:27:07 PM PST 24 |
| Finished | Feb 21 12:27:10 PM PST 24 |
| Peak memory | 212160 kb |
| Host | smart-ce2cde1e-1ccf-462a-bd71-5231de0d30e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108976179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3108976179 |
| Directory | /workspace/19.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1789428921 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2830453122 ps |
| CPU time | 18.02 seconds |
| Started | Feb 21 12:27:15 PM PST 24 |
| Finished | Feb 21 12:27:34 PM PST 24 |
| Peak memory | 215764 kb |
| Host | smart-7412f0f5-60c5-4387-902e-c01cd800b3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789428921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1 789428921 |
| Directory | /workspace/19.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3220806461 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3755472387 ps |
| CPU time | 28.51 seconds |
| Started | Feb 21 12:27:48 PM PST 24 |
| Finished | Feb 21 12:28:17 PM PST 24 |
| Peak memory | 203152 kb |
| Host | smart-7f8ac153-d4ec-450d-aa78-823e5fa10be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220806461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.3220806461 |
| Directory | /workspace/2.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3475713730 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 48492330939 ps |
| CPU time | 36.44 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:44 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-686ce574-4cb7-4d52-a4bd-50305e379eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475713730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3475713730 |
| Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.565095765 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 665218336 ps |
| CPU time | 2.4 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:20 PM PST 24 |
| Peak memory | 203868 kb |
| Host | smart-91fb2351-46fd-4455-9937-3d81a28d8bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565095765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.565095765 |
| Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.806361731 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2545952903 ps |
| CPU time | 4.16 seconds |
| Started | Feb 21 12:27:46 PM PST 24 |
| Finished | Feb 21 12:27:51 PM PST 24 |
| Peak memory | 213856 kb |
| Host | smart-961d150b-c1a8-42b3-b2cb-d80a3fe32b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806361731 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.806361731 |
| Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.51219981 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 109467538 ps |
| CPU time | 2.55 seconds |
| Started | Feb 21 12:26:00 PM PST 24 |
| Finished | Feb 21 12:26:03 PM PST 24 |
| Peak memory | 212464 kb |
| Host | smart-fc7e8693-6ac2-436c-8cab-00f3c6df50c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51219981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.51219981 |
| Directory | /workspace/2.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.621010352 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 14152133115 ps |
| CPU time | 8.3 seconds |
| Started | Feb 21 12:25:46 PM PST 24 |
| Finished | Feb 21 12:25:55 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-968d473d-e9af-4a3f-b07a-2f90ea08fe47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621010352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _aliasing.621010352 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4171410554 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 14125975430 ps |
| CPU time | 23.03 seconds |
| Started | Feb 21 12:25:40 PM PST 24 |
| Finished | Feb 21 12:26:04 PM PST 24 |
| Peak memory | 203684 kb |
| Host | smart-56792558-3eed-404f-b1e3-b3c3df6111ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171410554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_bit_bash.4171410554 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.944327777 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 461631774 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 12:27:47 PM PST 24 |
| Finished | Feb 21 12:27:49 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-e5446ca9-16ba-48b1-b580-18ef1b49d5bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944327777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _hw_reset.944327777 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.562060178 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 370356910 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:27:59 PM PST 24 |
| Finished | Feb 21 12:28:01 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-6a994924-7c11-4b84-a13b-20b4cf7d1ff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562060178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.562060178 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.181150045 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 218072287 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:26:01 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-4424bc9b-4636-446a-9316-f27247408d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181150045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _aliasing.181150045 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.782886878 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2237576865 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 12:25:43 PM PST 24 |
| Finished | Feb 21 12:25:45 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-e3c98db1-5da6-448e-ad74-4a2b4b439dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782886878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _bit_bash.782886878 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1634061267 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 169472352 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:27:37 PM PST 24 |
| Finished | Feb 21 12:27:38 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-b7740453-0e1a-4386-8a21-861f39fc9531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634061267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.1634061267 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1278695957 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 74518699 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:27:48 PM PST 24 |
| Finished | Feb 21 12:27:49 PM PST 24 |
| Peak memory | 203024 kb |
| Host | smart-81ea53c9-132d-4926-84f6-ff4c722663bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278695957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 278695957 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1342498999 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 22544501 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:25:57 PM PST 24 |
| Finished | Feb 21 12:25:58 PM PST 24 |
| Peak memory | 203652 kb |
| Host | smart-9b531e09-acc4-451d-8707-4c9335a8e130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342498999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1342498999 |
| Directory | /workspace/2.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3684990650 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 27995996 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:25:57 PM PST 24 |
| Finished | Feb 21 12:25:58 PM PST 24 |
| Peak memory | 203524 kb |
| Host | smart-89df98c0-b9c1-4022-b70b-5af311caf6b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684990650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3684990650 |
| Directory | /workspace/2.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3279107080 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 736922838 ps |
| CPU time | 3.77 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:11 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-6f5fc878-c304-4576-9674-ddc9f4692b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279107080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3279107080 |
| Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3700844546 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 342889194 ps |
| CPU time | 5.1 seconds |
| Started | Feb 21 12:25:46 PM PST 24 |
| Finished | Feb 21 12:25:51 PM PST 24 |
| Peak memory | 212568 kb |
| Host | smart-178b1379-010d-4e69-a215-de4e47d9198f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700844546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3700844546 |
| Directory | /workspace/2.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3988656670 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8012798403 ps |
| CPU time | 15.89 seconds |
| Started | Feb 21 12:27:25 PM PST 24 |
| Finished | Feb 21 12:27:41 PM PST 24 |
| Peak memory | 211972 kb |
| Host | smart-eeb79573-e4cc-4d25-af6d-a69122199b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988656670 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.3988656670 |
| Directory | /workspace/21.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.878663236 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 5263277179 ps |
| CPU time | 17.52 seconds |
| Started | Feb 21 12:27:06 PM PST 24 |
| Finished | Feb 21 12:27:24 PM PST 24 |
| Peak memory | 219624 kb |
| Host | smart-c2b8f2f3-5886-477c-b683-71b6d8eab88e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878663236 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.878663236 |
| Directory | /workspace/23.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.3519493211 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 23718003506 ps |
| CPU time | 23.55 seconds |
| Started | Feb 21 12:27:07 PM PST 24 |
| Finished | Feb 21 12:27:31 PM PST 24 |
| Peak memory | 220872 kb |
| Host | smart-2c5693a5-8619-4528-9510-1889a65f0265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519493211 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.3519493211 |
| Directory | /workspace/26.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.551108731 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4159906479 ps |
| CPU time | 14.12 seconds |
| Started | Feb 21 12:27:15 PM PST 24 |
| Finished | Feb 21 12:27:30 PM PST 24 |
| Peak memory | 220316 kb |
| Host | smart-456e7154-1419-4914-824f-383c88cf9ff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551108731 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.551108731 |
| Directory | /workspace/27.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.505323993 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1455630972 ps |
| CPU time | 52.19 seconds |
| Started | Feb 21 12:26:20 PM PST 24 |
| Finished | Feb 21 12:27:12 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-2ffea2a1-5808-470f-a9e3-cca4b1d4ffee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505323993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.505323993 |
| Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2655788381 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 110994646 ps |
| CPU time | 1.4 seconds |
| Started | Feb 21 12:27:46 PM PST 24 |
| Finished | Feb 21 12:27:48 PM PST 24 |
| Peak memory | 202700 kb |
| Host | smart-a30d0122-cba0-44a6-bf97-fd6a5a4b35d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655788381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2655788381 |
| Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.161984996 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 576052314 ps |
| CPU time | 2.51 seconds |
| Started | Feb 21 12:26:03 PM PST 24 |
| Finished | Feb 21 12:26:05 PM PST 24 |
| Peak memory | 212544 kb |
| Host | smart-742dd31d-da83-4339-9f3a-927343f3db19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161984996 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.161984996 |
| Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1827369854 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 128001680 ps |
| CPU time | 2.13 seconds |
| Started | Feb 21 12:27:51 PM PST 24 |
| Finished | Feb 21 12:27:54 PM PST 24 |
| Peak memory | 202940 kb |
| Host | smart-712c8405-5622-4412-b284-12c86a16c2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827369854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1827369854 |
| Directory | /workspace/3.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3418563072 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8429691689 ps |
| CPU time | 18.36 seconds |
| Started | Feb 21 12:28:15 PM PST 24 |
| Finished | Feb 21 12:28:36 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-b6d584fb-91f6-4e46-b830-3f267b0e7737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418563072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.3418563072 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2347932550 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3765111403 ps |
| CPU time | 14.72 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:26:14 PM PST 24 |
| Peak memory | 203740 kb |
| Host | smart-398be8fd-85bb-43ca-a038-77cfe6665acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347932550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_bit_bash.2347932550 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.543751923 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1089995950 ps |
| CPU time | 4.64 seconds |
| Started | Feb 21 12:26:17 PM PST 24 |
| Finished | Feb 21 12:26:22 PM PST 24 |
| Peak memory | 204256 kb |
| Host | smart-0b081d20-8d62-40ab-b18a-bf55d9d0fc83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543751923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _hw_reset.543751923 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1174065782 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 282522958 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 12:26:20 PM PST 24 |
| Finished | Feb 21 12:26:21 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-c6051beb-5f31-4175-91bc-fb445b6e579c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174065782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 174065782 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1160062904 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 130866649 ps |
| CPU time | 0.74 seconds |
| Started | Feb 21 12:27:47 PM PST 24 |
| Finished | Feb 21 12:27:49 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-3d814fc0-dcdf-4590-b6db-2ae0e6da9be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160062904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.1160062904 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4057853512 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 746394953 ps |
| CPU time | 3.26 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:26:02 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-6e7dd7eb-47d8-4385-8029-a0121c515fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057853512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.4057853512 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.734108362 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 29749654 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:27:37 PM PST 24 |
| Finished | Feb 21 12:27:38 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-65113f89-e02e-4218-9b0c-ebb617f8d29e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734108362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _hw_reset.734108362 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.146684646 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 136688497 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:26:09 PM PST 24 |
| Finished | Feb 21 12:26:11 PM PST 24 |
| Peak memory | 202660 kb |
| Host | smart-f1a1e430-59b4-4324-9c7f-c05ec5c20af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146684646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.146684646 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3563554179 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14078704 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:18 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-659491ea-5008-432c-9205-f62fa688fc45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563554179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.3563554179 |
| Directory | /workspace/3.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1425989958 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 20180225 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:27:46 PM PST 24 |
| Finished | Feb 21 12:27:47 PM PST 24 |
| Peak memory | 202712 kb |
| Host | smart-3379e1ee-ccd3-4846-94ad-37f20d42a0ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425989958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1425989958 |
| Directory | /workspace/3.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1771054957 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 590467796 ps |
| CPU time | 4.1 seconds |
| Started | Feb 21 12:26:20 PM PST 24 |
| Finished | Feb 21 12:26:24 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-533fe157-2eff-4be5-a798-2545d7b60d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771054957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1771054957 |
| Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2273565918 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 142155471 ps |
| CPU time | 3.21 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:21 PM PST 24 |
| Peak memory | 212140 kb |
| Host | smart-faf7cf94-790b-48e5-b212-ea1b3e901bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273565918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2273565918 |
| Directory | /workspace/3.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1377726830 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1526739125 ps |
| CPU time | 14.74 seconds |
| Started | Feb 21 12:26:02 PM PST 24 |
| Finished | Feb 21 12:26:17 PM PST 24 |
| Peak memory | 212088 kb |
| Host | smart-a41ac8df-3323-4d17-a178-73a8aa965453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377726830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1377726830 |
| Directory | /workspace/3.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1496508211 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5155915439 ps |
| CPU time | 16.67 seconds |
| Started | Feb 21 12:27:24 PM PST 24 |
| Finished | Feb 21 12:27:41 PM PST 24 |
| Peak memory | 214988 kb |
| Host | smart-85d44300-7d5a-4ce0-9ec3-c6d9c97527e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496508211 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1496508211 |
| Directory | /workspace/32.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.1058623939 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 11988562680 ps |
| CPU time | 17.12 seconds |
| Started | Feb 21 12:27:22 PM PST 24 |
| Finished | Feb 21 12:27:39 PM PST 24 |
| Peak memory | 216036 kb |
| Host | smart-865f1ac3-71a8-401a-beab-445eef36250d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058623939 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.1058623939 |
| Directory | /workspace/37.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3930175255 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6615096752 ps |
| CPU time | 14.12 seconds |
| Started | Feb 21 12:27:25 PM PST 24 |
| Finished | Feb 21 12:27:40 PM PST 24 |
| Peak memory | 219624 kb |
| Host | smart-7b328b47-2cab-4fa5-bf81-295e9fe9f2ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930175255 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.3930175255 |
| Directory | /workspace/38.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3003334976 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4069408543 ps |
| CPU time | 30.13 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:48 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-e39d8b86-9017-479c-ae45-6b55623d1d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003334976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.3003334976 |
| Directory | /workspace/4.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3923863808 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2437045761 ps |
| CPU time | 30.65 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:28:04 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-214700d8-409e-43ce-b1cd-3cc4c1fa01ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923863808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3923863808 |
| Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3199774872 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 72430208 ps |
| CPU time | 1.61 seconds |
| Started | Feb 21 12:26:14 PM PST 24 |
| Finished | Feb 21 12:26:16 PM PST 24 |
| Peak memory | 204024 kb |
| Host | smart-ce5543e1-ae45-4f00-add3-977d1e5bce6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199774872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3199774872 |
| Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.708323563 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4189690032 ps |
| CPU time | 6.71 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:40 PM PST 24 |
| Peak memory | 213620 kb |
| Host | smart-c6a4b488-2dae-476d-b74f-10b40aec43f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708323563 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.708323563 |
| Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1349246309 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 297977665 ps |
| CPU time | 2.33 seconds |
| Started | Feb 21 12:26:11 PM PST 24 |
| Finished | Feb 21 12:26:13 PM PST 24 |
| Peak memory | 211864 kb |
| Host | smart-1932cfa9-bc7d-45f0-8408-613717c5d126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349246309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1349246309 |
| Directory | /workspace/4.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2513005859 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6557199392 ps |
| CPU time | 24.39 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:58 PM PST 24 |
| Peak memory | 202336 kb |
| Host | smart-1e5c71f0-369d-42c5-8545-e93616ca366a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513005859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.2513005859 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2385753979 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1958804326 ps |
| CPU time | 6.45 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:14 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-8d4d2313-a4ff-4e3a-b1f8-70bbdbd7e6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385753979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2385753979 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4062850117 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 469015901 ps |
| CPU time | 1.53 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:19 PM PST 24 |
| Peak memory | 203736 kb |
| Host | smart-3061270f-50a2-46e9-9ece-c011a7e706e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062850117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4 062850117 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.662436123 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 207246106 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:19 PM PST 24 |
| Peak memory | 203504 kb |
| Host | smart-88f88a00-8efe-4a35-9778-2d616fce749b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662436123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.662436123 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3856184139 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2492462177 ps |
| CPU time | 2.64 seconds |
| Started | Feb 21 12:28:14 PM PST 24 |
| Finished | Feb 21 12:28:21 PM PST 24 |
| Peak memory | 203752 kb |
| Host | smart-77a2b2ee-3805-4b57-a50d-52159b8a5f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856184139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.3856184139 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.261480726 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 182441037 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:27:37 PM PST 24 |
| Finished | Feb 21 12:27:38 PM PST 24 |
| Peak memory | 202604 kb |
| Host | smart-86df3439-f5b0-4250-b9d3-074f747c8773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261480726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _hw_reset.261480726 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1142652802 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 46816946 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:27:52 PM PST 24 |
| Finished | Feb 21 12:27:53 PM PST 24 |
| Peak memory | 203128 kb |
| Host | smart-8ad10bc2-16ca-43a6-b3ae-9a867320e3db |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142652802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 142652802 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4083365711 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 27252350 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:26:27 PM PST 24 |
| Finished | Feb 21 12:26:28 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-644b107d-bd84-42d4-acb1-e9a096b59cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083365711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.4083365711 |
| Directory | /workspace/4.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1385585398 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 56888937 ps |
| CPU time | 0.58 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:34 PM PST 24 |
| Peak memory | 203116 kb |
| Host | smart-9a318665-23ae-4e00-91f4-9273fadfacf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385585398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1385585398 |
| Directory | /workspace/4.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3599914582 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 311382074 ps |
| CPU time | 4.05 seconds |
| Started | Feb 21 12:26:11 PM PST 24 |
| Finished | Feb 21 12:26:16 PM PST 24 |
| Peak memory | 203916 kb |
| Host | smart-95bc5777-a55d-4375-8211-0cfe39024533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599914582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.3599914582 |
| Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2440884958 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 64938376 ps |
| CPU time | 3.55 seconds |
| Started | Feb 21 12:26:10 PM PST 24 |
| Finished | Feb 21 12:26:13 PM PST 24 |
| Peak memory | 211984 kb |
| Host | smart-8351d46c-2135-4a16-b29b-9e537d34e2ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440884958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2440884958 |
| Directory | /workspace/4.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3122418165 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 714236449 ps |
| CPU time | 14.23 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:48 PM PST 24 |
| Peak memory | 210644 kb |
| Host | smart-b532bf02-0905-40fc-8182-7aed2431c9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122418165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3122418165 |
| Directory | /workspace/4.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.973187261 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 112761464 ps |
| CPU time | 2.21 seconds |
| Started | Feb 21 12:27:34 PM PST 24 |
| Finished | Feb 21 12:27:37 PM PST 24 |
| Peak memory | 219996 kb |
| Host | smart-6d583f4d-38a5-453b-b18a-fbbd03702ade |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973187261 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.973187261 |
| Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3041548235 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 197620205 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:35 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-dc7e7686-5363-40f4-a1d4-c99a5cf52ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041548235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3041548235 |
| Directory | /workspace/5.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3016681186 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 686480554 ps |
| CPU time | 2.57 seconds |
| Started | Feb 21 12:26:28 PM PST 24 |
| Finished | Feb 21 12:26:32 PM PST 24 |
| Peak memory | 203408 kb |
| Host | smart-36d6d75c-afb5-4df0-ae3b-bc745b073172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016681186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 016681186 |
| Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.560305656 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 26709051 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:26:17 PM PST 24 |
| Finished | Feb 21 12:26:18 PM PST 24 |
| Peak memory | 203296 kb |
| Host | smart-be6d65fa-d9d6-4869-b2a8-1cecef4445ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560305656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.560305656 |
| Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1647468464 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 163856062 ps |
| CPU time | 3.7 seconds |
| Started | Feb 21 12:26:15 PM PST 24 |
| Finished | Feb 21 12:26:19 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-6dd9407d-eab7-4211-8b4b-941a595a5fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647468464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1647468464 |
| Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2005035968 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 282412208 ps |
| CPU time | 3.61 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:38 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-877006d1-1c39-4d62-9fe0-510cbf048bf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005035968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2005035968 |
| Directory | /workspace/5.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2606562761 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3755994764 ps |
| CPU time | 15.99 seconds |
| Started | Feb 21 12:26:28 PM PST 24 |
| Finished | Feb 21 12:26:45 PM PST 24 |
| Peak memory | 212564 kb |
| Host | smart-38bf3f98-9c0e-4638-8ffd-64e4bcad95be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606562761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2606562761 |
| Directory | /workspace/5.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1721875904 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5317993906 ps |
| CPU time | 6.98 seconds |
| Started | Feb 21 12:28:04 PM PST 24 |
| Finished | Feb 21 12:28:11 PM PST 24 |
| Peak memory | 220008 kb |
| Host | smart-ec29a9e4-a19c-493c-9a6c-f5f031c4d363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721875904 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1721875904 |
| Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3432124923 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 102683275 ps |
| CPU time | 1.44 seconds |
| Started | Feb 21 12:27:33 PM PST 24 |
| Finished | Feb 21 12:27:36 PM PST 24 |
| Peak memory | 203532 kb |
| Host | smart-3fc184ad-978a-4291-9873-3788ef6fa557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432124923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3432124923 |
| Directory | /workspace/6.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2758552846 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 584883189 ps |
| CPU time | 2.56 seconds |
| Started | Feb 21 12:26:10 PM PST 24 |
| Finished | Feb 21 12:26:12 PM PST 24 |
| Peak memory | 203760 kb |
| Host | smart-d753f61e-3ee1-499c-b4b1-829daad74f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758552846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 758552846 |
| Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3477408742 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 78197119 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:27:34 PM PST 24 |
| Finished | Feb 21 12:27:35 PM PST 24 |
| Peak memory | 203320 kb |
| Host | smart-087a336c-b7b1-4e78-80ad-12777e4fd334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477408742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 477408742 |
| Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3829199359 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 210540285 ps |
| CPU time | 3.77 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:12 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-102f4143-7f97-4141-a770-e422f789538d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829199359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.3829199359 |
| Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3823331310 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 83233388 ps |
| CPU time | 5.01 seconds |
| Started | Feb 21 12:26:08 PM PST 24 |
| Finished | Feb 21 12:26:15 PM PST 24 |
| Peak memory | 212152 kb |
| Host | smart-24b5f982-8c56-4e4c-a023-8921982712cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823331310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3823331310 |
| Directory | /workspace/6.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2419002868 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1431849969 ps |
| CPU time | 16.25 seconds |
| Started | Feb 21 12:26:06 PM PST 24 |
| Finished | Feb 21 12:26:23 PM PST 24 |
| Peak memory | 212284 kb |
| Host | smart-30ecef5c-8960-46f3-b86a-ea05284cb31c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419002868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2419002868 |
| Directory | /workspace/6.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3871406015 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1625189824 ps |
| CPU time | 4.3 seconds |
| Started | Feb 21 12:26:11 PM PST 24 |
| Finished | Feb 21 12:26:16 PM PST 24 |
| Peak memory | 220512 kb |
| Host | smart-d880ffe2-3f77-4cdc-9cb0-0a50d7fdf48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871406015 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3871406015 |
| Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3522222421 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 48821149 ps |
| CPU time | 1.95 seconds |
| Started | Feb 21 12:28:04 PM PST 24 |
| Finished | Feb 21 12:28:06 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-6e74db4e-f771-401f-93df-80b733764471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522222421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3522222421 |
| Directory | /workspace/7.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2252309377 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 653715247 ps |
| CPU time | 2.79 seconds |
| Started | Feb 21 12:26:13 PM PST 24 |
| Finished | Feb 21 12:26:16 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-0c8d89a2-d9ad-424a-9066-0547b7ee0589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252309377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2 252309377 |
| Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3722731942 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 70463534 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:09 PM PST 24 |
| Peak memory | 203420 kb |
| Host | smart-93483cb4-35ce-41aa-8178-0f0841e35792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722731942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3 722731942 |
| Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.915328829 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2170198981 ps |
| CPU time | 7.48 seconds |
| Started | Feb 21 12:28:06 PM PST 24 |
| Finished | Feb 21 12:28:14 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-4504492e-2fa9-4453-ab2d-bf3ed19c5fad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915328829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c sr_outstanding.915328829 |
| Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1061580768 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 374409195 ps |
| CPU time | 2.88 seconds |
| Started | Feb 21 12:27:42 PM PST 24 |
| Finished | Feb 21 12:27:46 PM PST 24 |
| Peak memory | 210544 kb |
| Host | smart-fe5e8a24-efe4-4d30-99f9-0dbc55cb0ce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061580768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1061580768 |
| Directory | /workspace/7.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2114680452 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 997438489 ps |
| CPU time | 17.21 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:25 PM PST 24 |
| Peak memory | 214468 kb |
| Host | smart-b75d856a-706b-4c86-9035-ba0f55101014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114680452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2114680452 |
| Directory | /workspace/7.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.502980350 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1162841373 ps |
| CPU time | 5.14 seconds |
| Started | Feb 21 12:27:42 PM PST 24 |
| Finished | Feb 21 12:27:48 PM PST 24 |
| Peak memory | 213868 kb |
| Host | smart-22f7a621-fd32-453a-b33a-14f290bfc1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502980350 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.502980350 |
| Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.560825409 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 62310329 ps |
| CPU time | 2.03 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:10 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-16ba84a2-e3cb-434f-8770-cf3fea39192f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560825409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.560825409 |
| Directory | /workspace/8.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3327473936 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 168476382 ps |
| CPU time | 1.23 seconds |
| Started | Feb 21 12:28:04 PM PST 24 |
| Finished | Feb 21 12:28:06 PM PST 24 |
| Peak memory | 203728 kb |
| Host | smart-fd7caefe-a28d-49ff-8895-cc60a05101e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327473936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 327473936 |
| Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.688913489 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 111674079 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:26:27 PM PST 24 |
| Finished | Feb 21 12:26:29 PM PST 24 |
| Peak memory | 203188 kb |
| Host | smart-bb3080b4-5b7e-4219-93fe-a950237c2d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688913489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.688913489 |
| Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3555006266 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 151745811 ps |
| CPU time | 3.49 seconds |
| Started | Feb 21 12:26:13 PM PST 24 |
| Finished | Feb 21 12:26:16 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-10d9450a-a021-4c29-af36-631eb68d12bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555006266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3555006266 |
| Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.946997657 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 13858369007 ps |
| CPU time | 38.34 seconds |
| Started | Feb 21 12:28:04 PM PST 24 |
| Finished | Feb 21 12:28:43 PM PST 24 |
| Peak memory | 220436 kb |
| Host | smart-75926160-a748-43fc-b8fc-f4170a5dd408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946997657 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.946997657 |
| Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4218562556 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 431755118 ps |
| CPU time | 3.53 seconds |
| Started | Feb 21 12:28:04 PM PST 24 |
| Finished | Feb 21 12:28:08 PM PST 24 |
| Peak memory | 211788 kb |
| Host | smart-358a268d-2a94-4daa-8f98-e3f68fdb2d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218562556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4218562556 |
| Directory | /workspace/8.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.239689353 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 835626613 ps |
| CPU time | 14.29 seconds |
| Started | Feb 21 12:28:05 PM PST 24 |
| Finished | Feb 21 12:28:20 PM PST 24 |
| Peak memory | 212192 kb |
| Host | smart-07219ac8-7640-4f62-9d9b-560ef3e5f44b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239689353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.239689353 |
| Directory | /workspace/8.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2312917481 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3045464431 ps |
| CPU time | 3.27 seconds |
| Started | Feb 21 12:26:31 PM PST 24 |
| Finished | Feb 21 12:26:35 PM PST 24 |
| Peak memory | 212328 kb |
| Host | smart-8083e4ee-be2e-4218-b235-246a3579af16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312917481 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2312917481 |
| Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2645648124 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 212220015 ps |
| CPU time | 1.61 seconds |
| Started | Feb 21 12:26:34 PM PST 24 |
| Finished | Feb 21 12:26:36 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-ecb212b1-b81b-4cab-a67e-52069a3a6bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645648124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2645648124 |
| Directory | /workspace/9.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.745631460 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 150456578 ps |
| CPU time | 0.9 seconds |
| Started | Feb 21 12:27:42 PM PST 24 |
| Finished | Feb 21 12:27:44 PM PST 24 |
| Peak memory | 202884 kb |
| Host | smart-d4d7035c-cc94-4667-8822-be30466cd632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745631460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.745631460 |
| Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.249649087 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 196613934 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:28:07 PM PST 24 |
| Finished | Feb 21 12:28:09 PM PST 24 |
| Peak memory | 203444 kb |
| Host | smart-e4bc6ab7-bdbd-431a-a17f-aac663ff4d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249649087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.249649087 |
| Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1073442496 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 137586610 ps |
| CPU time | 6.02 seconds |
| Started | Feb 21 12:28:19 PM PST 24 |
| Finished | Feb 21 12:28:26 PM PST 24 |
| Peak memory | 203440 kb |
| Host | smart-7524b707-b5f6-4b28-885f-34d8f4230253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073442496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.1073442496 |
| Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2395994594 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 386393880 ps |
| CPU time | 2.7 seconds |
| Started | Feb 21 12:28:06 PM PST 24 |
| Finished | Feb 21 12:28:09 PM PST 24 |
| Peak memory | 212144 kb |
| Host | smart-5184ac2d-b63a-45de-830b-fb5e223c4cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395994594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2395994594 |
| Directory | /workspace/9.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4094452636 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1249436456 ps |
| CPU time | 17.21 seconds |
| Started | Feb 21 12:28:18 PM PST 24 |
| Finished | Feb 21 12:28:36 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-d7c2ded9-1b05-480f-9bde-cfc3285d4a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094452636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.4094452636 |
| Directory | /workspace/9.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_dm_alert_test.1087234048 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 126089401 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:29:10 PM PST 24 |
| Finished | Feb 21 12:29:11 PM PST 24 |
| Peak memory | 203900 kb |
| Host | smart-7bf73a88-9c50-4b02-85b2-0bc25882a114 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087234048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1087234048 |
| Directory | /workspace/0.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2558005644 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 13553044231 ps |
| CPU time | 19.65 seconds |
| Started | Feb 21 12:29:23 PM PST 24 |
| Finished | Feb 21 12:29:44 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-a7221ff1-ec8d-4b27-947b-c53fabaec54d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558005644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2558005644 |
| Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.244406094 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1838539494 ps |
| CPU time | 3.93 seconds |
| Started | Feb 21 12:29:04 PM PST 24 |
| Finished | Feb 21 12:29:09 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-9169527c-c97b-4f5f-8e21-a75204f4b24c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244406094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.244406094 |
| Directory | /workspace/0.rv_dm_cmderr_busy/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2028002181 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 965506580 ps |
| CPU time | 1.92 seconds |
| Started | Feb 21 12:29:09 PM PST 24 |
| Finished | Feb 21 12:29:11 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-349fe89e-9d8e-43a2-94e0-1b9a1e7bb86f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028002181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2028002181 |
| Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.741370868 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 38554174 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:29:11 PM PST 24 |
| Finished | Feb 21 12:29:12 PM PST 24 |
| Peak memory | 203604 kb |
| Host | smart-dfe2bbe7-eb84-4482-b47c-28c1d945a70a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=741370868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.741370868 |
| Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3525298329 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1810408519 ps |
| CPU time | 4.44 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:24 PM PST 24 |
| Peak memory | 204372 kb |
| Host | smart-5a31cb37-c879-4664-9b39-4aee911f3002 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3525298329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.3525298329 |
| Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1587713861 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 275337498 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:29:25 PM PST 24 |
| Finished | Feb 21 12:29:27 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-c342d8a0-0bcc-40f7-ac4d-56703115f4cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1587713861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1587713861 |
| Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.255951315 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 140233336 ps |
| CPU time | 1.04 seconds |
| Started | Feb 21 12:29:19 PM PST 24 |
| Finished | Feb 21 12:29:22 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-ae5a97ae-7785-4491-95ef-1ac46b21dd83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255951315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.255951315 |
| Directory | /workspace/0.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2557039011 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 241365988 ps |
| CPU time | 0.79 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:21 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-7c936f90-e86b-4490-96ad-9ec791ec3495 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557039011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2557039011 |
| Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1854727064 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 41711222 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:29:13 PM PST 24 |
| Finished | Feb 21 12:29:14 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-92761319-6f57-4b83-9a2c-247115aa7ca7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854727064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1854727064 |
| Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.993836260 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 53240754 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:29:08 PM PST 24 |
| Finished | Feb 21 12:29:09 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-814627d9-8e5b-4e1f-bf93-b1bd52116d1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993836260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.993836260 |
| Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4081036121 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 111187925 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:29:20 PM PST 24 |
| Finished | Feb 21 12:29:22 PM PST 24 |
| Peak memory | 203996 kb |
| Host | smart-601ee5d9-a3fc-43d0-920f-8552697df4e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081036121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4081036121 |
| Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.312199147 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 449479476 ps |
| CPU time | 1.43 seconds |
| Started | Feb 21 12:29:11 PM PST 24 |
| Finished | Feb 21 12:29:12 PM PST 24 |
| Peak memory | 204096 kb |
| Host | smart-f3505ff6-a3b5-4bc1-b4c7-95264ffebae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312199147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.312199147 |
| Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.3067148070 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 888117930 ps |
| CPU time | 2.44 seconds |
| Started | Feb 21 12:29:33 PM PST 24 |
| Finished | Feb 21 12:29:35 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-607a9d75-5a2e-4a80-9401-a6e58a668972 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067148070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3067148070 |
| Directory | /workspace/0.rv_dm_ndmreset_req/latest |
| Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.1242760186 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2219894553 ps |
| CPU time | 5.85 seconds |
| Started | Feb 21 12:29:09 PM PST 24 |
| Finished | Feb 21 12:29:15 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-a5d8d9a7-54b0-4fee-b664-c424f3cec65a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242760186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1242760186 |
| Directory | /workspace/0.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_smoke.2662598775 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 891381880 ps |
| CPU time | 1.6 seconds |
| Started | Feb 21 12:29:19 PM PST 24 |
| Finished | Feb 21 12:29:22 PM PST 24 |
| Peak memory | 203984 kb |
| Host | smart-b8cf91e4-f529-4199-a5bd-cfeecc94d5a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662598775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2662598775 |
| Directory | /workspace/0.rv_dm_smoke/latest |
| Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1664652072 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5249999340 ps |
| CPU time | 3.62 seconds |
| Started | Feb 21 12:29:19 PM PST 24 |
| Finished | Feb 21 12:29:24 PM PST 24 |
| Peak memory | 203976 kb |
| Host | smart-ae6200c2-759f-4a49-b9f7-0776540c68c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664652072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1664652072 |
| Directory | /workspace/0.rv_dm_tap_fsm/latest |
| Test location | /workspace/coverage/default/1.rv_dm_alert_test.4133143490 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 18299216 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:31 PM PST 24 |
| Peak memory | 203952 kb |
| Host | smart-c3d7c9cb-efae-46f7-bc20-e7a14c1fc992 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133143490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4133143490 |
| Directory | /workspace/1.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1448028645 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1436000075 ps |
| CPU time | 3.4 seconds |
| Started | Feb 21 12:29:17 PM PST 24 |
| Finished | Feb 21 12:29:20 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-e62b3ddc-059b-420b-b8c3-5a97b40a1757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448028645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1448028645 |
| Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2763972151 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2391586088 ps |
| CPU time | 4.54 seconds |
| Started | Feb 21 12:29:15 PM PST 24 |
| Finished | Feb 21 12:29:20 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-dd7fb1a6-fae3-4083-9692-79ba73f02aa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763972151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2763972151 |
| Directory | /workspace/1.rv_dm_cmderr_busy/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.1304303700 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 209664046 ps |
| CPU time | 0.94 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:20 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-4ae2134c-583c-4f66-9afc-a8e38b012419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304303700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1304303700 |
| Directory | /workspace/1.rv_dm_cmderr_exception/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.39305891 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 293520065 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-d5120c27-daf5-4803-a6a1-7cbf2c58bcbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39305891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.39305891 |
| Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2792964545 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5302356527 ps |
| CPU time | 2.72 seconds |
| Started | Feb 21 12:29:30 PM PST 24 |
| Finished | Feb 21 12:29:33 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-08e059a8-c7d1-4a07-b924-6e45d5bc9256 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2792964545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2792964545 |
| Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.21878684 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 32973532 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:36 PM PST 24 |
| Peak memory | 203852 kb |
| Host | smart-8ded1dc3-1f92-4b67-a310-4e8cded6131b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21878684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.21878684 |
| Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.387300411 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1268286700 ps |
| CPU time | 3.83 seconds |
| Started | Feb 21 12:29:13 PM PST 24 |
| Finished | Feb 21 12:29:18 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-67dafbbb-092f-4ecb-a4f7-7b3729fb661e |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=387300411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl _access.387300411 |
| Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4024268529 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 174457770 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:29:25 PM PST 24 |
| Finished | Feb 21 12:29:27 PM PST 24 |
| Peak memory | 204220 kb |
| Host | smart-9987042e-5a43-444e-a044-35a24eb5a745 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024268529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4024268529 |
| Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.4184795882 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 73578137 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:31 PM PST 24 |
| Peak memory | 203864 kb |
| Host | smart-72ef09fd-d4a9-4cba-953d-a511a3bc3490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184795882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4184795882 |
| Directory | /workspace/1.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2402996280 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 177827225 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:15 PM PST 24 |
| Peak memory | 203824 kb |
| Host | smart-733f77dc-e3cf-454d-8567-66ba6eef5215 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2402996280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2402996280 |
| Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3365783840 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 154423868 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:16 PM PST 24 |
| Peak memory | 203572 kb |
| Host | smart-eb89566f-413f-4012-bf16-d62be2aa946c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365783840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3365783840 |
| Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.4023220388 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 21565294 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:31 PM PST 24 |
| Peak memory | 203656 kb |
| Host | smart-7011bc80-3e29-4dba-97cc-8cf863a0f9d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023220388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.4023220388 |
| Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3288618982 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 108540314 ps |
| CPU time | 0.91 seconds |
| Started | Feb 21 12:29:24 PM PST 24 |
| Finished | Feb 21 12:29:26 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-d7d51002-1434-48bb-b70f-539879e62efa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288618982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3288618982 |
| Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2684805227 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 121434326 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 12:29:09 PM PST 24 |
| Finished | Feb 21 12:29:11 PM PST 24 |
| Peak memory | 203676 kb |
| Host | smart-c03e91f4-92fe-430a-9d56-aac1f5535de9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684805227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2684805227 |
| Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.3833511208 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 156051758 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:29:24 PM PST 24 |
| Finished | Feb 21 12:29:26 PM PST 24 |
| Peak memory | 203876 kb |
| Host | smart-9947a38d-ffa3-4908-ac35-bc4d1026b8fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833511208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3833511208 |
| Directory | /workspace/1.rv_dm_ndmreset_req/latest |
| Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.2014937891 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 334491951 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:19 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-e26d7b71-0b46-4561-89fe-ab759d2dd60b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2014937891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2014937891 |
| Directory | /workspace/1.rv_dm_progbuf_busy/latest |
| Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.3832328608 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1607801635 ps |
| CPU time | 4.14 seconds |
| Started | Feb 21 12:29:13 PM PST 24 |
| Finished | Feb 21 12:29:18 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-313e3a8b-e351-4586-85de-858d7c54d1e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832328608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3832328608 |
| Directory | /workspace/1.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/1.rv_dm_sec_cm.3301212745 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 376124158 ps |
| CPU time | 1.29 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 220152 kb |
| Host | smart-4650f6ab-f1f4-4af3-8e37-280d1c9756bc |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301212745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3301212745 |
| Directory | /workspace/1.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_dm_smoke.1875391117 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 796104268 ps |
| CPU time | 1.24 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 203796 kb |
| Host | smart-8065bb96-5d02-43ba-9ec6-0be39b634ccd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875391117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1875391117 |
| Directory | /workspace/1.rv_dm_smoke/latest |
| Test location | /workspace/coverage/default/10.rv_dm_alert_test.1336313907 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 42326450 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:29:39 PM PST 24 |
| Finished | Feb 21 12:29:40 PM PST 24 |
| Peak memory | 203952 kb |
| Host | smart-f2d47536-e968-4534-914e-b9b3c36ffd63 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336313907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1336313907 |
| Directory | /workspace/10.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.782647752 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3621921800 ps |
| CPU time | 11.59 seconds |
| Started | Feb 21 12:29:34 PM PST 24 |
| Finished | Feb 21 12:29:46 PM PST 24 |
| Peak memory | 204256 kb |
| Host | smart-52b2678f-cb21-403d-8661-d7dd5ed441d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782647752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.782647752 |
| Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3262484212 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 8365956652 ps |
| CPU time | 11.02 seconds |
| Started | Feb 21 12:29:13 PM PST 24 |
| Finished | Feb 21 12:29:24 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-9e3ef210-9890-42b9-9070-0ef663340f6b |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3262484212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.3262484212 |
| Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.2352025507 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5332068811 ps |
| CPU time | 8.5 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-11d10a13-cdec-44e5-8a28-ade0a82d411b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352025507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2352025507 |
| Directory | /workspace/10.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/11.rv_dm_alert_test.617904363 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 18703721 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:30:00 PM PST 24 |
| Finished | Feb 21 12:30:00 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-4934255d-85a9-4c42-adcd-acab93ee155a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617904363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.617904363 |
| Directory | /workspace/11.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2568081310 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2914604260 ps |
| CPU time | 9.54 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:28 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-23c92a0d-d35e-4b0a-85af-22065b5b912c |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2568081310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.2568081310 |
| Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.4281124737 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4198915686 ps |
| CPU time | 8.55 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:46 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-76f6ef22-c470-4cd8-95bc-ab795cad39c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281124737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.4281124737 |
| Directory | /workspace/11.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/12.rv_dm_alert_test.178065130 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 32870103 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:30:18 PM PST 24 |
| Finished | Feb 21 12:30:21 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-bdfccb54-7807-454c-9e63-fbc38a103d57 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178065130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.178065130 |
| Directory | /workspace/12.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1730516988 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1151449404 ps |
| CPU time | 6.58 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:42 PM PST 24 |
| Peak memory | 204224 kb |
| Host | smart-ae43d19c-c878-472e-b6af-d37bb991961c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730516988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1730516988 |
| Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3749341606 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 14126837092 ps |
| CPU time | 43.06 seconds |
| Started | Feb 21 12:29:32 PM PST 24 |
| Finished | Feb 21 12:30:16 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-b8b08767-c806-436d-9b55-075d3687ff0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3749341606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3749341606 |
| Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.2446642034 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 8421952456 ps |
| CPU time | 12.15 seconds |
| Started | Feb 21 12:29:41 PM PST 24 |
| Finished | Feb 21 12:29:54 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-66576c1b-5770-49bb-9a5b-7e2f99d33155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446642034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2446642034 |
| Directory | /workspace/12.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/13.rv_dm_alert_test.1577942325 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 39409600 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:15 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-0ae3afc6-5d37-4ce2-8ed1-325f9337d800 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577942325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1577942325 |
| Directory | /workspace/13.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3156239186 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 29403834262 ps |
| CPU time | 49.31 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:30:24 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-14d0e276-8ad5-45ea-ad95-e9b4f5d6267d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156239186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3156239186 |
| Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.202102839 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1767820589 ps |
| CPU time | 8.35 seconds |
| Started | Feb 21 12:29:30 PM PST 24 |
| Finished | Feb 21 12:29:39 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-21a98c8a-8e35-4843-b164-bacb9c03e46c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202102839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.202102839 |
| Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.367627262 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11773973162 ps |
| CPU time | 21.52 seconds |
| Started | Feb 21 12:30:18 PM PST 24 |
| Finished | Feb 21 12:30:42 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-9a439f85-548a-4425-b819-f9c1e4e4d824 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=367627262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t l_access.367627262 |
| Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.750559677 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1063753766 ps |
| CPU time | 3.61 seconds |
| Started | Feb 21 12:29:34 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 204300 kb |
| Host | smart-17fb4a9b-e847-4e77-bd1e-b0b1809caa62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750559677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.750559677 |
| Directory | /workspace/13.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/14.rv_dm_alert_test.513641284 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 52388042 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:34 PM PST 24 |
| Finished | Feb 21 12:29:35 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-0dd9b0dc-ddad-4e4a-b453-23fb431c4f9f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513641284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.513641284 |
| Directory | /workspace/14.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1210511796 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 586451121 ps |
| CPU time | 3.44 seconds |
| Started | Feb 21 12:29:27 PM PST 24 |
| Finished | Feb 21 12:29:33 PM PST 24 |
| Peak memory | 204608 kb |
| Host | smart-6db32718-d2bf-401e-9540-0e54dc085f2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210511796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1210511796 |
| Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2053789687 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1051452439 ps |
| CPU time | 1.61 seconds |
| Started | Feb 21 12:29:31 PM PST 24 |
| Finished | Feb 21 12:29:33 PM PST 24 |
| Peak memory | 204212 kb |
| Host | smart-d96b902d-daac-41e5-abf6-ec7dc42e4a56 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2053789687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.2053789687 |
| Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.1562015037 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1052321839 ps |
| CPU time | 1.99 seconds |
| Started | Feb 21 12:29:31 PM PST 24 |
| Finished | Feb 21 12:29:34 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-74ad77e1-4165-4433-9263-70fbd26dec6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562015037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1562015037 |
| Directory | /workspace/14.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/14.rv_dm_stress_all.2140464254 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1795022609 ps |
| CPU time | 6.22 seconds |
| Started | Feb 21 12:29:32 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 204072 kb |
| Host | smart-be0cd1a7-3d15-4306-a8a8-32592af2187c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140464254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2140464254 |
| Directory | /workspace/14.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/15.rv_dm_alert_test.3511021075 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 24902588 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:30:16 PM PST 24 |
| Finished | Feb 21 12:30:20 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-58a6de40-d926-41fb-bfad-e343f5cb858c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511021075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3511021075 |
| Directory | /workspace/15.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1686719900 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 24001286767 ps |
| CPU time | 78.97 seconds |
| Started | Feb 21 12:29:32 PM PST 24 |
| Finished | Feb 21 12:30:52 PM PST 24 |
| Peak memory | 204252 kb |
| Host | smart-3618fa1e-5a3a-4531-b0a1-011a2fae99b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686719900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1686719900 |
| Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3699585329 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 806291455 ps |
| CPU time | 1.92 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:20 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-53a925a7-0e39-4364-a6dd-5bf64129a7ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699585329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3699585329 |
| Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3088282088 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3395584208 ps |
| CPU time | 6.05 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:25 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-a2124535-0f12-4d72-b735-340b389a7b1c |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3088282088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.3088282088 |
| Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.3459991350 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2992175391 ps |
| CPU time | 6.01 seconds |
| Started | Feb 21 12:29:27 PM PST 24 |
| Finished | Feb 21 12:29:34 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-2b35d613-dbda-41b0-881b-ee4e99ac6e9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3459991350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3459991350 |
| Directory | /workspace/15.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/16.rv_dm_alert_test.2837007871 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 17164817 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:36 PM PST 24 |
| Peak memory | 203928 kb |
| Host | smart-4a71780e-9a5c-4f04-a79d-77f599a31556 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837007871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2837007871 |
| Directory | /workspace/16.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1403550179 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4245532500 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 12:29:38 PM PST 24 |
| Finished | Feb 21 12:29:45 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-fe0459ee-d502-4b7c-a826-7fc232ae0e84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403550179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1403550179 |
| Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1774374710 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 11433583279 ps |
| CPU time | 21.11 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:59 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-a24decd0-a340-4c44-9198-f37a3d7a1a1c |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1774374710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.1774374710 |
| Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1377822359 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 352669911 ps |
| CPU time | 1.96 seconds |
| Started | Feb 21 12:30:19 PM PST 24 |
| Finished | Feb 21 12:30:22 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-991c46cc-6fd6-48ef-b158-8fdc12b83974 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377822359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1377822359 |
| Directory | /workspace/16.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/17.rv_dm_alert_test.2994776576 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 56837492 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:29:30 PM PST 24 |
| Finished | Feb 21 12:29:31 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-05df3a15-31c6-4e34-8d34-74ea172ebcf0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994776576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2994776576 |
| Directory | /workspace/17.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3950330739 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9313017008 ps |
| CPU time | 44.76 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:30:21 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-bdf2271a-7af0-42ea-8694-ab45c146f15f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950330739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3950330739 |
| Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2147438058 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 826567781 ps |
| CPU time | 3.57 seconds |
| Started | Feb 21 12:29:43 PM PST 24 |
| Finished | Feb 21 12:29:47 PM PST 24 |
| Peak memory | 204232 kb |
| Host | smart-1cf36147-2cf3-48a8-a7df-045552ba9abf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147438058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2147438058 |
| Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2104832906 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 6039892920 ps |
| CPU time | 20.16 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:57 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-af01f01d-60a8-4b22-a9bc-0f7b52810174 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2104832906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.2104832906 |
| Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.3158541177 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3417338981 ps |
| CPU time | 13.49 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:49 PM PST 24 |
| Peak memory | 204328 kb |
| Host | smart-68aa49e8-7335-43cb-974a-82f4c10a7eaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158541177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3158541177 |
| Directory | /workspace/17.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/17.rv_dm_stress_all.4257707675 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3104824964 ps |
| CPU time | 9.74 seconds |
| Started | Feb 21 12:30:03 PM PST 24 |
| Finished | Feb 21 12:30:13 PM PST 24 |
| Peak memory | 204112 kb |
| Host | smart-8b7b3ac4-9351-4db9-ba24-cab232b265fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257707675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.4257707675 |
| Directory | /workspace/17.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/18.rv_dm_alert_test.1426687662 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 16700634 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:37 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-7649da3a-db0c-434a-97bf-8996b13977fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426687662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1426687662 |
| Directory | /workspace/18.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1043115947 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1388812507 ps |
| CPU time | 2.65 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 204200 kb |
| Host | smart-835eb530-8aa0-4e99-a478-00fee8186220 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1043115947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1043115947 |
| Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3321884147 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8871391169 ps |
| CPU time | 5.6 seconds |
| Started | Feb 21 12:29:41 PM PST 24 |
| Finished | Feb 21 12:29:47 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-896f38e6-0753-4ed4-a7d7-c8e5a0bc4b28 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3321884147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3321884147 |
| Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.2587823708 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 5140291016 ps |
| CPU time | 17.87 seconds |
| Started | Feb 21 12:30:05 PM PST 24 |
| Finished | Feb 21 12:30:23 PM PST 24 |
| Peak memory | 204312 kb |
| Host | smart-d5a96f0d-e257-4351-af40-916a091736ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587823708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2587823708 |
| Directory | /workspace/18.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/19.rv_dm_alert_test.4271372171 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 27483081 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-f060c527-70f4-437a-822d-a9515214c7e5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271372171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.4271372171 |
| Directory | /workspace/19.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.4063090680 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6541092000 ps |
| CPU time | 20.72 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:58 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-5529feba-e736-407e-b224-f69301bfd581 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063090680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.4063090680 |
| Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3530425223 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4251166216 ps |
| CPU time | 14.77 seconds |
| Started | Feb 21 12:29:53 PM PST 24 |
| Finished | Feb 21 12:30:08 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-9cc4ecfb-c602-452f-a57a-4146c565357d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530425223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3530425223 |
| Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1637110046 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 7631725262 ps |
| CPU time | 23.98 seconds |
| Started | Feb 21 12:29:46 PM PST 24 |
| Finished | Feb 21 12:30:10 PM PST 24 |
| Peak memory | 204356 kb |
| Host | smart-3c8b6018-81d1-4171-8b57-614004606420 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1637110046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.1637110046 |
| Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.631532826 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2835157813 ps |
| CPU time | 6.49 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:42 PM PST 24 |
| Peak memory | 204304 kb |
| Host | smart-85f47fd3-05e9-4827-af57-26568f921cec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631532826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.631532826 |
| Directory | /workspace/19.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/19.rv_dm_stress_all.3237529519 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2604738806 ps |
| CPU time | 6.63 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:41 PM PST 24 |
| Peak memory | 204116 kb |
| Host | smart-9e70f839-8cb2-4182-a9fc-83fdbcf7e4a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237529519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3237529519 |
| Directory | /workspace/19.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/2.rv_dm_alert_test.3304385919 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 17854880 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:29:09 PM PST 24 |
| Finished | Feb 21 12:29:10 PM PST 24 |
| Peak memory | 203836 kb |
| Host | smart-e0b3083d-3724-46ba-8786-326048455204 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304385919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3304385919 |
| Directory | /workspace/2.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3664337889 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1552715028 ps |
| CPU time | 4.2 seconds |
| Started | Feb 21 12:29:31 PM PST 24 |
| Finished | Feb 21 12:29:35 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-c45f6b37-05ca-49c2-87c6-e0fdea7632e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664337889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3664337889 |
| Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2590214741 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 11421640041 ps |
| CPU time | 13.76 seconds |
| Started | Feb 21 12:29:23 PM PST 24 |
| Finished | Feb 21 12:29:37 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-3d9cfdcf-6904-42ac-a689-a256bfbb4d19 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2590214741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.2590214741 |
| Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.3661251976 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 113951496 ps |
| CPU time | 0.92 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:30 PM PST 24 |
| Peak memory | 203784 kb |
| Host | smart-8d50b38b-fa10-412d-9117-043d737a3e1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661251976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3661251976 |
| Directory | /workspace/2.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.1898508509 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3563606647 ps |
| CPU time | 5.54 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:20 PM PST 24 |
| Peak memory | 204356 kb |
| Host | smart-471385c9-36ca-4991-8bc6-673595427ba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898508509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1898508509 |
| Directory | /workspace/2.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2608279044 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 259844399 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:31 PM PST 24 |
| Peak memory | 219088 kb |
| Host | smart-5c52471d-0e1a-424d-a02b-40855a09b644 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608279044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2608279044 |
| Directory | /workspace/2.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/20.rv_dm_alert_test.3022664321 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 36265585 ps |
| CPU time | 0.7 seconds |
| Started | Feb 21 12:30:25 PM PST 24 |
| Finished | Feb 21 12:30:26 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-b947e7f7-31c0-402e-ab8e-5e1aacf6a79c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022664321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3022664321 |
| Directory | /workspace/20.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/21.rv_dm_alert_test.2524920292 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 15072694 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:30:28 PM PST 24 |
| Finished | Feb 21 12:30:30 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-a62c1aac-d317-47f3-9642-6924c66b0763 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524920292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2524920292 |
| Directory | /workspace/21.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/22.rv_dm_alert_test.2089009448 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 52078196 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:29:39 PM PST 24 |
| Finished | Feb 21 12:29:40 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-9b3f56d9-2fe1-48ff-bdbb-9d9948735dac |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089009448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2089009448 |
| Directory | /workspace/22.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/23.rv_dm_alert_test.3442302139 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 18181890 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:30:05 PM PST 24 |
| Finished | Feb 21 12:30:06 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-7fbb87a3-f6c1-4645-b810-69c9b3419833 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442302139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3442302139 |
| Directory | /workspace/23.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/24.rv_dm_alert_test.3369876912 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 27700268 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:29:55 PM PST 24 |
| Finished | Feb 21 12:29:56 PM PST 24 |
| Peak memory | 203948 kb |
| Host | smart-adf44624-f9e7-4dcc-8e37-fefb2cf97aec |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369876912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3369876912 |
| Directory | /workspace/24.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/25.rv_dm_alert_test.3335238026 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 25275192 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:37 PM PST 24 |
| Peak memory | 203908 kb |
| Host | smart-bf84f17c-321c-4e82-a259-b8ce774829e3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335238026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3335238026 |
| Directory | /workspace/25.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/26.rv_dm_alert_test.2380518052 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 24964239 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:51 PM PST 24 |
| Finished | Feb 21 12:29:52 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-f99b025d-4352-423a-bcfb-5a0d76b53528 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380518052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2380518052 |
| Directory | /workspace/26.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/26.rv_dm_stress_all.157359817 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1108719308 ps |
| CPU time | 2.73 seconds |
| Started | Feb 21 12:30:15 PM PST 24 |
| Finished | Feb 21 12:30:20 PM PST 24 |
| Peak memory | 204104 kb |
| Host | smart-ac2469f6-3ad0-402b-bf89-c87b18211844 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157359817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.157359817 |
| Directory | /workspace/26.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/27.rv_dm_alert_test.3943377656 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 19680191 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:37 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-69cff83f-505a-4a12-b89a-d0894675d213 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943377656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3943377656 |
| Directory | /workspace/27.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/28.rv_dm_alert_test.1476133858 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 26861782 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:30:25 PM PST 24 |
| Finished | Feb 21 12:30:26 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-16af5f81-3217-493f-8dfc-39351ec5ac46 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476133858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1476133858 |
| Directory | /workspace/28.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/28.rv_dm_stress_all.856467769 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4610625528 ps |
| CPU time | 13.56 seconds |
| Started | Feb 21 12:30:03 PM PST 24 |
| Finished | Feb 21 12:30:17 PM PST 24 |
| Peak memory | 204136 kb |
| Host | smart-3a484448-fa67-4692-b123-94d4f085436a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856467769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.856467769 |
| Directory | /workspace/28.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_dm_alert_test.1193735394 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 47318628 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:30:52 PM PST 24 |
| Finished | Feb 21 12:30:55 PM PST 24 |
| Peak memory | 204004 kb |
| Host | smart-e54aa3ad-68c9-4106-9f08-c585cb98d2ff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193735394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1193735394 |
| Directory | /workspace/29.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/3.rv_dm_alert_test.3727278279 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 30157472 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:36 PM PST 24 |
| Peak memory | 203872 kb |
| Host | smart-28f90746-e3b8-45e4-b853-6218c8fb9392 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727278279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3727278279 |
| Directory | /workspace/3.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2430422184 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 10291094047 ps |
| CPU time | 29.83 seconds |
| Started | Feb 21 12:29:14 PM PST 24 |
| Finished | Feb 21 12:29:44 PM PST 24 |
| Peak memory | 204380 kb |
| Host | smart-e2ea9279-2b92-41a1-981a-4ff0dbf9a4c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430422184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2430422184 |
| Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2875143716 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3138952789 ps |
| CPU time | 4.28 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:29:41 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-ab37f438-5f2c-472f-a809-930f5eb3a87c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875143716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2875143716 |
| Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3821637581 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 10311057679 ps |
| CPU time | 9.94 seconds |
| Started | Feb 21 12:29:25 PM PST 24 |
| Finished | Feb 21 12:29:36 PM PST 24 |
| Peak memory | 204324 kb |
| Host | smart-15d8affc-0d78-42b8-96e7-408565b6a431 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3821637581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3821637581 |
| Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.2828262089 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 216115136 ps |
| CPU time | 1.21 seconds |
| Started | Feb 21 12:29:33 PM PST 24 |
| Finished | Feb 21 12:29:34 PM PST 24 |
| Peak memory | 203804 kb |
| Host | smart-b63ecb42-1926-4215-abca-9d7faacc3702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828262089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2828262089 |
| Directory | /workspace/3.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.3912766800 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2281004753 ps |
| CPU time | 7.64 seconds |
| Started | Feb 21 12:29:29 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 204356 kb |
| Host | smart-12e843b5-9f19-47e7-892f-537594aab56f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912766800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3912766800 |
| Directory | /workspace/3.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3550663539 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 83636081 ps |
| CPU time | 1.05 seconds |
| Started | Feb 21 12:29:28 PM PST 24 |
| Finished | Feb 21 12:29:30 PM PST 24 |
| Peak memory | 220084 kb |
| Host | smart-62de2e80-907b-485b-b070-002be856f324 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550663539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3550663539 |
| Directory | /workspace/3.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/30.rv_dm_alert_test.1955021242 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 16956288 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:30:20 PM PST 24 |
| Finished | Feb 21 12:30:22 PM PST 24 |
| Peak memory | 204036 kb |
| Host | smart-773dcd7a-0796-434d-9750-79911df89b7e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955021242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1955021242 |
| Directory | /workspace/30.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/31.rv_dm_alert_test.3047450793 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 26449150 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:29:42 PM PST 24 |
| Finished | Feb 21 12:29:43 PM PST 24 |
| Peak memory | 204016 kb |
| Host | smart-cfab9264-0336-43ea-a8eb-b3b332d8ace6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047450793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3047450793 |
| Directory | /workspace/31.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/32.rv_dm_alert_test.3612968095 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 20847862 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:29:40 PM PST 24 |
| Finished | Feb 21 12:29:41 PM PST 24 |
| Peak memory | 204016 kb |
| Host | smart-eaf6c0a3-8be2-446d-a396-db4cade8e12c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612968095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3612968095 |
| Directory | /workspace/32.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/33.rv_dm_alert_test.535284267 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 77276410 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:29:56 PM PST 24 |
| Finished | Feb 21 12:29:57 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-300fe156-543d-47ef-9dc8-0c430a26e482 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535284267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.535284267 |
| Directory | /workspace/33.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/34.rv_dm_alert_test.3871480386 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 22182570 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:39 PM PST 24 |
| Finished | Feb 21 12:29:40 PM PST 24 |
| Peak memory | 204040 kb |
| Host | smart-874e10b0-d23a-4013-b34a-db63d17a0efa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871480386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3871480386 |
| Directory | /workspace/34.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/35.rv_dm_alert_test.985798446 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 47203170 ps |
| CPU time | 0.6 seconds |
| Started | Feb 21 12:29:52 PM PST 24 |
| Finished | Feb 21 12:29:53 PM PST 24 |
| Peak memory | 203852 kb |
| Host | smart-13f25328-a5de-4eec-a789-3456b99c8b17 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985798446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.985798446 |
| Directory | /workspace/35.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/36.rv_dm_alert_test.3482942069 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 63350600 ps |
| CPU time | 0.64 seconds |
| Started | Feb 21 12:29:48 PM PST 24 |
| Finished | Feb 21 12:29:49 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-49aeba8a-6072-4809-8ea3-7b6357184932 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482942069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3482942069 |
| Directory | /workspace/36.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/37.rv_dm_alert_test.4213540170 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 22869045 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:29:50 PM PST 24 |
| Finished | Feb 21 12:29:51 PM PST 24 |
| Peak memory | 203904 kb |
| Host | smart-3a82fd7c-b6bc-4ecb-b9ea-887ea31993f1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213540170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4213540170 |
| Directory | /workspace/37.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/38.rv_dm_alert_test.1517452375 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 38705432 ps |
| CPU time | 0.66 seconds |
| Started | Feb 21 12:30:22 PM PST 24 |
| Finished | Feb 21 12:30:23 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-fa8804f9-c286-4997-bb4f-3ca07de9e6ad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517452375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1517452375 |
| Directory | /workspace/38.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/39.rv_dm_alert_test.2338045787 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 38070979 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:55 PM PST 24 |
| Finished | Feb 21 12:29:56 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-2bfb3085-83f1-494b-bced-6e70d8eabecc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338045787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2338045787 |
| Directory | /workspace/39.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/4.rv_dm_alert_test.6979445 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 15016016 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:29:07 PM PST 24 |
| Finished | Feb 21 12:29:08 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-e3bb1b4c-7efb-472d-96d3-8c28223e17c0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6979445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.6979445 |
| Directory | /workspace/4.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.935123460 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3388019884 ps |
| CPU time | 8.66 seconds |
| Started | Feb 21 12:29:16 PM PST 24 |
| Finished | Feb 21 12:29:25 PM PST 24 |
| Peak memory | 204276 kb |
| Host | smart-2a10c330-b999-456c-90a2-1716b6fef016 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935123460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.935123460 |
| Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1354550930 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2660273184 ps |
| CPU time | 5.24 seconds |
| Started | Feb 21 12:29:33 PM PST 24 |
| Finished | Feb 21 12:29:39 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-27d4854c-6a4f-4c3c-9f92-dcd0ac129c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354550930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1354550930 |
| Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3473618429 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2056634731 ps |
| CPU time | 4.71 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:40 PM PST 24 |
| Peak memory | 204220 kb |
| Host | smart-b52264cd-f9eb-405e-be11-310b8c5eb05e |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3473618429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3473618429 |
| Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1242979600 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 153721159 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:29:34 PM PST 24 |
| Finished | Feb 21 12:29:35 PM PST 24 |
| Peak memory | 203468 kb |
| Host | smart-29419048-f593-4be6-8632-5feee02d4e4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242979600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1242979600 |
| Directory | /workspace/4.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.756324534 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8210262700 ps |
| CPU time | 24.57 seconds |
| Started | Feb 21 12:29:36 PM PST 24 |
| Finished | Feb 21 12:30:01 PM PST 24 |
| Peak memory | 204228 kb |
| Host | smart-5daa4759-320c-4384-bde9-7c1cc9aab009 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756324534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.756324534 |
| Directory | /workspace/4.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/4.rv_dm_sec_cm.3281712619 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 320409796 ps |
| CPU time | 1.61 seconds |
| Started | Feb 21 12:29:12 PM PST 24 |
| Finished | Feb 21 12:29:13 PM PST 24 |
| Peak memory | 220304 kb |
| Host | smart-ae7b9f96-6e27-480c-8fe7-7764d652aa3a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281712619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3281712619 |
| Directory | /workspace/4.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/40.rv_dm_alert_test.2346511955 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 30024141 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:29:57 PM PST 24 |
| Finished | Feb 21 12:29:58 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-f3d5b5e1-fe46-46c9-b66a-5c92d9d76c85 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346511955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2346511955 |
| Directory | /workspace/40.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/41.rv_dm_alert_test.3907862276 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 50786714 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:59 PM PST 24 |
| Finished | Feb 21 12:30:00 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-9a95f98a-f45a-474f-bfdc-8405debc357b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907862276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3907862276 |
| Directory | /workspace/41.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/42.rv_dm_alert_test.1278569868 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 23008109 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:48 PM PST 24 |
| Finished | Feb 21 12:29:49 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-ea8bd581-e8ab-475f-bef9-bf81417f71d4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278569868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1278569868 |
| Directory | /workspace/42.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/43.rv_dm_alert_test.3160856950 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 32195027 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:30:02 PM PST 24 |
| Finished | Feb 21 12:30:03 PM PST 24 |
| Peak memory | 203912 kb |
| Host | smart-d42d14b7-7e4e-4807-a5c6-fe3b3850a0cd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160856950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3160856950 |
| Directory | /workspace/43.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/44.rv_dm_alert_test.902920432 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 75208794 ps |
| CPU time | 0.61 seconds |
| Started | Feb 21 12:29:45 PM PST 24 |
| Finished | Feb 21 12:29:46 PM PST 24 |
| Peak memory | 203856 kb |
| Host | smart-9c1d84bf-b0d8-4dfa-a533-50bad6bc9aaf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902920432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.902920432 |
| Directory | /workspace/44.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/45.rv_dm_alert_test.2439787050 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 65121689 ps |
| CPU time | 0.72 seconds |
| Started | Feb 21 12:30:02 PM PST 24 |
| Finished | Feb 21 12:30:03 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-d5d403be-93d5-4444-b06f-a6cb094fcbd9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439787050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2439787050 |
| Directory | /workspace/45.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/46.rv_dm_alert_test.3429600218 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 15014341 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:29:57 PM PST 24 |
| Finished | Feb 21 12:29:58 PM PST 24 |
| Peak memory | 203932 kb |
| Host | smart-27fe183f-a283-48e8-b4bc-203725228751 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429600218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3429600218 |
| Directory | /workspace/46.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/46.rv_dm_stress_all.3242453556 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1108738118 ps |
| CPU time | 4.82 seconds |
| Started | Feb 21 12:29:55 PM PST 24 |
| Finished | Feb 21 12:30:00 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-8c7cd842-4943-487f-8eb6-3c94213c211f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242453556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3242453556 |
| Directory | /workspace/46.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_dm_alert_test.3045635949 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 25203872 ps |
| CPU time | 0.68 seconds |
| Started | Feb 21 12:29:52 PM PST 24 |
| Finished | Feb 21 12:29:53 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-2c8c3e25-f9b3-4c62-b29d-ce983fc569d2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045635949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3045635949 |
| Directory | /workspace/48.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/49.rv_dm_alert_test.2853108457 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 21247408 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:57 PM PST 24 |
| Finished | Feb 21 12:29:58 PM PST 24 |
| Peak memory | 203936 kb |
| Host | smart-82b61595-d408-4dcc-8094-8cc0bf29611d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853108457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2853108457 |
| Directory | /workspace/49.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/49.rv_dm_stress_all.934918223 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4409828562 ps |
| CPU time | 14.81 seconds |
| Started | Feb 21 12:29:52 PM PST 24 |
| Finished | Feb 21 12:30:07 PM PST 24 |
| Peak memory | 204104 kb |
| Host | smart-94490c53-950a-478c-83be-a8d873c59c4c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934918223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.934918223 |
| Directory | /workspace/49.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/5.rv_dm_alert_test.1152926249 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 23277296 ps |
| CPU time | 0.69 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:20 PM PST 24 |
| Peak memory | 203712 kb |
| Host | smart-384b392e-fc1c-48e5-84d4-9304fbfa3290 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152926249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1152926249 |
| Directory | /workspace/5.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.895624421 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 36960087969 ps |
| CPU time | 19.51 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:57 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-48288f8f-605f-4d1f-be08-678a317266f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895624421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.895624421 |
| Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3589624560 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 835302049 ps |
| CPU time | 2.43 seconds |
| Started | Feb 21 12:29:42 PM PST 24 |
| Finished | Feb 21 12:29:45 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-d755650d-de13-49b7-b86c-da566ab432de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589624560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3589624560 |
| Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2908436646 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8470374624 ps |
| CPU time | 26.08 seconds |
| Started | Feb 21 12:29:30 PM PST 24 |
| Finished | Feb 21 12:29:56 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-15411dea-c0ab-48b5-8f56-31ebba2b1213 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2908436646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.2908436646 |
| Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.4074992456 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3666889926 ps |
| CPU time | 7.96 seconds |
| Started | Feb 21 12:29:27 PM PST 24 |
| Finished | Feb 21 12:29:35 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-f19c8102-e40d-4345-8593-c1888d7653d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074992456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4074992456 |
| Directory | /workspace/5.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/6.rv_dm_alert_test.3913040972 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 49133797 ps |
| CPU time | 0.63 seconds |
| Started | Feb 21 12:29:32 PM PST 24 |
| Finished | Feb 21 12:29:33 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-93a76f1d-3aca-4de9-9f87-b5286f42cdaa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913040972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3913040972 |
| Directory | /workspace/6.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2509948559 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 582819865 ps |
| CPU time | 3.2 seconds |
| Started | Feb 21 12:29:34 PM PST 24 |
| Finished | Feb 21 12:29:38 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-17b56edd-73f0-4fc5-9c9e-5631028815dc |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2509948559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.2509948559 |
| Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.1693028993 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2865586321 ps |
| CPU time | 10.79 seconds |
| Started | Feb 21 12:29:51 PM PST 24 |
| Finished | Feb 21 12:30:02 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-1a11fc6e-9c0c-4857-affa-cf13a82ca9e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693028993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1693028993 |
| Directory | /workspace/6.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/7.rv_dm_alert_test.2211331208 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 37875006 ps |
| CPU time | 0.65 seconds |
| Started | Feb 21 12:29:33 PM PST 24 |
| Finished | Feb 21 12:29:34 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-54d8e25e-79c9-4fd4-aefb-fd3164c85b23 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211331208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2211331208 |
| Directory | /workspace/7.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.4008040353 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 8330203083 ps |
| CPU time | 28.32 seconds |
| Started | Feb 21 12:29:12 PM PST 24 |
| Finished | Feb 21 12:29:41 PM PST 24 |
| Peak memory | 204232 kb |
| Host | smart-24cf4fd4-8c83-4329-86c4-8a0a2e3a28f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008040353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.4008040353 |
| Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1075459899 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2396306390 ps |
| CPU time | 8.09 seconds |
| Started | Feb 21 12:29:28 PM PST 24 |
| Finished | Feb 21 12:29:36 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-21988268-7dbc-4569-b648-e77f2211930c |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1075459899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.1075459899 |
| Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3453679693 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2923435143 ps |
| CPU time | 6.96 seconds |
| Started | Feb 21 12:29:34 PM PST 24 |
| Finished | Feb 21 12:29:42 PM PST 24 |
| Peak memory | 204376 kb |
| Host | smart-4751af92-8dd2-4103-aa1f-ae3be5f7fa9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453679693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3453679693 |
| Directory | /workspace/7.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/8.rv_dm_alert_test.2746516681 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 238120356 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:39 PM PST 24 |
| Peak memory | 203916 kb |
| Host | smart-919d39d0-b343-466c-81e1-3429158ca54a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746516681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2746516681 |
| Directory | /workspace/8.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1150147694 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 5755951349 ps |
| CPU time | 12.95 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:32 PM PST 24 |
| Peak memory | 204060 kb |
| Host | smart-814ad1e0-19a2-4d80-b050-550581f6d147 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150147694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1150147694 |
| Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.66634727 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13070938469 ps |
| CPU time | 39.82 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:30:18 PM PST 24 |
| Peak memory | 204260 kb |
| Host | smart-1ab17665-934a-44ac-8b9c-e3f31bb8f1bb |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=66634727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_ access.66634727 |
| Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.2644720250 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1371782867 ps |
| CPU time | 7.47 seconds |
| Started | Feb 21 12:29:26 PM PST 24 |
| Finished | Feb 21 12:29:34 PM PST 24 |
| Peak memory | 204632 kb |
| Host | smart-ea3444ee-2685-4898-9319-cf784d91fdda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644720250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2644720250 |
| Directory | /workspace/8.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/9.rv_dm_alert_test.2932677317 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 68075353 ps |
| CPU time | 0.67 seconds |
| Started | Feb 21 12:29:35 PM PST 24 |
| Finished | Feb 21 12:29:36 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-3276dfee-1586-4665-9d7f-6a65c2cf9856 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932677317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2932677317 |
| Directory | /workspace/9.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1915169278 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 9704286729 ps |
| CPU time | 35.15 seconds |
| Started | Feb 21 12:29:12 PM PST 24 |
| Finished | Feb 21 12:29:47 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-8f35ae59-db86-4482-9cdd-f92415ed59ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915169278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1915169278 |
| Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1864636713 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2832016250 ps |
| CPU time | 4.15 seconds |
| Started | Feb 21 12:29:18 PM PST 24 |
| Finished | Feb 21 12:29:23 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-bdc06569-0e6a-4f9c-9585-f7062f0d6ef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864636713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1864636713 |
| Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2444050678 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1349874538 ps |
| CPU time | 4.8 seconds |
| Started | Feb 21 12:29:42 PM PST 24 |
| Finished | Feb 21 12:29:47 PM PST 24 |
| Peak memory | 204316 kb |
| Host | smart-a7a73367-9690-4149-8bac-5eec5b4127c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2444050678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.2444050678 |
| Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.3959814116 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 6435715539 ps |
| CPU time | 8.04 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:29:46 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-2ee3e130-4c65-4945-9814-7fedf718cf43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959814116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3959814116 |
| Directory | /workspace/9.rv_dm_sba_tl_access/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |