Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.46	91.34	79.75	91.95	77.46	81.96	96.32

Total modules in report: 51

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
rv_dm_regs_csr_assert_fpv	0.00						0.00
tlul_err_resp	57.80	76.92	40.91			55.56
dm_csrs	68.17	85.35	61.33			57.83
dm_mem	77.02	80.00	58.06		100.00	70.00
tlul_lc_gate	78.58	96.08	77.78		85.71	83.33	50.00
prim_sync_reqack	79.17	100.00	66.67			100.00	50.00
rv_dm_regs_reg_top	82.14	75.00	82.14			71.43	100.00
prim_alert_sender	83.33			83.33
dmi_jtag	84.72	95.45	92.45		66.67	84.31
debug_rom	87.50	100.00				75.00
rv_dm	88.73	100.00	75.86	91.55			87.50
prim_secded_inv_64_57_dec	89.23			89.23
prim_fifo_sync	89.81	100.00	69.23			90.00	100.00
tlul_rsp_intg_gen	91.67	83.33					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
dmi_jtag_tap	92.41	100.00	100.00		71.05	98.57
prim_fifo_async_simple	95.83	100.00	87.50			100.00
tlul_adapter_reg	96.29	98.96	88.57			97.62	100.00
tlul_adapter_reg	100.00						100.00
tlul_adapter_reg ( parameter CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,RegAw=2,RegDw=32,AccessLatency=0,RegBw=4,IW=8,SZW=2 )	98.55	100.00	95.65			100.00
tlul_adapter_reg ( parameter CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=1,RegAw=12,RegDw=32,AccessLatency=1,RegBw=4,IW=8,SZW=2 )	91.55	97.92	81.48			95.24
dm_sba	98.53	100.00	100.00		100.00	94.12
tlul_assert	99.13	100.00				100.00	97.39
prim_fifo_sync_cnt	100.00	100.00				100.00
prim_generic_clock_mux2	100.00	100.00	100.00				100.00
prim_lc_sync	100.00	100.00					100.00
prim_lc_sync	100.00						100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
tlul_data_integ_dec	100.00	100.00
tlul_rsp_intg_chk	100.00	100.00	100.00				100.00
prim_sparse_fsm_flop	100.00	100.00					100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
tlul_cmd_intg_gen	100.00	100.00					100.00
prim_generic_and2	100.00	100.00
prim_onehot_check	100.00			100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
dm_top	100.00	100.00
tlul_adapter_host	100.00	100.00	100.00			100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
dmi_cdc	100.00	100.00	100.00			100.00
prim_generic_flop	100.00	100.00				100.00
tlul_data_integ_enc
prim_reg_we_check
prim_clock_mux2
prim_blanker
prim_buf
prim_generic_clock_inv
prim_clock_inv
prim_flop
prim_flop_2sync
tb
prim_and2
prim_sec_anchor_buf