Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	249152	1		T3	35		T6	18		T4	13
full_word	553136	1		T3	17		T6	2		T4	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	801988	1		T3	52		T6	20		T4	18
auto[TlIntgErrCmd]	94	1		T40	5		T41	8		T42	2
auto[TlIntgErrData]	101	1		T40	5		T41	8		T42	6
auto[TlIntgErrBoth]	105	1		T40	10		T41	4		T42	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	483224	1		T5	6		T7	33		T22	2
auto[1]	319064	1		T3	52		T6	20		T4	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	198721	1		T5	4		T7	13		T22	2
auto[TlIntgErrNone]	partial	auto[1]	50155	1		T3	35		T6	18		T4	13
auto[TlIntgErrNone]	full_word	auto[0]	284365	1		T5	2		T7	20		T19	12
auto[TlIntgErrNone]	full_word	auto[1]	268747	1		T3	17		T6	2		T4	5
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T40	2		T41	3		T71	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T40	3		T41	5		T42	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T130	1		T127	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T131	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1		T40	1		T41	3		T42	3
auto[TlIntgErrData]	partial	auto[1]	40	1		T40	4		T41	4		T42	3
auto[TlIntgErrData]	full_word	auto[0]	1	1		T123	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1		T41	1		T71	1		T94	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T40	4		T41	1		T42	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T40	5		T41	3		T42	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T40	1		T123	1		T129	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T71	1		T123	1		T126	2