Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	206555	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	551496	1		T3	17		T6	2		T4	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	481366	1		T5	6		T7	33		T22	2
values[0x0]	135486	1		T3	25		T6	6		T4	7
values[0x1]	141199	1		T3	27		T6	14		T4	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156739	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	601312	1		T3	18		T6	5		T4	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2514	1		T12	1		T43	3		T46	19
valid_sources[0x01]	2575	1		T5	1		T12	1		T43	1
valid_sources[0x02]	2710	1		T14	1		T12	1		T46	26
valid_sources[0x03]	2995	1		T84	1		T34	1		T43	1
valid_sources[0x04]	3023	1		T12	1		T43	3		T46	34
valid_sources[0x05]	3096	1		T43	5		T46	26		T47	28
valid_sources[0x06]	3340	1		T43	2		T46	29		T47	28
valid_sources[0x07]	3321	1		T46	24		T44	4		T47	24
valid_sources[0x08]	2886	1		T14	1		T83	4		T60	1
valid_sources[0x09]	3140	1		T43	14		T46	31		T47	19
valid_sources[0x0a]	2851	1		T60	1		T43	4		T46	24
valid_sources[0x0b]	2889	1		T43	8		T46	31		T47	14
valid_sources[0x0c]	2856	1		T43	4		T46	32		T47	41
valid_sources[0x0d]	2662	1		T3	1		T46	17		T47	20
valid_sources[0x0e]	3758	1		T60	1		T46	38		T47	29
valid_sources[0x0f]	3124	1		T84	1		T43	5		T46	33
valid_sources[0x10]	2790	1		T3	1		T12	2		T43	1
valid_sources[0x11]	2822	1		T3	1		T4	2		T30	1
valid_sources[0x12]	2982	1		T43	1		T46	13		T47	18
valid_sources[0x13]	3144	1		T7	4		T43	7		T46	22
valid_sources[0x14]	2736	1		T12	1		T46	16		T47	21
valid_sources[0x15]	2638	1		T11	1		T12	2		T43	3
valid_sources[0x16]	3429	1		T83	4		T12	1		T60	1
valid_sources[0x17]	2878	1		T34	1		T43	1		T46	21
valid_sources[0x18]	3028	1		T43	3		T46	21		T44	3
valid_sources[0x19]	3130	1		T6	9		T7	2		T43	2
valid_sources[0x1a]	2942	1		T43	5		T46	18		T47	23
valid_sources[0x1b]	3709	1		T46	23		T47	39		T56	243
valid_sources[0x1c]	3057	1		T12	1		T43	3		T46	17
valid_sources[0x1d]	2638	1		T5	1		T11	1		T27	2
valid_sources[0x1e]	3209	1		T22	28		T19	101		T132	1
valid_sources[0x1f]	2491	1		T46	16		T47	42		T56	182
valid_sources[0x20]	2287	1		T43	7		T46	23		T47	21
valid_sources[0x21]	2945	1		T43	3		T46	27		T47	29
valid_sources[0x22]	2703	1		T122	1		T43	20		T46	25
valid_sources[0x23]	2631	1		T12	1		T133	2		T43	4
valid_sources[0x24]	3027	1		T7	8		T84	1		T46	27
valid_sources[0x25]	3050	1		T11	1		T43	4		T46	28
valid_sources[0x26]	2419	1		T4	2		T43	3		T46	15
valid_sources[0x27]	2987	1		T11	3		T122	1		T46	13
valid_sources[0x28]	2399	1		T3	1		T11	1		T43	1
valid_sources[0x29]	2818	1		T43	4		T46	27		T47	25
valid_sources[0x2a]	3155	1		T46	16		T47	34		T56	195
valid_sources[0x2b]	3035	1		T46	24		T47	26		T56	194
valid_sources[0x2c]	3898	1		T4	1		T11	1		T43	1
valid_sources[0x2d]	3556	1		T134	1		T43	3		T46	24
valid_sources[0x2e]	3052	1		T3	1		T60	1		T46	21
valid_sources[0x2f]	3280	1		T43	1		T46	28		T47	20
valid_sources[0x30]	3189	1		T43	11		T46	21		T47	40
valid_sources[0x31]	3389	1		T3	1		T43	1		T46	26
valid_sources[0x32]	2816	1		T3	1		T12	1		T46	28
valid_sources[0x33]	2686	1		T73	1		T12	1		T43	5
valid_sources[0x34]	2839	1		T43	4		T46	24		T47	29
valid_sources[0x35]	2625	1		T3	1		T7	1		T43	9
valid_sources[0x36]	3052	1		T3	1		T43	5		T46	17
valid_sources[0x37]	2998	1		T3	1		T83	1		T84	1
valid_sources[0x38]	3919	1		T3	1		T12	1		T43	9
valid_sources[0x39]	2958	1		T60	1		T43	1		T46	30
valid_sources[0x3a]	2699	1		T3	1		T83	1		T12	1
valid_sources[0x3b]	2478	1		T46	24		T47	25		T56	215
valid_sources[0x3c]	2639	1		T11	1		T12	1		T43	5
valid_sources[0x3d]	3078	1		T84	1		T43	10		T46	24
valid_sources[0x3e]	3358	1		T84	1		T60	1		T43	8
valid_sources[0x3f]	3736	1		T73	1		T12	1		T60	1
valid_sources[0x40]	2403	1		T34	1		T43	1		T46	28
valid_sources[0x41]	2811	1		T84	1		T43	2		T46	20
valid_sources[0x42]	3338	1		T43	2		T46	16		T47	13
valid_sources[0x43]	2931	1		T43	2		T46	24		T47	18
valid_sources[0x44]	2446	1		T3	1		T5	1		T14	1
valid_sources[0x45]	3255	1		T12	1		T85	72		T46	26
valid_sources[0x46]	2539	1		T84	2		T12	1		T43	7
valid_sources[0x47]	3314	1		T46	39		T47	6		T56	219
valid_sources[0x48]	3202	1		T83	4		T43	2		T46	21
valid_sources[0x49]	3560	1		T11	4		T43	2		T46	17
valid_sources[0x4a]	3680	1		T60	1		T43	2		T46	35
valid_sources[0x4b]	2896	1		T43	2		T46	24		T47	15
valid_sources[0x4c]	2544	1		T43	3		T46	21		T47	33
valid_sources[0x4d]	2894	1		T4	2		T11	1		T43	4
valid_sources[0x4e]	3308	1		T84	1		T12	2		T43	10
valid_sources[0x4f]	2800	1		T4	1		T46	17		T44	5
valid_sources[0x50]	2833	1		T43	1		T46	31		T47	13
valid_sources[0x51]	2885	1		T4	2		T12	1		T43	6
valid_sources[0x52]	2649	1		T7	3		T11	1		T43	1
valid_sources[0x53]	3211	1		T3	1		T43	5		T46	20
valid_sources[0x54]	2923	1		T43	5		T46	29		T47	20
valid_sources[0x55]	3375	1		T7	3		T84	1		T43	4
valid_sources[0x56]	2687	1		T5	1		T43	8		T46	16
valid_sources[0x57]	3743	1		T12	1		T43	4		T46	18
valid_sources[0x58]	3187	1		T43	7		T46	5		T47	38
valid_sources[0x59]	2805	1		T43	5		T46	25		T47	30
valid_sources[0x5a]	2743	1		T6	1		T11	3		T30	3
valid_sources[0x5b]	2820	1		T12	1		T60	2		T43	3
valid_sources[0x5c]	2742	1		T43	6		T46	21		T47	33
valid_sources[0x5d]	3881	1		T3	1		T11	1		T46	22
valid_sources[0x5e]	2924	1		T43	7		T46	32		T47	26
valid_sources[0x5f]	2597	1		T12	2		T30	9		T43	4
valid_sources[0x60]	2416	1		T3	1		T43	17		T46	15
valid_sources[0x61]	2757	1		T3	2		T14	1		T12	1
valid_sources[0x62]	2481	1		T3	1		T43	2		T46	22
valid_sources[0x63]	3143	1		T5	2		T46	17		T44	17
valid_sources[0x64]	2803	1		T46	32		T47	12		T56	189
valid_sources[0x65]	2930	1		T34	1		T43	5		T46	33
valid_sources[0x66]	2699	1		T46	24		T47	23		T56	180
valid_sources[0x67]	2958	1		T43	2		T46	24		T47	21
valid_sources[0x68]	2808	1		T43	3		T46	24		T47	33
valid_sources[0x69]	2353	1		T12	2		T43	7		T46	17
valid_sources[0x6a]	2941	1		T43	7		T46	21		T47	24
valid_sources[0x6b]	3045	1		T83	5		T30	2		T46	22
valid_sources[0x6c]	2962	1		T30	2		T43	4		T46	31
valid_sources[0x6d]	2894	1		T3	1		T83	4		T12	1
valid_sources[0x6e]	2769	1		T46	19		T44	19		T47	13
valid_sources[0x6f]	3002	1		T12	1		T43	2		T46	28
valid_sources[0x70]	3255	1		T27	6		T43	9		T46	26
valid_sources[0x71]	3320	1		T12	1		T43	2		T46	32
valid_sources[0x72]	2763	1		T12	1		T43	7		T46	20
valid_sources[0x73]	2700	1		T86	5		T43	2		T46	14
valid_sources[0x74]	3135	1		T12	1		T43	3		T46	32
valid_sources[0x75]	3577	1		T27	3		T46	29		T47	30
valid_sources[0x76]	2623	1		T7	6		T43	1		T46	18
valid_sources[0x77]	2982	1		T3	1		T46	20		T47	29
valid_sources[0x78]	3264	1		T12	1		T43	1		T46	29
valid_sources[0x79]	2736	1		T3	1		T15	4		T43	3
valid_sources[0x7a]	2689	1		T43	2		T46	24		T47	18
valid_sources[0x7b]	3443	1		T14	1		T27	9		T43	8
valid_sources[0x7c]	3844	1		T3	1		T122	1		T132	1
valid_sources[0x7d]	3593	1		T3	1		T11	5		T84	1
valid_sources[0x7e]	2971	1		T3	1		T43	1		T46	24
valid_sources[0x7f]	2651	1		T43	4		T46	18		T47	29
valid_sources[0x80]	2987	1		T46	25		T47	18		T56	205

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

284151

1

T5

2

T7

20

T19

12

values[0x0]

all_enables

biggest_size

133550

1

T3

10

T6

1

T4

5

values[0x1]

all_enables

biggest_size

133795

1

T3

7

T6

1

T5

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2283	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21815	1		T35	6		T37	4		T49	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7229	1		T43	40		T46	9		T44	163
values[0x0]	8407	1		T35	10		T37	8		T49	5
values[0x1]	8462	1		T2	2		T35	6		T32	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1734	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22364	1		T2	1		T35	6		T37	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	72	1		T135	1		T43	1		T44	4
valid_sources[0x01]	91	1		T136	1		T44	3		T56	22
valid_sources[0x02]	82	1		T137	1		T138	1		T139	2
valid_sources[0x03]	159	1		T44	1		T75	3		T78	12
valid_sources[0x04]	79	1		T138	1		T56	12		T75	4
valid_sources[0x05]	70	1		T121	1		T138	1		T44	1
valid_sources[0x06]	69	1		T52	1		T136	1		T43	2
valid_sources[0x07]	199	1		T47	1		T74	1		T75	1
valid_sources[0x08]	90	1		T136	1		T44	2		T75	3
valid_sources[0x09]	93	1		T53	2		T140	1		T44	2
valid_sources[0x0a]	119	1		T121	1		T137	1		T141	1
valid_sources[0x0b]	102	1		T35	1		T121	1		T44	3
valid_sources[0x0c]	75	1		T121	1		T46	1		T44	1
valid_sources[0x0d]	101	1		T142	7		T44	7		T75	4
valid_sources[0x0e]	129	1		T56	5		T40	1		T75	8
valid_sources[0x0f]	107	1		T44	2		T41	1		T76	49
valid_sources[0x10]	81	1		T75	4		T78	7		T123	2
valid_sources[0x11]	72	1		T44	4		T56	2		T75	3
valid_sources[0x12]	114	1		T138	1		T44	3		T74	1
valid_sources[0x13]	59	1		T44	3		T56	2		T75	6
valid_sources[0x14]	232	1		T44	5		T75	1		T78	3
valid_sources[0x15]	66	1		T143	4		T44	2		T74	1
valid_sources[0x16]	112	1		T120	5		T144	10		T44	4
valid_sources[0x17]	76	1		T41	1		T75	3		T77	2
valid_sources[0x18]	79	1		T44	5		T74	2		T75	4
valid_sources[0x19]	118	1		T136	1		T44	6		T74	1
valid_sources[0x1a]	88	1		T145	1		T43	1		T44	1
valid_sources[0x1b]	93	1		T49	1		T136	1		T58	1
valid_sources[0x1c]	204	1		T44	4		T75	4		T146	2
valid_sources[0x1d]	62	1		T37	1		T52	1		T44	2
valid_sources[0x1e]	80	1		T46	1		T47	1		T40	2
valid_sources[0x1f]	62	1		T52	3		T136	1		T137	1
valid_sources[0x20]	180	1		T135	1		T43	1		T44	7
valid_sources[0x21]	116	1		T53	1		T44	2		T75	6
valid_sources[0x22]	95	1		T44	8		T75	3		T80	6
valid_sources[0x23]	88	1		T44	1		T75	8		T146	1
valid_sources[0x24]	66	1		T44	1		T56	2		T75	2
valid_sources[0x25]	79	1		T147	3		T43	1		T75	4
valid_sources[0x26]	102	1		T44	1		T41	1		T74	1
valid_sources[0x27]	54	1		T47	1		T74	1		T75	5
valid_sources[0x28]	88	1		T46	1		T44	4		T56	1
valid_sources[0x29]	80	1		T44	2		T40	1		T41	1
valid_sources[0x2a]	114	1		T40	3		T74	1		T76	41
valid_sources[0x2b]	85	1		T44	4		T41	2		T75	3
valid_sources[0x2c]	86	1		T44	1		T47	1		T75	5
valid_sources[0x2d]	57	1		T148	3		T44	2		T40	3
valid_sources[0x2e]	87	1		T52	2		T121	1		T149	1
valid_sources[0x2f]	87	1		T44	7		T40	1		T74	1
valid_sources[0x30]	94	1		T43	1		T44	3		T56	20
valid_sources[0x31]	85	1		T44	4		T75	1		T78	4
valid_sources[0x32]	66	1		T37	1		T150	1		T44	3
valid_sources[0x33]	103	1		T137	1		T44	3		T74	1
valid_sources[0x34]	85	1		T43	9		T44	1		T80	10
valid_sources[0x35]	66	1		T43	1		T44	2		T41	1
valid_sources[0x36]	66	1		T151	1		T145	1		T44	5
valid_sources[0x37]	79	1		T147	3		T152	1		T44	1
valid_sources[0x38]	74	1		T143	1		T137	1		T46	1
valid_sources[0x39]	71	1		T151	1		T46	1		T44	2
valid_sources[0x3a]	97	1		T35	1		T145	1		T44	4
valid_sources[0x3b]	73	1		T44	1		T41	1		T74	1
valid_sources[0x3c]	214	1		T54	1		T44	1		T47	1
valid_sources[0x3d]	71	1		T153	8		T44	1		T75	3
valid_sources[0x3e]	85	1		T140	3		T46	1		T44	1
valid_sources[0x3f]	77	1		T120	1		T44	1		T75	3
valid_sources[0x40]	71	1		T43	1		T44	5		T75	3
valid_sources[0x41]	53	1		T154	1		T47	1		T41	1
valid_sources[0x42]	76	1		T44	1		T75	6		T77	14
valid_sources[0x43]	71	1		T44	3		T56	10		T41	1
valid_sources[0x44]	132	1		T121	1		T43	1		T44	2
valid_sources[0x45]	115	1		T35	1		T53	1		T44	1
valid_sources[0x46]	70	1		T44	1		T56	5		T58	2
valid_sources[0x47]	103	1		T40	2		T75	4		T78	3
valid_sources[0x48]	242	1		T139	3		T43	1		T44	4
valid_sources[0x49]	80	1		T155	2		T44	1		T59	1
valid_sources[0x4a]	150	1		T43	3		T44	2		T40	1
valid_sources[0x4b]	132	1		T52	5		T121	1		T151	1
valid_sources[0x4c]	72	1		T46	1		T75	3		T78	2
valid_sources[0x4d]	121	1		T54	1		T44	4		T74	1
valid_sources[0x4e]	75	1		T42	1		T75	5		T78	1
valid_sources[0x4f]	91	1		T156	10		T43	6		T44	3
valid_sources[0x50]	130	1		T137	1		T44	10		T56	11
valid_sources[0x51]	100	1		T157	3		T44	5		T75	1
valid_sources[0x52]	82	1		T44	1		T75	2		T78	3
valid_sources[0x53]	67	1		T52	1		T140	1		T44	5
valid_sources[0x54]	69	1		T145	2		T44	2		T74	3
valid_sources[0x55]	79	1		T43	1		T44	1		T75	3
valid_sources[0x56]	75	1		T151	1		T43	2		T44	6
valid_sources[0x57]	79	1		T46	2		T44	3		T75	7
valid_sources[0x58]	112	1		T54	1		T44	5		T75	4
valid_sources[0x59]	177	1		T44	3		T42	1		T75	6
valid_sources[0x5a]	112	1		T136	1		T158	1		T138	1
valid_sources[0x5b]	70	1		T44	3		T75	1		T80	3
valid_sources[0x5c]	149	1		T136	1		T44	2		T41	1
valid_sources[0x5d]	114	1		T44	4		T42	1		T75	4
valid_sources[0x5e]	61	1		T135	1		T155	7		T44	1
valid_sources[0x5f]	104	1		T152	1		T44	3		T40	1
valid_sources[0x60]	104	1		T81	6		T143	1		T151	1
valid_sources[0x61]	98	1		T44	1		T57	9		T75	4
valid_sources[0x62]	96	1		T44	2		T41	1		T87	4
valid_sources[0x63]	79	1		T44	9		T56	3		T75	1
valid_sources[0x64]	95	1		T35	1		T52	3		T142	2
valid_sources[0x65]	115	1		T121	3		T143	2		T44	3
valid_sources[0x66]	70	1		T136	1		T44	4		T74	2
valid_sources[0x67]	76	1		T121	1		T145	1		T44	2
valid_sources[0x68]	103	1		T52	1		T159	11		T56	2
valid_sources[0x69]	56	1		T140	1		T44	3		T47	2
valid_sources[0x6a]	75	1		T158	1		T44	4		T75	1
valid_sources[0x6b]	141	1		T135	1		T44	4		T41	1
valid_sources[0x6c]	92	1		T51	6		T53	1		T54	1
valid_sources[0x6d]	117	1		T138	1		T44	7		T41	1
valid_sources[0x6e]	119	1		T44	5		T75	3		T78	2
valid_sources[0x6f]	104	1		T43	2		T75	4		T160	5
valid_sources[0x70]	99	1		T51	3		T47	1		T56	4
valid_sources[0x71]	146	1		T50	1		T137	1		T43	1
valid_sources[0x72]	108	1		T46	1		T44	10		T74	2
valid_sources[0x73]	85	1		T161	3		T43	4		T44	3
valid_sources[0x74]	107	1		T54	1		T121	2		T151	1
valid_sources[0x75]	74	1		T152	2		T44	2		T75	1
valid_sources[0x76]	73	1		T52	2		T121	2		T158	1
valid_sources[0x77]	267	1		T44	1		T47	1		T74	1
valid_sources[0x78]	76	1		T43	3		T41	1		T75	2
valid_sources[0x79]	70	1		T37	4		T136	1		T44	5
valid_sources[0x7a]	74	1		T53	3		T82	1		T143	3
valid_sources[0x7b]	143	1		T50	1		T143	1		T44	3
valid_sources[0x7c]	69	1		T137	1		T151	1		T44	1
valid_sources[0x7d]	81	1		T43	4		T44	4		T47	1
valid_sources[0x7e]	75	1		T143	1		T56	3		T41	2
valid_sources[0x7f]	103	1		T44	6		T41	1		T45	20
valid_sources[0x80]	97	1		T161	2		T43	1		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6081

1

T43

40

T46

9

T44

163

values[0x0]

all_enables

biggest_size

7946

1

T35

5

T37

4

T49

3

values[0x1]

all_enables

biggest_size

7788

1

T35

1

T51

1

T52

2