SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 636 | 636 | 0 | 0 |
OutputsKnown_A | 78350260 | 78187484 | 0 | 0 |
gen_flops.OutputDelay_A | 39175130 | 39090088 | 0 | 954 |
gen_no_flops.OutputDelay_A | 39175130 | 39093742 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 636 | 636 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T10 | 4 | 4 | 0 | 0 |
T13 | 4 | 4 | 0 | 0 |
T16 | 4 | 4 | 0 | 0 |
T32 | 4 | 4 | 0 | 0 |
T35 | 4 | 4 | 0 | 0 |
T36 | 4 | 4 | 0 | 0 |
T37 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 78350260 | 78187484 | 0 | 0 |
T1 | 473068 | 472716 | 0 | 0 |
T2 | 5092 | 4728 | 0 | 0 |
T3 | 461128 | 460100 | 0 | 0 |
T10 | 968392 | 968072 | 0 | 0 |
T13 | 671680 | 671464 | 0 | 0 |
T16 | 1540876 | 1536092 | 0 | 0 |
T32 | 4956 | 4620 | 0 | 0 |
T35 | 8608 | 8348 | 0 | 0 |
T36 | 236136 | 235800 | 0 | 0 |
T37 | 12716 | 12372 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 39175130 | 39090088 | 0 | 954 |
T1 | 236534 | 236352 | 0 | 6 |
T2 | 2546 | 2358 | 0 | 6 |
T3 | 230564 | 230026 | 0 | 6 |
T10 | 484196 | 484030 | 0 | 6 |
T13 | 335840 | 335726 | 0 | 6 |
T16 | 770438 | 767938 | 0 | 6 |
T32 | 2478 | 2304 | 0 | 6 |
T35 | 4304 | 4168 | 0 | 6 |
T36 | 118068 | 117894 | 0 | 6 |
T37 | 6358 | 6180 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 39175130 | 39093742 | 0 | 0 |
T1 | 236534 | 236358 | 0 | 0 |
T2 | 2546 | 2364 | 0 | 0 |
T3 | 230564 | 230050 | 0 | 0 |
T10 | 484196 | 484036 | 0 | 0 |
T13 | 335840 | 335732 | 0 | 0 |
T16 | 770438 | 768046 | 0 | 0 |
T32 | 2478 | 2310 | 0 | 0 |
T35 | 4304 | 4174 | 0 | 0 |
T36 | 118068 | 117900 | 0 | 0 |
T37 | 6358 | 6186 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 159 | 159 | 0 | 0 |
OutputsKnown_A | 19587565 | 19546871 | 0 | 0 |
gen_flops.OutputDelay_A | 19587565 | 19545044 | 0 | 477 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159 | 159 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19546871 | 0 | 0 |
T1 | 118267 | 118179 | 0 | 0 |
T2 | 1273 | 1182 | 0 | 0 |
T3 | 115282 | 115025 | 0 | 0 |
T10 | 242098 | 242018 | 0 | 0 |
T13 | 167920 | 167866 | 0 | 0 |
T16 | 385219 | 384023 | 0 | 0 |
T32 | 1239 | 1155 | 0 | 0 |
T35 | 2152 | 2087 | 0 | 0 |
T36 | 59034 | 58950 | 0 | 0 |
T37 | 3179 | 3093 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19545044 | 0 | 477 |
T1 | 118267 | 118176 | 0 | 3 |
T2 | 1273 | 1179 | 0 | 3 |
T3 | 115282 | 115013 | 0 | 3 |
T10 | 242098 | 242015 | 0 | 3 |
T13 | 167920 | 167863 | 0 | 3 |
T16 | 385219 | 383969 | 0 | 3 |
T32 | 1239 | 1152 | 0 | 3 |
T35 | 2152 | 2084 | 0 | 3 |
T36 | 59034 | 58947 | 0 | 3 |
T37 | 3179 | 3090 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 159 | 159 | 0 | 0 |
OutputsKnown_A | 19587565 | 19546871 | 0 | 0 |
gen_flops.OutputDelay_A | 19587565 | 19545044 | 0 | 477 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159 | 159 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19546871 | 0 | 0 |
T1 | 118267 | 118179 | 0 | 0 |
T2 | 1273 | 1182 | 0 | 0 |
T3 | 115282 | 115025 | 0 | 0 |
T10 | 242098 | 242018 | 0 | 0 |
T13 | 167920 | 167866 | 0 | 0 |
T16 | 385219 | 384023 | 0 | 0 |
T32 | 1239 | 1155 | 0 | 0 |
T35 | 2152 | 2087 | 0 | 0 |
T36 | 59034 | 58950 | 0 | 0 |
T37 | 3179 | 3093 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19545044 | 0 | 477 |
T1 | 118267 | 118176 | 0 | 3 |
T2 | 1273 | 1179 | 0 | 3 |
T3 | 115282 | 115013 | 0 | 3 |
T10 | 242098 | 242015 | 0 | 3 |
T13 | 167920 | 167863 | 0 | 3 |
T16 | 385219 | 383969 | 0 | 3 |
T32 | 1239 | 1152 | 0 | 3 |
T35 | 2152 | 2084 | 0 | 3 |
T36 | 59034 | 58947 | 0 | 3 |
T37 | 3179 | 3090 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 159 | 159 | 0 | 0 |
OutputsKnown_A | 19587565 | 19546871 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19587565 | 19546871 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159 | 159 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19546871 | 0 | 0 |
T1 | 118267 | 118179 | 0 | 0 |
T2 | 1273 | 1182 | 0 | 0 |
T3 | 115282 | 115025 | 0 | 0 |
T10 | 242098 | 242018 | 0 | 0 |
T13 | 167920 | 167866 | 0 | 0 |
T16 | 385219 | 384023 | 0 | 0 |
T32 | 1239 | 1155 | 0 | 0 |
T35 | 2152 | 2087 | 0 | 0 |
T36 | 59034 | 58950 | 0 | 0 |
T37 | 3179 | 3093 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19546871 | 0 | 0 |
T1 | 118267 | 118179 | 0 | 0 |
T2 | 1273 | 1182 | 0 | 0 |
T3 | 115282 | 115025 | 0 | 0 |
T10 | 242098 | 242018 | 0 | 0 |
T13 | 167920 | 167866 | 0 | 0 |
T16 | 385219 | 384023 | 0 | 0 |
T32 | 1239 | 1155 | 0 | 0 |
T35 | 2152 | 2087 | 0 | 0 |
T36 | 59034 | 58950 | 0 | 0 |
T37 | 3179 | 3093 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 159 | 159 | 0 | 0 |
OutputsKnown_A | 19587565 | 19546871 | 0 | 0 |
gen_no_flops.OutputDelay_A | 19587565 | 19546871 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159 | 159 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19546871 | 0 | 0 |
T1 | 118267 | 118179 | 0 | 0 |
T2 | 1273 | 1182 | 0 | 0 |
T3 | 115282 | 115025 | 0 | 0 |
T10 | 242098 | 242018 | 0 | 0 |
T13 | 167920 | 167866 | 0 | 0 |
T16 | 385219 | 384023 | 0 | 0 |
T32 | 1239 | 1155 | 0 | 0 |
T35 | 2152 | 2087 | 0 | 0 |
T36 | 59034 | 58950 | 0 | 0 |
T37 | 3179 | 3093 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 19587565 | 19546871 | 0 | 0 |
T1 | 118267 | 118179 | 0 | 0 |
T2 | 1273 | 1182 | 0 | 0 |
T3 | 115282 | 115025 | 0 | 0 |
T10 | 242098 | 242018 | 0 | 0 |
T13 | 167920 | 167866 | 0 | 0 |
T16 | 385219 | 384023 | 0 | 0 |
T32 | 1239 | 1155 | 0 | 0 |
T35 | 2152 | 2087 | 0 | 0 |
T36 | 59034 | 58950 | 0 | 0 |
T37 | 3179 | 3093 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |