Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	228974	1		T7	2		T8	16		T4	14
full_word	572045	1		T8	12		T4	4		T5	33

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	800729	1		T7	2		T8	28		T4	18
auto[TlIntgErrCmd]	82	1		T42	2		T43	4		T44	5
auto[TlIntgErrData]	105	1		T42	5		T43	9		T44	6
auto[TlIntgErrBoth]	103	1		T42	3		T43	7		T44	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	475628	1		T8	12		T5	24		T30	80
auto[1]	325391	1		T7	2		T8	16		T4	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	192241	1		T8	4		T5	12		T6	16
auto[TlIntgErrNone]	partial	auto[1]	36464	1		T7	2		T8	12		T4	14
auto[TlIntgErrNone]	full_word	auto[0]	283253	1		T8	8		T5	12		T30	80
auto[TlIntgErrNone]	full_word	auto[1]	288771	1		T8	4		T4	4		T5	21
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T43	3		T44	4		T72	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T42	2		T43	1		T44	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T127	1		T128	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T129	1		T127	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1		T42	3		T43	4		T44	4
auto[TlIntgErrData]	partial	auto[1]	48	1		T42	2		T43	5		T44	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T130	1		T131	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T121	1		T125	1		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T42	1		T43	3		T44	6
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T42	2		T43	4		T44	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T120	1		T121	2		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T44	1		T72	1		T125	1