Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198452	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	570871	1		T8	12		T4	4		T5	33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	474073	1		T8	12		T5	24		T30	80
values[0x0]	145462	1		T7	1		T8	10		T4	8
values[0x1]	149788	1		T7	1		T8	6		T4	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153357	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	615966	1		T8	14		T4	5		T5	42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2772	1		T65	4		T45	4		T42	21
valid_sources[0x01]	2982	1		T30	3		T31	1		T45	1
valid_sources[0x02]	3183	1		T10	2		T45	2		T48	18
valid_sources[0x03]	2823	1		T5	1		T65	1		T31	2
valid_sources[0x04]	3003	1		T5	1		T45	5		T42	19
valid_sources[0x05]	2836	1		T4	1		T45	1		T42	22
valid_sources[0x06]	2736	1		T45	3		T42	5		T48	23
valid_sources[0x07]	3139	1		T5	3		T30	1		T42	23
valid_sources[0x08]	2995	1		T5	1		T21	1		T65	7
valid_sources[0x09]	3137	1		T65	2		T45	2		T48	5
valid_sources[0x0a]	3666	1		T5	2		T45	4		T48	11
valid_sources[0x0b]	2644	1		T45	4		T48	8		T49	3
valid_sources[0x0c]	2796	1		T5	3		T45	5		T48	14
valid_sources[0x0d]	3003	1		T45	4		T42	19		T48	21
valid_sources[0x0e]	3684	1		T5	2		T45	1		T48	10
valid_sources[0x0f]	2696	1		T45	2		T48	14		T49	5
valid_sources[0x10]	3267	1		T42	53		T48	13		T49	3
valid_sources[0x11]	2851	1		T5	1		T30	1		T34	1
valid_sources[0x12]	2954	1		T45	4		T48	15		T49	9
valid_sources[0x13]	4044	1		T31	1		T45	2		T42	13
valid_sources[0x14]	2799	1		T45	1		T48	10		T49	6
valid_sources[0x15]	2896	1		T5	2		T65	1		T45	4
valid_sources[0x16]	2852	1		T45	4		T48	3		T49	5
valid_sources[0x17]	3416	1		T45	3		T48	10		T49	3
valid_sources[0x18]	3251	1		T45	5		T42	101		T48	20
valid_sources[0x19]	3046	1		T65	1		T31	1		T48	12
valid_sources[0x1a]	2848	1		T5	1		T21	2		T31	1
valid_sources[0x1b]	2802	1		T5	1		T18	9		T45	3
valid_sources[0x1c]	2787	1		T30	1		T31	1		T45	2
valid_sources[0x1d]	2877	1		T65	1		T31	1		T45	5
valid_sources[0x1e]	2854	1		T34	2		T42	32		T48	13
valid_sources[0x1f]	2927	1		T10	3		T45	2		T48	12
valid_sources[0x20]	2715	1		T5	1		T21	1		T45	2
valid_sources[0x21]	3016	1		T45	5		T48	8		T49	7
valid_sources[0x22]	2883	1		T5	2		T21	3		T45	2
valid_sources[0x23]	2953	1		T5	1		T31	1		T45	1
valid_sources[0x24]	3003	1		T45	2		T48	5		T49	9
valid_sources[0x25]	2859	1		T65	3		T45	7		T42	4
valid_sources[0x26]	3108	1		T31	3		T45	2		T48	12
valid_sources[0x27]	2851	1		T45	5		T42	6		T48	11
valid_sources[0x28]	3323	1		T65	3		T45	3		T48	17
valid_sources[0x29]	3199	1		T5	1		T45	5		T42	11
valid_sources[0x2a]	3255	1		T5	1		T31	2		T45	1
valid_sources[0x2b]	3175	1		T31	1		T48	7		T49	5
valid_sources[0x2c]	2843	1		T31	1		T45	1		T42	24
valid_sources[0x2d]	3028	1		T5	1		T45	5		T42	38
valid_sources[0x2e]	2517	1		T45	5		T48	11		T56	143
valid_sources[0x2f]	2955	1		T65	5		T42	1		T48	13
valid_sources[0x30]	3580	1		T45	8		T42	634		T48	15
valid_sources[0x31]	2689	1		T45	2		T48	18		T56	136
valid_sources[0x32]	2977	1		T31	2		T45	2		T42	7
valid_sources[0x33]	2883	1		T45	1		T48	14		T49	2
valid_sources[0x34]	2533	1		T30	2		T31	1		T45	2
valid_sources[0x35]	3009	1		T4	3		T21	1		T45	2
valid_sources[0x36]	2789	1		T133	2		T45	4		T42	5
valid_sources[0x37]	2922	1		T42	5		T48	15		T49	6
valid_sources[0x38]	2864	1		T10	1		T45	2		T48	12
valid_sources[0x39]	2897	1		T5	1		T45	1		T48	20
valid_sources[0x3a]	3006	1		T45	1		T42	53		T48	17
valid_sources[0x3b]	2910	1		T5	1		T48	15		T56	151
valid_sources[0x3c]	3025	1		T31	3		T48	12		T49	1
valid_sources[0x3d]	2849	1		T45	2		T48	13		T49	1
valid_sources[0x3e]	3159	1		T33	2		T45	7		T42	14
valid_sources[0x3f]	2940	1		T5	1		T74	2		T18	1
valid_sources[0x40]	2792	1		T5	1		T31	1		T45	3
valid_sources[0x41]	2850	1		T45	3		T42	3		T48	14
valid_sources[0x42]	2874	1		T45	1		T48	10		T49	5
valid_sources[0x43]	3108	1		T45	5		T48	11		T49	14
valid_sources[0x44]	3162	1		T31	2		T48	16		T49	9
valid_sources[0x45]	2798	1		T65	3		T45	3		T42	10
valid_sources[0x46]	2741	1		T45	3		T48	11		T49	1
valid_sources[0x47]	3320	1		T18	1		T31	1		T45	2
valid_sources[0x48]	2942	1		T5	1		T45	3		T42	70
valid_sources[0x49]	2854	1		T30	2		T45	2		T48	19
valid_sources[0x4a]	3087	1		T21	1		T31	1		T45	4
valid_sources[0x4b]	3088	1		T45	2		T42	17		T48	9
valid_sources[0x4c]	4143	1		T65	2		T45	1		T42	17
valid_sources[0x4d]	3078	1		T31	2		T45	6		T48	9
valid_sources[0x4e]	3086	1		T5	2		T33	1		T45	1
valid_sources[0x4f]	3266	1		T33	1		T48	7		T49	2
valid_sources[0x50]	2641	1		T5	1		T45	2		T48	7
valid_sources[0x51]	2969	1		T48	7		T49	10		T56	120
valid_sources[0x52]	3064	1		T4	4		T45	3		T42	13
valid_sources[0x53]	2781	1		T5	1		T21	1		T65	1
valid_sources[0x54]	3410	1		T74	1		T45	3		T48	17
valid_sources[0x55]	2825	1		T5	1		T65	1		T45	4
valid_sources[0x56]	3091	1		T33	1		T18	1		T42	298
valid_sources[0x57]	3086	1		T65	4		T45	5		T48	12
valid_sources[0x58]	3887	1		T45	2		T48	14		T49	5
valid_sources[0x59]	3101	1		T8	1		T65	2		T45	3
valid_sources[0x5a]	3243	1		T5	1		T42	275		T48	16
valid_sources[0x5b]	3143	1		T5	3		T30	3		T45	2
valid_sources[0x5c]	2833	1		T21	2		T31	2		T45	6
valid_sources[0x5d]	3036	1		T5	1		T31	1		T45	4
valid_sources[0x5e]	3193	1		T10	1		T31	1		T45	2
valid_sources[0x5f]	3130	1		T6	124		T45	6		T42	275
valid_sources[0x60]	2751	1		T45	1		T48	15		T49	1
valid_sources[0x61]	2743	1		T7	2		T34	1		T45	4
valid_sources[0x62]	3694	1		T5	1		T33	2		T31	4
valid_sources[0x63]	2737	1		T31	1		T45	1		T48	11
valid_sources[0x64]	3057	1		T5	2		T65	2		T31	2
valid_sources[0x65]	2905	1		T10	1		T65	5		T48	20
valid_sources[0x66]	3272	1		T10	3		T45	3		T48	12
valid_sources[0x67]	2950	1		T5	2		T45	5		T48	7
valid_sources[0x68]	3056	1		T45	4		T42	1		T48	11
valid_sources[0x69]	2711	1		T5	3		T10	1		T48	16
valid_sources[0x6a]	2758	1		T21	2		T65	2		T48	7
valid_sources[0x6b]	2950	1		T31	2		T45	1		T48	10
valid_sources[0x6c]	2940	1		T18	1		T42	17		T48	10
valid_sources[0x6d]	2756	1		T30	1		T31	4		T45	1
valid_sources[0x6e]	2785	1		T45	3		T48	8		T49	16
valid_sources[0x6f]	2903	1		T30	3		T45	6		T48	12
valid_sources[0x70]	3199	1		T4	2		T5	1		T21	1
valid_sources[0x71]	3001	1		T31	1		T45	1		T48	13
valid_sources[0x72]	2763	1		T30	1		T45	6		T48	17
valid_sources[0x73]	3129	1		T4	1		T45	3		T42	32
valid_sources[0x74]	2996	1		T5	1		T30	6		T45	2
valid_sources[0x75]	2926	1		T21	1		T28	38		T45	1
valid_sources[0x76]	2823	1		T4	1		T31	1		T45	4
valid_sources[0x77]	2916	1		T31	1		T45	2		T48	21
valid_sources[0x78]	3676	1		T5	1		T45	4		T42	6
valid_sources[0x79]	2722	1		T45	3		T48	12		T49	5
valid_sources[0x7a]	2971	1		T8	2		T5	1		T30	2
valid_sources[0x7b]	3389	1		T30	1		T45	3		T42	282
valid_sources[0x7c]	2785	1		T5	1		T33	1		T65	3
valid_sources[0x7d]	2969	1		T34	3		T45	7		T48	15
valid_sources[0x7e]	2611	1		T21	1		T45	2		T48	8
valid_sources[0x7f]	3202	1		T31	3		T45	3		T42	2
valid_sources[0x80]	2848	1		T5	1		T45	2		T42	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

283116

1

T8

8

T5

12

T30

80

values[0x0]

all_enables

biggest_size

143722

1

T8

3

T4

2

T5

18

values[0x1]

all_enables

biggest_size

144033

1

T8

1

T4

2

T5

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1946	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14788	1		T2	2		T3	1		T37	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4909	1		T45	108		T42	14		T48	8
values[0x0]	5898	1		T1	4		T2	3		T36	2
values[0x1]	5927	1		T1	7		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1564	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	15170	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	45	1		T80	1		T46	4		T77	1
valid_sources[0x01]	45	1		T55	1		T43	2		T44	7
valid_sources[0x02]	60	1		T134	2		T43	1		T77	3
valid_sources[0x03]	72	1		T50	2		T55	2		T75	14
valid_sources[0x04]	271	1		T135	3		T55	1		T76	2
valid_sources[0x05]	57	1		T55	2		T56	2		T43	1
valid_sources[0x06]	48	1		T115	1		T49	2		T80	1
valid_sources[0x07]	64	1		T136	1		T137	1		T138	1
valid_sources[0x08]	43	1		T37	1		T55	2		T47	3
valid_sources[0x09]	60	1		T139	2		T140	3		T49	2
valid_sources[0x0a]	72	1		T141	1		T142	8		T60	3
valid_sources[0x0b]	33	1		T77	4		T63	4		T143	1
valid_sources[0x0c]	56	1		T144	13		T57	1		T76	1
valid_sources[0x0d]	70	1		T79	1		T145	3		T58	1
valid_sources[0x0e]	62	1		T146	12		T42	2		T46	2
valid_sources[0x0f]	30	1		T134	1		T55	1		T46	1
valid_sources[0x10]	38	1		T37	1		T43	1		T77	4
valid_sources[0x11]	63	1		T53	4		T45	2		T55	1
valid_sources[0x12]	30	1		T55	1		T43	1		T46	3
valid_sources[0x13]	65	1		T55	1		T76	2		T77	4
valid_sources[0x14]	53	1		T46	4		T47	6		T107	2
valid_sources[0x15]	35	1		T56	4		T46	2		T77	1
valid_sources[0x16]	83	1		T139	1		T55	1		T46	1
valid_sources[0x17]	52	1		T134	1		T60	1		T46	1
valid_sources[0x18]	187	1		T37	1		T43	1		T76	13
valid_sources[0x19]	36	1		T55	1		T80	1		T76	3
valid_sources[0x1a]	54	1		T115	2		T55	1		T47	4
valid_sources[0x1b]	101	1		T138	1		T46	1		T47	12
valid_sources[0x1c]	67	1		T52	1		T115	11		T60	1
valid_sources[0x1d]	149	1		T139	1		T136	1		T55	1
valid_sources[0x1e]	28	1		T55	1		T77	1		T147	1
valid_sources[0x1f]	36	1		T139	1		T138	1		T141	1
valid_sources[0x20]	33	1		T45	5		T46	1		T77	2
valid_sources[0x21]	66	1		T37	1		T148	16		T55	1
valid_sources[0x22]	44	1		T116	1		T137	1		T149	1
valid_sources[0x23]	31	1		T55	1		T76	1		T106	1
valid_sources[0x24]	40	1		T55	3		T43	1		T46	1
valid_sources[0x25]	57	1		T114	1		T55	1		T80	1
valid_sources[0x26]	58	1		T37	1		T80	1		T75	16
valid_sources[0x27]	119	1		T150	5		T56	3		T76	2
valid_sources[0x28]	47	1		T37	1		T60	1		T46	1
valid_sources[0x29]	71	1		T149	2		T45	12		T55	2
valid_sources[0x2a]	31	1		T60	2		T46	1		T77	2
valid_sources[0x2b]	90	1		T45	26		T48	8		T55	2
valid_sources[0x2c]	53	1		T151	1		T48	6		T143	2
valid_sources[0x2d]	60	1		T149	2		T55	1		T60	2
valid_sources[0x2e]	70	1		T60	3		T76	4		T77	11
valid_sources[0x2f]	49	1		T45	1		T44	3		T46	2
valid_sources[0x30]	61	1		T79	1		T137	1		T76	1
valid_sources[0x31]	55	1		T152	1		T43	2		T47	2
valid_sources[0x32]	39	1		T60	1		T77	4		T147	1
valid_sources[0x33]	47	1		T153	1		T152	1		T46	3
valid_sources[0x34]	137	1		T75	57		T46	2		T47	3
valid_sources[0x35]	45	1		T137	1		T56	2		T80	1
valid_sources[0x36]	55	1		T76	2		T46	1		T77	2
valid_sources[0x37]	51	1		T37	1		T115	2		T46	2
valid_sources[0x38]	130	1		T46	1		T47	12		T77	3
valid_sources[0x39]	67	1		T56	2		T46	2		T47	4
valid_sources[0x3a]	58	1		T55	1		T56	1		T80	1
valid_sources[0x3b]	58	1		T50	2		T56	5		T60	1
valid_sources[0x3c]	56	1		T152	1		T56	4		T43	1
valid_sources[0x3d]	49	1		T50	1		T136	1		T55	1
valid_sources[0x3e]	58	1		T154	2		T55	1		T77	5
valid_sources[0x3f]	63	1		T55	2		T60	1		T80	1
valid_sources[0x40]	121	1		T155	1		T45	22		T55	1
valid_sources[0x41]	40	1		T50	1		T156	6		T55	1
valid_sources[0x42]	38	1		T55	1		T46	1		T77	8
valid_sources[0x43]	56	1		T152	1		T55	1		T43	1
valid_sources[0x44]	45	1		T50	1		T60	1		T76	3
valid_sources[0x45]	37	1		T136	1		T55	3		T56	3
valid_sources[0x46]	34	1		T76	3		T132	5		T157	8
valid_sources[0x47]	65	1		T145	3		T76	8		T46	4
valid_sources[0x48]	54	1		T46	4		T77	5		T62	3
valid_sources[0x49]	121	1		T155	1		T77	1		T105	1
valid_sources[0x4a]	49	1		T158	4		T55	1		T76	2
valid_sources[0x4b]	56	1		T141	1		T43	1		T75	11
valid_sources[0x4c]	45	1		T1	11		T115	1		T60	2
valid_sources[0x4d]	64	1		T45	23		T55	2		T46	2
valid_sources[0x4e]	43	1		T55	1		T60	1		T76	4
valid_sources[0x4f]	41	1		T77	4		T120	1		T125	9
valid_sources[0x50]	144	1		T141	2		T45	5		T55	1
valid_sources[0x51]	157	1		T45	13		T55	1		T46	2
valid_sources[0x52]	51	1		T116	2		T55	1		T60	1
valid_sources[0x53]	38	1		T116	1		T55	1		T60	1
valid_sources[0x54]	101	1		T37	1		T42	27		T60	1
valid_sources[0x55]	37	1		T137	1		T55	2		T46	1
valid_sources[0x56]	48	1		T116	1		T155	1		T134	1
valid_sources[0x57]	46	1		T139	1		T46	5		T47	3
valid_sources[0x58]	40	1		T54	3		T159	1		T46	1
valid_sources[0x59]	42	1		T52	1		T134	1		T46	2
valid_sources[0x5a]	31	1		T151	2		T46	4		T77	1
valid_sources[0x5b]	115	1		T117	1		T134	1		T55	1
valid_sources[0x5c]	65	1		T160	5		T149	2		T55	1
valid_sources[0x5d]	100	1		T136	1		T55	2		T46	1
valid_sources[0x5e]	32	1		T55	1		T60	2		T46	4
valid_sources[0x5f]	31	1		T60	1		T76	4		T46	3
valid_sources[0x60]	33	1		T55	1		T59	2		T46	1
valid_sources[0x61]	59	1		T138	1		T55	3		T47	5
valid_sources[0x62]	94	1		T55	1		T60	1		T76	7
valid_sources[0x63]	59	1		T137	1		T60	2		T75	5
valid_sources[0x64]	48	1		T2	4		T137	1		T55	1
valid_sources[0x65]	49	1		T37	2		T156	3		T55	1
valid_sources[0x66]	34	1		T46	1		T47	9		T157	1
valid_sources[0x67]	48	1		T45	1		T55	2		T46	3
valid_sources[0x68]	155	1		T79	1		T55	1		T56	10
valid_sources[0x69]	80	1		T161	1		T45	1		T55	1
valid_sources[0x6a]	118	1		T55	1		T56	2		T43	1
valid_sources[0x6b]	34	1		T80	2		T76	3		T46	1
valid_sources[0x6c]	231	1		T155	1		T141	1		T140	3
valid_sources[0x6d]	85	1		T3	1		T55	1		T46	7
valid_sources[0x6e]	67	1		T37	1		T162	6		T55	3
valid_sources[0x6f]	32	1		T55	2		T56	1		T46	4
valid_sources[0x70]	42	1		T163	3		T56	4		T43	1
valid_sources[0x71]	31	1		T42	1		T55	1		T46	1
valid_sources[0x72]	76	1		T55	2		T60	1		T76	1
valid_sources[0x73]	64	1		T45	2		T56	3		T44	6
valid_sources[0x74]	52	1		T149	1		T45	7		T55	1
valid_sources[0x75]	55	1		T114	2		T56	1		T77	3
valid_sources[0x76]	75	1		T45	12		T55	1		T63	1
valid_sources[0x77]	128	1		T164	1		T45	56		T55	1
valid_sources[0x78]	43	1		T43	2		T46	6		T47	1
valid_sources[0x79]	73	1		T141	1		T48	1		T76	6
valid_sources[0x7a]	51	1		T55	1		T47	1		T77	2
valid_sources[0x7b]	48	1		T159	2		T43	1		T46	1
valid_sources[0x7c]	43	1		T134	1		T45	3		T55	1
valid_sources[0x7d]	44	1		T155	2		T80	1		T46	1
valid_sources[0x7e]	50	1		T60	2		T47	8		T77	1
valid_sources[0x7f]	47	1		T55	1		T46	2		T77	4
valid_sources[0x80]	35	1		T57	2		T46	1		T77	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4103

1

T45

108

T42

3

T48

8

values[0x0]

all_enables

biggest_size

5415

1

T2

2

T37

2

T51

1

values[0x1]

all_enables

biggest_size

5270

1

T3

1

T37

2

T50

3