SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 644 | 644 | 0 | 0 |
OutputsKnown_A | 97205136 | 97015944 | 0 | 0 |
gen_flops.OutputDelay_A | 48602568 | 48503730 | 0 | 966 |
gen_no_flops.OutputDelay_A | 48602568 | 48507972 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 644 | 644 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T7 | 4 | 4 | 0 | 0 |
T8 | 4 | 4 | 0 | 0 |
T9 | 4 | 4 | 0 | 0 |
T11 | 4 | 4 | 0 | 0 |
T36 | 4 | 4 | 0 | 0 |
T37 | 4 | 4 | 0 | 0 |
T38 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97205136 | 97015944 | 0 | 0 |
T1 | 5708 | 5460 | 0 | 0 |
T2 | 6948 | 6748 | 0 | 0 |
T3 | 4444 | 4152 | 0 | 0 |
T7 | 7708 | 7472 | 0 | 0 |
T8 | 49832 | 49484 | 0 | 0 |
T9 | 511384 | 511096 | 0 | 0 |
T11 | 140848 | 140540 | 0 | 0 |
T36 | 5644 | 5280 | 0 | 0 |
T37 | 6172 | 5948 | 0 | 0 |
T38 | 25928 | 20036 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48602568 | 48503730 | 0 | 966 |
T1 | 2854 | 2724 | 0 | 6 |
T2 | 3474 | 3368 | 0 | 6 |
T3 | 2222 | 2070 | 0 | 6 |
T7 | 3854 | 3730 | 0 | 6 |
T8 | 24916 | 24736 | 0 | 6 |
T9 | 255692 | 255540 | 0 | 6 |
T11 | 70424 | 70264 | 0 | 6 |
T36 | 2822 | 2634 | 0 | 6 |
T37 | 3086 | 2968 | 0 | 6 |
T38 | 12964 | 9892 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 48602568 | 48507972 | 0 | 0 |
T1 | 2854 | 2730 | 0 | 0 |
T2 | 3474 | 3374 | 0 | 0 |
T3 | 2222 | 2076 | 0 | 0 |
T7 | 3854 | 3736 | 0 | 0 |
T8 | 24916 | 24742 | 0 | 0 |
T9 | 255692 | 255548 | 0 | 0 |
T11 | 70424 | 70270 | 0 | 0 |
T36 | 2822 | 2640 | 0 | 0 |
T37 | 3086 | 2974 | 0 | 0 |
T38 | 12964 | 10018 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 24301284 | 24253986 | 0 | 0 |
gen_flops.OutputDelay_A | 24301284 | 24251865 | 0 | 483 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24253986 | 0 | 0 |
T1 | 1427 | 1365 | 0 | 0 |
T2 | 1737 | 1687 | 0 | 0 |
T3 | 1111 | 1038 | 0 | 0 |
T7 | 1927 | 1868 | 0 | 0 |
T8 | 12458 | 12371 | 0 | 0 |
T9 | 127846 | 127774 | 0 | 0 |
T11 | 35212 | 35135 | 0 | 0 |
T36 | 1411 | 1320 | 0 | 0 |
T37 | 1543 | 1487 | 0 | 0 |
T38 | 6482 | 5009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24251865 | 0 | 483 |
T1 | 1427 | 1362 | 0 | 3 |
T2 | 1737 | 1684 | 0 | 3 |
T3 | 1111 | 1035 | 0 | 3 |
T7 | 1927 | 1865 | 0 | 3 |
T8 | 12458 | 12368 | 0 | 3 |
T9 | 127846 | 127770 | 0 | 3 |
T11 | 35212 | 35132 | 0 | 3 |
T36 | 1411 | 1317 | 0 | 3 |
T37 | 1543 | 1484 | 0 | 3 |
T38 | 6482 | 4946 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 24301284 | 24253986 | 0 | 0 |
gen_flops.OutputDelay_A | 24301284 | 24251865 | 0 | 483 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24253986 | 0 | 0 |
T1 | 1427 | 1365 | 0 | 0 |
T2 | 1737 | 1687 | 0 | 0 |
T3 | 1111 | 1038 | 0 | 0 |
T7 | 1927 | 1868 | 0 | 0 |
T8 | 12458 | 12371 | 0 | 0 |
T9 | 127846 | 127774 | 0 | 0 |
T11 | 35212 | 35135 | 0 | 0 |
T36 | 1411 | 1320 | 0 | 0 |
T37 | 1543 | 1487 | 0 | 0 |
T38 | 6482 | 5009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24251865 | 0 | 483 |
T1 | 1427 | 1362 | 0 | 3 |
T2 | 1737 | 1684 | 0 | 3 |
T3 | 1111 | 1035 | 0 | 3 |
T7 | 1927 | 1865 | 0 | 3 |
T8 | 12458 | 12368 | 0 | 3 |
T9 | 127846 | 127770 | 0 | 3 |
T11 | 35212 | 35132 | 0 | 3 |
T36 | 1411 | 1317 | 0 | 3 |
T37 | 1543 | 1484 | 0 | 3 |
T38 | 6482 | 4946 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 24301284 | 24253986 | 0 | 0 |
gen_no_flops.OutputDelay_A | 24301284 | 24253986 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24253986 | 0 | 0 |
T1 | 1427 | 1365 | 0 | 0 |
T2 | 1737 | 1687 | 0 | 0 |
T3 | 1111 | 1038 | 0 | 0 |
T7 | 1927 | 1868 | 0 | 0 |
T8 | 12458 | 12371 | 0 | 0 |
T9 | 127846 | 127774 | 0 | 0 |
T11 | 35212 | 35135 | 0 | 0 |
T36 | 1411 | 1320 | 0 | 0 |
T37 | 1543 | 1487 | 0 | 0 |
T38 | 6482 | 5009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24253986 | 0 | 0 |
T1 | 1427 | 1365 | 0 | 0 |
T2 | 1737 | 1687 | 0 | 0 |
T3 | 1111 | 1038 | 0 | 0 |
T7 | 1927 | 1868 | 0 | 0 |
T8 | 12458 | 12371 | 0 | 0 |
T9 | 127846 | 127774 | 0 | 0 |
T11 | 35212 | 35135 | 0 | 0 |
T36 | 1411 | 1320 | 0 | 0 |
T37 | 1543 | 1487 | 0 | 0 |
T38 | 6482 | 5009 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 24301284 | 24253986 | 0 | 0 |
gen_no_flops.OutputDelay_A | 24301284 | 24253986 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24253986 | 0 | 0 |
T1 | 1427 | 1365 | 0 | 0 |
T2 | 1737 | 1687 | 0 | 0 |
T3 | 1111 | 1038 | 0 | 0 |
T7 | 1927 | 1868 | 0 | 0 |
T8 | 12458 | 12371 | 0 | 0 |
T9 | 127846 | 127774 | 0 | 0 |
T11 | 35212 | 35135 | 0 | 0 |
T36 | 1411 | 1320 | 0 | 0 |
T37 | 1543 | 1487 | 0 | 0 |
T38 | 6482 | 5009 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 24301284 | 24253986 | 0 | 0 |
T1 | 1427 | 1365 | 0 | 0 |
T2 | 1737 | 1687 | 0 | 0 |
T3 | 1111 | 1038 | 0 | 0 |
T7 | 1927 | 1868 | 0 | 0 |
T8 | 12458 | 12371 | 0 | 0 |
T9 | 127846 | 127774 | 0 | 0 |
T11 | 35212 | 35135 | 0 | 0 |
T36 | 1411 | 1320 | 0 | 0 |
T37 | 1543 | 1487 | 0 | 0 |
T38 | 6482 | 5009 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |