SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 753131 | 1 | T3 | 49 | T4 | 29 | T5 | 70 | |||
auto[1] | 19439 | 1 | T8 | 80 | T22 | 80 | T39 | 232 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 772348 | 1 | T3 | 49 | T4 | 29 | T8 | 80 | |||
values[1] | 12 | 1 | T36 | 2 | T120 | 1 | T121 | 3 | |||
values[2] | 4 | 1 | T122 | 1 | T123 | 1 | T124 | 1 | |||
values[3] | 129 | 1 | T36 | 5 | T37 | 5 | T38 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 772354 | 1 | T3 | 49 | T4 | 29 | T8 | 80 | |||
values[1] | 27 | 1 | T36 | 2 | T125 | 3 | T120 | 3 | |||
values[2] | 4 | 1 | T126 | 1 | T127 | 1 | T124 | 1 | |||
values[3] | 97 | 1 | T36 | 5 | T37 | 1 | T38 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 772240 | 1 | T3 | 49 | T4 | 29 | T8 | 80 | |||
auto[TlIntgErrCmd] | 114 | 1 | T36 | 4 | T37 | 4 | T38 | 8 | |||
auto[TlIntgErrData] | 108 | 1 | T36 | 11 | T37 | 4 | T38 | 4 | |||
auto[TlIntgErrBoth] | 108 | 1 | T36 | 5 | T37 | 2 | T38 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 32738 | 0 | T26 | 12 | T31 | 7 | T32 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 32526 | 1 | T26 | 12 | T31 | 7 | T32 | 11 | |||
values[1] | 19 | 1 | T38 | 2 | T125 | 3 | T128 | 1 | |||
values[2] | 2 | 1 | T38 | 1 | T129 | 1 | - | - | |||
values[3] | 121 | 1 | T36 | 6 | T37 | 3 | T38 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 32517 | 1 | T26 | 12 | T31 | 7 | T32 | 11 | |||
values[1] | 27 | 1 | T36 | 3 | T38 | 2 | T125 | 3 | |||
values[2] | 2 | 1 | T128 | 1 | T123 | 1 | - | - | |||
values[3] | 89 | 1 | T36 | 5 | T37 | 5 | T38 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 32408 | 1 | T26 | 12 | T31 | 7 | T32 | 11 | |||
auto[TlIntgErrCmd] | 109 | 1 | T36 | 7 | T37 | 2 | T38 | 10 | |||
auto[TlIntgErrData] | 118 | 1 | T36 | 10 | T37 | 5 | T38 | 5 | |||
auto[TlIntgErrBoth] | 103 | 1 | T36 | 3 | T37 | 3 | T38 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |