Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	228602	1		T3	39		T4	15		T5	48
full_word	543968	1		T3	10		T4	14		T8	80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	772240	1		T3	49		T4	29		T8	80
auto[TlIntgErrCmd]	114	1		T36	4		T37	4		T38	8
auto[TlIntgErrData]	108	1		T36	11		T37	4		T38	4
auto[TlIntgErrBoth]	108	1		T36	5		T37	2		T38	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	456811	1		T4	8		T8	80		T5	30
auto[1]	315759	1		T3	49		T4	21		T5	40

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	180522	1		T4	6		T5	16		T6	19
auto[TlIntgErrNone]	partial	auto[1]	47779	1		T3	39		T4	9		T5	32
auto[TlIntgErrNone]	full_word	auto[0]	276136	1		T4	2		T8	80		T5	14
auto[TlIntgErrNone]	full_word	auto[1]	267803	1		T3	10		T4	12		T5	8
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T36	3		T38	3		T125	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T36	1		T37	2		T38	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T37	2		T121	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T120	1		T121	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T36	4		T37	1		T38	2
auto[TlIntgErrData]	partial	auto[1]	52	1		T36	7		T37	3		T38	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T125	1		T122	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T122	1		T124	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T36	1		T38	5		T125	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T36	3		T37	2		T38	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T38	1		T121	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T36	1		T123	2		T124	1