Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	187641	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	542333	1		T3	10		T4	14		T8	80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	454879	1		T4	8		T8	80		T5	30
values[0x0]	135440	1		T3	20		T4	12		T5	15
values[0x1]	139655	1		T3	29		T4	9		T5	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142872	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	587102	1		T3	13		T4	15		T8	80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2948	1		T3	2		T39	4		T41	3
valid_sources[0x01]	2945	1		T25	1		T10	1		T41	3
valid_sources[0x02]	2438	1		T39	1		T43	3		T75	3
valid_sources[0x03]	2841	1		T132	1		T117	1		T43	16
valid_sources[0x04]	2806	1		T25	1		T41	3		T58	2
valid_sources[0x05]	2156	1		T6	2		T25	1		T9	2
valid_sources[0x06]	2711	1		T43	2		T75	2		T51	7
valid_sources[0x07]	2458	1		T6	1		T39	1		T41	3
valid_sources[0x08]	2609	1		T40	4		T41	3		T58	2
valid_sources[0x09]	2605	1		T10	1		T133	31		T39	1
valid_sources[0x0a]	2786	1		T41	4		T58	1		T43	6
valid_sources[0x0b]	2640	1		T3	1		T24	1		T39	1
valid_sources[0x0c]	2982	1		T10	1		T40	2		T41	5
valid_sources[0x0d]	2747	1		T13	3		T39	4		T43	23
valid_sources[0x0e]	2568	1		T6	5		T39	2		T43	2
valid_sources[0x0f]	2853	1		T6	1		T134	1		T40	1
valid_sources[0x10]	3157	1		T3	1		T39	2		T43	9
valid_sources[0x11]	2790	1		T6	1		T79	2		T39	2
valid_sources[0x12]	2582	1		T3	3		T39	2		T41	3
valid_sources[0x13]	3504	1		T134	1		T39	1		T41	4
valid_sources[0x14]	2704	1		T132	1		T39	1		T41	1
valid_sources[0x15]	3063	1		T39	1		T41	4		T58	1
valid_sources[0x16]	2790	1		T79	7		T9	2		T41	7
valid_sources[0x17]	2845	1		T132	1		T39	3		T40	5
valid_sources[0x18]	4026	1		T18	2		T39	2		T40	19
valid_sources[0x19]	2349	1		T18	1		T39	2		T41	8
valid_sources[0x1a]	3997	1		T74	1		T25	1		T39	1
valid_sources[0x1b]	2609	1		T117	3		T58	1		T43	9
valid_sources[0x1c]	3074	1		T39	1		T41	1		T43	2
valid_sources[0x1d]	3100	1		T39	2		T41	5		T58	1
valid_sources[0x1e]	2364	1		T39	2		T41	6		T43	11
valid_sources[0x1f]	2713	1		T39	2		T41	1		T43	1
valid_sources[0x20]	2597	1		T39	1		T40	6		T41	1
valid_sources[0x21]	3353	1		T4	4		T74	2		T117	1
valid_sources[0x22]	2825	1		T23	2		T39	1		T40	9
valid_sources[0x23]	2489	1		T6	3		T18	3		T132	1
valid_sources[0x24]	2943	1		T39	1		T41	1		T58	1
valid_sources[0x25]	2994	1		T39	1		T58	5		T43	10
valid_sources[0x26]	3087	1		T25	2		T39	2		T58	2
valid_sources[0x27]	2495	1		T39	2		T58	1		T43	2
valid_sources[0x28]	2595	1		T39	1		T40	5		T41	1
valid_sources[0x29]	2901	1		T4	2		T78	21		T39	1
valid_sources[0x2a]	2924	1		T4	1		T132	2		T41	1
valid_sources[0x2b]	3145	1		T117	1		T41	3		T58	1
valid_sources[0x2c]	2827	1		T3	5		T6	2		T24	1
valid_sources[0x2d]	2385	1		T132	1		T117	1		T39	2
valid_sources[0x2e]	2622	1		T39	1		T41	1		T51	23
valid_sources[0x2f]	2772	1		T6	1		T25	1		T117	4
valid_sources[0x30]	2895	1		T18	3		T39	2		T41	14
valid_sources[0x31]	2829	1		T39	2		T40	1		T41	1
valid_sources[0x32]	2313	1		T135	4		T58	3		T43	9
valid_sources[0x33]	3426	1		T58	1		T43	2		T75	3
valid_sources[0x34]	3475	1		T41	4		T58	1		T43	10
valid_sources[0x35]	2845	1		T41	1		T58	1		T43	13
valid_sources[0x36]	2386	1		T10	2		T39	1		T40	6
valid_sources[0x37]	2498	1		T43	3		T75	2		T51	18
valid_sources[0x38]	2722	1		T25	1		T117	1		T39	2
valid_sources[0x39]	2743	1		T117	2		T39	2		T41	1
valid_sources[0x3a]	2742	1		T117	1		T39	2		T41	6
valid_sources[0x3b]	2598	1		T39	2		T41	3		T43	4
valid_sources[0x3c]	2563	1		T6	1		T39	1		T58	1
valid_sources[0x3d]	2451	1		T9	5		T134	1		T39	4
valid_sources[0x3e]	2863	1		T39	1		T41	4		T58	1
valid_sources[0x3f]	3185	1		T39	2		T41	5		T43	4
valid_sources[0x40]	2593	1		T10	1		T39	2		T43	5
valid_sources[0x41]	3231	1		T39	3		T41	4		T43	5
valid_sources[0x42]	2319	1		T6	3		T117	2		T43	10
valid_sources[0x43]	2521	1		T4	1		T41	2		T43	14
valid_sources[0x44]	2640	1		T132	2		T117	2		T41	6
valid_sources[0x45]	2215	1		T6	6		T25	1		T136	3
valid_sources[0x46]	2757	1		T6	1		T39	3		T43	1
valid_sources[0x47]	2826	1		T79	1		T42	275		T39	2
valid_sources[0x48]	2476	1		T40	4		T41	3		T58	1
valid_sources[0x49]	2551	1		T10	1		T39	1		T41	9
valid_sources[0x4a]	3219	1		T39	1		T41	3		T58	1
valid_sources[0x4b]	2935	1		T6	1		T39	1		T41	7
valid_sources[0x4c]	2862	1		T6	5		T41	4		T43	3
valid_sources[0x4d]	3260	1		T39	3		T40	7		T58	1
valid_sources[0x4e]	2997	1		T25	1		T10	2		T39	2
valid_sources[0x4f]	2486	1		T6	1		T41	3		T43	8
valid_sources[0x50]	2807	1		T41	5		T58	1		T43	7
valid_sources[0x51]	2940	1		T134	3		T39	1		T41	1
valid_sources[0x52]	2741	1		T6	1		T10	1		T39	3
valid_sources[0x53]	4895	1		T39	2		T43	14		T75	1
valid_sources[0x54]	2693	1		T132	1		T43	9		T75	1
valid_sources[0x55]	2190	1		T39	1		T41	5		T43	4
valid_sources[0x56]	3107	1		T22	37		T132	2		T39	1
valid_sources[0x57]	2792	1		T18	3		T39	1		T58	1
valid_sources[0x58]	3032	1		T6	1		T41	3		T58	3
valid_sources[0x59]	3434	1		T6	5		T9	3		T41	2
valid_sources[0x5a]	2624	1		T30	87		T135	20		T58	5
valid_sources[0x5b]	2892	1		T6	2		T11	65		T39	1
valid_sources[0x5c]	2494	1		T41	1		T58	3		T43	7
valid_sources[0x5d]	2532	1		T39	1		T40	5		T41	7
valid_sources[0x5e]	2354	1		T6	4		T41	7		T43	11
valid_sources[0x5f]	2538	1		T39	1		T41	2		T58	1
valid_sources[0x60]	3298	1		T39	1		T41	5		T43	6
valid_sources[0x61]	2575	1		T39	1		T40	10		T41	5
valid_sources[0x62]	3613	1		T39	1		T40	3		T41	2
valid_sources[0x63]	2812	1		T6	3		T117	2		T39	1
valid_sources[0x64]	3058	1		T3	5		T117	2		T41	1
valid_sources[0x65]	3778	1		T41	2		T58	1		T43	3
valid_sources[0x66]	3462	1		T25	2		T137	8		T41	4
valid_sources[0x67]	2595	1		T24	1		T39	1		T43	9
valid_sources[0x68]	2725	1		T6	4		T9	1		T58	1
valid_sources[0x69]	2345	1		T117	4		T39	2		T41	5
valid_sources[0x6a]	2874	1		T13	4		T79	2		T117	1
valid_sources[0x6b]	2809	1		T18	1		T41	4		T58	1
valid_sources[0x6c]	2702	1		T74	1		T41	4		T58	1
valid_sources[0x6d]	2597	1		T132	1		T39	1		T41	4
valid_sources[0x6e]	3090	1		T117	5		T39	1		T41	2
valid_sources[0x6f]	2628	1		T117	1		T40	2		T41	3
valid_sources[0x70]	2443	1		T79	1		T39	1		T41	2
valid_sources[0x71]	2775	1		T25	1		T117	2		T24	1
valid_sources[0x72]	2466	1		T39	1		T41	2		T43	5
valid_sources[0x73]	2651	1		T41	10		T58	2		T43	8
valid_sources[0x74]	3676	1		T39	1		T41	5		T58	3
valid_sources[0x75]	2449	1		T6	1		T132	6		T39	2
valid_sources[0x76]	2582	1		T10	4		T41	1		T58	2
valid_sources[0x77]	2952	1		T134	1		T43	3		T75	6
valid_sources[0x78]	2721	1		T6	3		T10	1		T39	2
valid_sources[0x79]	2818	1		T3	1		T25	1		T39	2
valid_sources[0x7a]	3646	1		T3	1		T16	190		T39	1
valid_sources[0x7b]	2423	1		T7	1		T39	2		T41	1
valid_sources[0x7c]	2904	1		T9	3		T39	1		T43	4
valid_sources[0x7d]	2374	1		T117	3		T41	5		T58	4
valid_sources[0x7e]	2671	1		T79	1		T39	1		T41	3
valid_sources[0x7f]	2798	1		T4	1		T6	1		T79	2
valid_sources[0x80]	2683	1		T9	1		T39	1		T40	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

275964

1

T4

2

T8

80

T5

14

values[0x0]

all_enables

biggest_size

133575

1

T3

5

T4

6

T5

4

values[0x1]

all_enables

biggest_size

132794

1

T3

5

T4

6

T5

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2156	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19413	1		T26	3		T31	1		T32	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6411	1		T42	1		T39	9		T40	25
values[0x0]	7411	1		T26	6		T31	3		T32	5
values[0x1]	7747	1		T26	6		T31	4		T32	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1619	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19950	1		T26	6		T31	1		T32	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56	1		T138	1		T39	10		T77	2
valid_sources[0x01]	59	1		T139	1		T140	1		T100	1
valid_sources[0x02]	198	1		T110	1		T141	1		T142	2
valid_sources[0x03]	90	1		T114	1		T59	3		T80	2
valid_sources[0x04]	45	1		T40	2		T43	2		T75	1
valid_sources[0x05]	88	1		T75	2		T53	11		T36	1
valid_sources[0x06]	76	1		T110	1		T40	1		T75	2
valid_sources[0x07]	388	1		T53	3		T77	2		T143	1
valid_sources[0x08]	83	1		T40	2		T75	1		T77	1
valid_sources[0x09]	149	1		T144	9		T39	2		T43	2
valid_sources[0x0a]	56	1		T139	1		T41	1		T43	2
valid_sources[0x0b]	46	1		T51	2		T53	2		T77	2
valid_sources[0x0c]	45	1		T40	1		T41	1		T77	1
valid_sources[0x0d]	85	1		T43	1		T75	5		T77	2
valid_sources[0x0e]	53	1		T43	2		T75	5		T53	2
valid_sources[0x0f]	83	1		T138	1		T145	5		T40	1
valid_sources[0x10]	45	1		T75	3		T53	2		T146	1
valid_sources[0x11]	132	1		T141	1		T147	2		T40	1
valid_sources[0x12]	64	1		T76	2		T80	1		T148	1
valid_sources[0x13]	95	1		T39	1		T43	1		T75	1
valid_sources[0x14]	81	1		T41	1		T76	3		T77	2
valid_sources[0x15]	93	1		T41	2		T43	2		T53	2
valid_sources[0x16]	79	1		T110	1		T113	1		T75	1
valid_sources[0x17]	58	1		T41	2		T75	4		T76	1
valid_sources[0x18]	122	1		T41	1		T76	1		T53	2
valid_sources[0x19]	58	1		T142	3		T149	1		T150	1
valid_sources[0x1a]	78	1		T48	2		T41	1		T75	1
valid_sources[0x1b]	45	1		T50	1		T43	1		T75	2
valid_sources[0x1c]	79	1		T40	1		T75	1		T53	3
valid_sources[0x1d]	67	1		T40	1		T41	2		T43	3
valid_sources[0x1e]	93	1		T26	1		T151	1		T144	4
valid_sources[0x1f]	92	1		T76	3		T53	1		T77	1
valid_sources[0x20]	53	1		T75	2		T76	1		T77	1
valid_sources[0x21]	48	1		T75	3		T76	1		T53	1
valid_sources[0x22]	52	1		T69	1		T75	3		T77	3
valid_sources[0x23]	45	1		T113	1		T40	1		T76	3
valid_sources[0x24]	132	1		T40	2		T43	1		T75	1
valid_sources[0x25]	99	1		T26	1		T138	1		T152	2
valid_sources[0x26]	50	1		T69	1		T153	1		T40	1
valid_sources[0x27]	383	1		T154	1		T150	1		T75	1
valid_sources[0x28]	63	1		T44	2		T43	8		T76	1
valid_sources[0x29]	125	1		T48	1		T50	1		T75	4
valid_sources[0x2a]	114	1		T40	1		T75	1		T76	6
valid_sources[0x2b]	92	1		T43	1		T75	3		T51	2
valid_sources[0x2c]	47	1		T50	1		T151	1		T75	2
valid_sources[0x2d]	45	1		T43	3		T75	2		T80	1
valid_sources[0x2e]	68	1		T43	3		T75	1		T76	5
valid_sources[0x2f]	88	1		T111	3		T75	2		T76	1
valid_sources[0x30]	58	1		T75	3		T53	5		T77	3
valid_sources[0x31]	43	1		T113	1		T141	1		T76	1
valid_sources[0x32]	55	1		T113	1		T141	1		T147	1
valid_sources[0x33]	61	1		T147	1		T75	3		T51	1
valid_sources[0x34]	69	1		T138	1		T155	1		T41	2
valid_sources[0x35]	106	1		T64	1		T43	4		T75	2
valid_sources[0x36]	106	1		T75	4		T53	4		T77	2
valid_sources[0x37]	64	1		T156	1		T39	1		T40	1
valid_sources[0x38]	66	1		T46	1		T41	1		T76	5
valid_sources[0x39]	60	1		T75	1		T52	23		T53	1
valid_sources[0x3a]	44	1		T138	1		T41	1		T75	8
valid_sources[0x3b]	40	1		T43	5		T75	1		T76	1
valid_sources[0x3c]	62	1		T41	1		T76	1		T77	1
valid_sources[0x3d]	81	1		T75	5		T51	2		T53	2
valid_sources[0x3e]	47	1		T43	2		T75	1		T76	6
valid_sources[0x3f]	107	1		T69	1		T154	1		T39	1
valid_sources[0x40]	42	1		T151	2		T41	1		T76	2
valid_sources[0x41]	38	1		T75	1		T53	4		T36	1
valid_sources[0x42]	53	1		T153	1		T75	1		T53	8
valid_sources[0x43]	51	1		T48	1		T69	1		T41	2
valid_sources[0x44]	38	1		T41	1		T75	2		T51	1
valid_sources[0x45]	87	1		T157	3		T53	1		T77	4
valid_sources[0x46]	57	1		T113	1		T151	3		T76	2
valid_sources[0x47]	68	1		T46	1		T158	6		T76	1
valid_sources[0x48]	58	1		T69	1		T75	3		T76	12
valid_sources[0x49]	76	1		T49	1		T150	1		T43	2
valid_sources[0x4a]	48	1		T152	2		T75	1		T77	1
valid_sources[0x4b]	343	1		T48	1		T76	2		T77	1
valid_sources[0x4c]	90	1		T159	1		T150	1		T41	1
valid_sources[0x4d]	53	1		T160	1		T139	2		T75	2
valid_sources[0x4e]	59	1		T75	2		T53	7		T77	1
valid_sources[0x4f]	36	1		T40	1		T41	1		T59	1
valid_sources[0x50]	191	1		T44	2		T48	2		T155	2
valid_sources[0x51]	118	1		T110	1		T154	1		T58	51
valid_sources[0x52]	47	1		T43	3		T75	3		T77	1
valid_sources[0x53]	87	1		T48	2		T141	1		T142	1
valid_sources[0x54]	117	1		T39	1		T43	1		T75	3
valid_sources[0x55]	58	1		T39	3		T43	2		T75	2
valid_sources[0x56]	70	1		T39	1		T40	2		T75	4
valid_sources[0x57]	72	1		T31	1		T76	2		T53	3
valid_sources[0x58]	87	1		T113	1		T138	1		T40	1
valid_sources[0x59]	63	1		T40	1		T75	2		T76	4
valid_sources[0x5a]	48	1		T76	2		T53	6		T143	1
valid_sources[0x5b]	68	1		T50	1		T75	2		T76	1
valid_sources[0x5c]	65	1		T39	2		T58	3		T43	4
valid_sources[0x5d]	142	1		T110	1		T154	1		T145	2
valid_sources[0x5e]	47	1		T40	2		T75	6		T76	2
valid_sources[0x5f]	63	1		T75	2		T76	1		T77	1
valid_sources[0x60]	82	1		T39	3		T43	2		T75	1
valid_sources[0x61]	64	1		T75	5		T51	1		T53	7
valid_sources[0x62]	96	1		T50	1		T69	1		T113	1
valid_sources[0x63]	52	1		T53	2		T77	1		T143	1
valid_sources[0x64]	135	1		T69	1		T41	1		T43	6
valid_sources[0x65]	146	1		T40	1		T41	2		T75	3
valid_sources[0x66]	83	1		T69	1		T75	3		T53	8
valid_sources[0x67]	53	1		T40	1		T41	1		T75	1
valid_sources[0x68]	31	1		T138	1		T39	1		T75	1
valid_sources[0x69]	67	1		T161	2		T58	10		T75	1
valid_sources[0x6a]	46	1		T113	2		T154	2		T43	2
valid_sources[0x6b]	62	1		T40	1		T76	4		T77	2
valid_sources[0x6c]	95	1		T111	1		T149	2		T159	1
valid_sources[0x6d]	70	1		T53	4		T80	1		T143	1
valid_sources[0x6e]	53	1		T40	1		T77	1		T143	2
valid_sources[0x6f]	65	1		T31	1		T142	2		T153	1
valid_sources[0x70]	71	1		T153	1		T162	1		T41	2
valid_sources[0x71]	168	1		T43	3		T75	1		T76	1
valid_sources[0x72]	105	1		T26	1		T48	1		T110	1
valid_sources[0x73]	42	1		T151	2		T76	4		T77	2
valid_sources[0x74]	289	1		T138	1		T163	10		T40	1
valid_sources[0x75]	61	1		T41	1		T76	1		T53	8
valid_sources[0x76]	70	1		T141	1		T153	1		T139	3
valid_sources[0x77]	79	1		T75	1		T76	2		T53	1
valid_sources[0x78]	62	1		T39	1		T41	1		T75	1
valid_sources[0x79]	65	1		T164	11		T41	1		T75	3
valid_sources[0x7a]	36	1		T75	1		T53	1		T77	1
valid_sources[0x7b]	58	1		T159	1		T40	1		T43	4
valid_sources[0x7c]	87	1		T31	1		T141	1		T41	1
valid_sources[0x7d]	54	1		T158	6		T159	3		T153	1
valid_sources[0x7e]	95	1		T50	1		T43	1		T75	3
valid_sources[0x7f]	53	1		T40	1		T77	2		T165	18
valid_sources[0x80]	105	1		T110	1		T43	1		T75	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5344

1

T39

9

T40

25

T41

22

values[0x0]

all_enables

biggest_size

6987

1

T26

2

T31

1

T32

2

values[0x1]

all_enables

biggest_size

7082

1

T26

1

T32

1

T46

1