SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 664 | 664 | 0 | 0 |
OutputsKnown_A | 106845376 | 106680632 | 0 | 0 |
gen_flops.OutputDelay_A | 53422688 | 53336584 | 0 | 996 |
gen_no_flops.OutputDelay_A | 53422688 | 53340316 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 664 | 664 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T12 | 4 | 4 | 0 | 0 |
T14 | 4 | 4 | 0 | 0 |
T26 | 4 | 4 | 0 | 0 |
T27 | 4 | 4 | 0 | 0 |
T28 | 4 | 4 | 0 | 0 |
T29 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 106845376 | 106680632 | 0 | 0 |
T1 | 261824 | 261520 | 0 | 0 |
T2 | 1823968 | 1817992 | 0 | 0 |
T3 | 425912 | 425624 | 0 | 0 |
T4 | 329896 | 328904 | 0 | 0 |
T12 | 361988 | 361716 | 0 | 0 |
T14 | 671000 | 667788 | 0 | 0 |
T26 | 4312 | 4004 | 0 | 0 |
T27 | 56592 | 56264 | 0 | 0 |
T28 | 442676 | 442476 | 0 | 0 |
T29 | 893372 | 893116 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53422688 | 53336584 | 0 | 996 |
T1 | 130912 | 130754 | 0 | 6 |
T2 | 911984 | 908870 | 0 | 6 |
T3 | 212956 | 212806 | 0 | 6 |
T4 | 164948 | 164428 | 0 | 6 |
T12 | 180994 | 180852 | 0 | 6 |
T14 | 335500 | 333822 | 0 | 6 |
T26 | 2156 | 1996 | 0 | 6 |
T27 | 28296 | 28126 | 0 | 6 |
T28 | 221338 | 221232 | 0 | 6 |
T29 | 446686 | 446552 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53422688 | 53340316 | 0 | 0 |
T1 | 130912 | 130760 | 0 | 0 |
T2 | 911984 | 908996 | 0 | 0 |
T3 | 212956 | 212812 | 0 | 0 |
T4 | 164948 | 164452 | 0 | 0 |
T12 | 180994 | 180858 | 0 | 0 |
T14 | 335500 | 333894 | 0 | 0 |
T26 | 2156 | 2002 | 0 | 0 |
T27 | 28296 | 28132 | 0 | 0 |
T28 | 221338 | 221238 | 0 | 0 |
T29 | 446686 | 446558 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 26711344 | 26670158 | 0 | 0 |
gen_flops.OutputDelay_A | 26711344 | 26668292 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26670158 | 0 | 0 |
T1 | 65456 | 65380 | 0 | 0 |
T2 | 455992 | 454498 | 0 | 0 |
T3 | 106478 | 106406 | 0 | 0 |
T4 | 82474 | 82226 | 0 | 0 |
T12 | 90497 | 90429 | 0 | 0 |
T14 | 167750 | 166947 | 0 | 0 |
T26 | 1078 | 1001 | 0 | 0 |
T27 | 14148 | 14066 | 0 | 0 |
T28 | 110669 | 110619 | 0 | 0 |
T29 | 223343 | 223279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26668292 | 0 | 498 |
T1 | 65456 | 65377 | 0 | 3 |
T2 | 455992 | 454435 | 0 | 3 |
T3 | 106478 | 106403 | 0 | 3 |
T4 | 82474 | 82214 | 0 | 3 |
T12 | 90497 | 90426 | 0 | 3 |
T14 | 167750 | 166911 | 0 | 3 |
T26 | 1078 | 998 | 0 | 3 |
T27 | 14148 | 14063 | 0 | 3 |
T28 | 110669 | 110616 | 0 | 3 |
T29 | 223343 | 223276 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 26711344 | 26670158 | 0 | 0 |
gen_flops.OutputDelay_A | 26711344 | 26668292 | 0 | 498 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26670158 | 0 | 0 |
T1 | 65456 | 65380 | 0 | 0 |
T2 | 455992 | 454498 | 0 | 0 |
T3 | 106478 | 106406 | 0 | 0 |
T4 | 82474 | 82226 | 0 | 0 |
T12 | 90497 | 90429 | 0 | 0 |
T14 | 167750 | 166947 | 0 | 0 |
T26 | 1078 | 1001 | 0 | 0 |
T27 | 14148 | 14066 | 0 | 0 |
T28 | 110669 | 110619 | 0 | 0 |
T29 | 223343 | 223279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26668292 | 0 | 498 |
T1 | 65456 | 65377 | 0 | 3 |
T2 | 455992 | 454435 | 0 | 3 |
T3 | 106478 | 106403 | 0 | 3 |
T4 | 82474 | 82214 | 0 | 3 |
T12 | 90497 | 90426 | 0 | 3 |
T14 | 167750 | 166911 | 0 | 3 |
T26 | 1078 | 998 | 0 | 3 |
T27 | 14148 | 14063 | 0 | 3 |
T28 | 110669 | 110616 | 0 | 3 |
T29 | 223343 | 223276 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 26711344 | 26670158 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26711344 | 26670158 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26670158 | 0 | 0 |
T1 | 65456 | 65380 | 0 | 0 |
T2 | 455992 | 454498 | 0 | 0 |
T3 | 106478 | 106406 | 0 | 0 |
T4 | 82474 | 82226 | 0 | 0 |
T12 | 90497 | 90429 | 0 | 0 |
T14 | 167750 | 166947 | 0 | 0 |
T26 | 1078 | 1001 | 0 | 0 |
T27 | 14148 | 14066 | 0 | 0 |
T28 | 110669 | 110619 | 0 | 0 |
T29 | 223343 | 223279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26670158 | 0 | 0 |
T1 | 65456 | 65380 | 0 | 0 |
T2 | 455992 | 454498 | 0 | 0 |
T3 | 106478 | 106406 | 0 | 0 |
T4 | 82474 | 82226 | 0 | 0 |
T12 | 90497 | 90429 | 0 | 0 |
T14 | 167750 | 166947 | 0 | 0 |
T26 | 1078 | 1001 | 0 | 0 |
T27 | 14148 | 14066 | 0 | 0 |
T28 | 110669 | 110619 | 0 | 0 |
T29 | 223343 | 223279 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 166 | 166 | 0 | 0 |
OutputsKnown_A | 26711344 | 26670158 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26711344 | 26670158 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 166 | 166 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26670158 | 0 | 0 |
T1 | 65456 | 65380 | 0 | 0 |
T2 | 455992 | 454498 | 0 | 0 |
T3 | 106478 | 106406 | 0 | 0 |
T4 | 82474 | 82226 | 0 | 0 |
T12 | 90497 | 90429 | 0 | 0 |
T14 | 167750 | 166947 | 0 | 0 |
T26 | 1078 | 1001 | 0 | 0 |
T27 | 14148 | 14066 | 0 | 0 |
T28 | 110669 | 110619 | 0 | 0 |
T29 | 223343 | 223279 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26711344 | 26670158 | 0 | 0 |
T1 | 65456 | 65380 | 0 | 0 |
T2 | 455992 | 454498 | 0 | 0 |
T3 | 106478 | 106406 | 0 | 0 |
T4 | 82474 | 82226 | 0 | 0 |
T12 | 90497 | 90429 | 0 | 0 |
T14 | 167750 | 166947 | 0 | 0 |
T26 | 1078 | 1001 | 0 | 0 |
T27 | 14148 | 14066 | 0 | 0 |
T28 | 110669 | 110619 | 0 | 0 |
T29 | 223343 | 223279 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |