Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	250563	1		T9	9		T7	3		T4	1
full_word	597418	1		T9	23		T4	1		T8	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	847651	1		T9	32		T7	3		T4	2
auto[TlIntgErrCmd]	109	1		T47	3		T48	3		T49	5
auto[TlIntgErrData]	128	1		T47	3		T48	2		T49	13
auto[TlIntgErrBoth]	93	1		T47	4		T48	5		T49	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	513896	1		T9	16		T6	15		T30	80
auto[1]	334085	1		T9	16		T7	3		T4	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	211366	1		T9	9		T6	11		T19	19
auto[TlIntgErrNone]	partial	auto[1]	38888	1		T7	3		T4	1		T8	6
auto[TlIntgErrNone]	full_word	auto[0]	302363	1		T9	7		T6	4		T30	80
auto[TlIntgErrNone]	full_word	auto[1]	295034	1		T9	16		T4	1		T8	2
auto[TlIntgErrCmd]	partial	auto[0]	50	1		T47	1		T49	4		T83	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T47	2		T48	3		T49	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T85	2		T131	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T84	1		T125	1		-	-
auto[TlIntgErrData]	partial	auto[0]	70	1		T47	3		T48	2		T49	4
auto[TlIntgErrData]	partial	auto[1]	48	1		T49	7		T68	1		T83	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T49	2		T132	1		T128	2
auto[TlIntgErrData]	full_word	auto[1]	4	1		T83	1		T127	1		T126	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T47	2		T48	1		T49	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T47	1		T48	4		T49	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T128	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T47	1		T127	1		T134	1