Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 218072 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 596087 1 T9 23 T4 1 T8 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 512249 1 T9 16 T6 15 T30 80
values[0x0] 149241 1 T9 8 T7 1 T4 1
values[0x1] 152669 1 T9 8 T7 2 T4 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 166544 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 647615 1 T9 24 T7 1 T4 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2826 1 T32 3 T31 1 T20 1
valid_sources[0x01] 3075 1 T5 2 T14 1 T32 1
valid_sources[0x02] 3136 1 T27 2 T26 1 T19 1
valid_sources[0x03] 4440 1 T32 2 T31 1 T87 1
valid_sources[0x04] 2674 1 T13 1 T137 1 T31 1
valid_sources[0x05] 2898 1 T26 1 T31 1 T87 1
valid_sources[0x06] 2671 1 T20 1 T101 110 T48 8
valid_sources[0x07] 3047 1 T71 1 T101 144 T53 9
valid_sources[0x08] 3113 1 T13 2 T87 1 T101 136
valid_sources[0x09] 3081 1 T30 9 T87 1 T71 1
valid_sources[0x0a] 3108 1 T31 1 T101 107 T82 1
valid_sources[0x0b] 2674 1 T26 1 T13 1 T31 1
valid_sources[0x0c] 3263 1 T20 1 T87 1 T50 1
valid_sources[0x0d] 3174 1 T26 1 T50 2 T101 101
valid_sources[0x0e] 2921 1 T31 2 T87 5 T50 2
valid_sources[0x0f] 4409 1 T9 32 T50 1 T101 76
valid_sources[0x10] 3724 1 T19 2 T31 1 T101 127
valid_sources[0x11] 3668 1 T137 2 T31 1 T50 1
valid_sources[0x12] 2966 1 T13 1 T32 1 T71 1
valid_sources[0x13] 4835 1 T31 1 T87 1 T50 1
valid_sources[0x14] 3020 1 T32 2 T50 1 T101 111
valid_sources[0x15] 2520 1 T12 3 T71 1 T50 1
valid_sources[0x16] 2994 1 T12 1 T71 1 T50 1
valid_sources[0x17] 2373 1 T5 2 T30 12 T12 3
valid_sources[0x18] 2977 1 T87 1 T50 1 T101 80
valid_sources[0x19] 2980 1 T14 1 T12 3 T26 1
valid_sources[0x1a] 3004 1 T20 1 T87 2 T50 1
valid_sources[0x1b] 2746 1 T31 1 T20 1 T87 1
valid_sources[0x1c] 3007 1 T7 1 T5 1 T19 2
valid_sources[0x1d] 3032 1 T137 2 T101 67 T82 2
valid_sources[0x1e] 3749 1 T5 1 T31 1 T71 1
valid_sources[0x1f] 2423 1 T8 1 T14 1 T87 1
valid_sources[0x20] 2789 1 T5 2 T20 1 T101 111
valid_sources[0x21] 3039 1 T5 1 T30 17 T101 120
valid_sources[0x22] 2619 1 T20 1 T71 2 T50 2
valid_sources[0x23] 3099 1 T32 1 T101 113 T53 2
valid_sources[0x24] 2999 1 T87 2 T101 93 T53 7
valid_sources[0x25] 2762 1 T5 1 T50 2 T101 144
valid_sources[0x26] 2618 1 T87 1 T138 2 T71 1
valid_sources[0x27] 3013 1 T26 1 T87 1 T71 1
valid_sources[0x28] 3057 1 T31 1 T50 1 T101 130
valid_sources[0x29] 3778 1 T19 4 T87 2 T71 2
valid_sources[0x2a] 2817 1 T137 1 T101 118 T53 6
valid_sources[0x2b] 3218 1 T14 2 T34 1 T71 3
valid_sources[0x2c] 3514 1 T32 1 T31 1 T87 3
valid_sources[0x2d] 2928 1 T14 1 T31 1 T71 1
valid_sources[0x2e] 3103 1 T8 3 T31 1 T20 1
valid_sources[0x2f] 2931 1 T26 1 T87 1 T71 1
valid_sources[0x30] 3209 1 T31 1 T87 2 T101 148
valid_sources[0x31] 3118 1 T12 1 T20 1 T87 1
valid_sources[0x32] 3401 1 T5 1 T138 1 T50 1
valid_sources[0x33] 3048 1 T25 1 T137 3 T71 1
valid_sources[0x34] 3451 1 T71 2 T50 1 T101 102
valid_sources[0x35] 3024 1 T19 1 T32 1 T20 1
valid_sources[0x36] 3000 1 T5 1 T87 1 T101 72
valid_sources[0x37] 3817 1 T137 2 T20 1 T50 1
valid_sources[0x38] 3693 1 T31 2 T20 1 T71 4
valid_sources[0x39] 3097 1 T5 1 T101 97 T82 2
valid_sources[0x3a] 3734 1 T5 1 T31 1 T20 2
valid_sources[0x3b] 2886 1 T41 4 T31 2 T20 1
valid_sources[0x3c] 3204 1 T50 2 T101 88 T82 1
valid_sources[0x3d] 3675 1 T101 153 T53 6 T48 18
valid_sources[0x3e] 2909 1 T87 1 T50 4 T101 87
valid_sources[0x3f] 3040 1 T19 3 T31 1 T71 1
valid_sources[0x40] 2743 1 T8 3 T13 1 T20 1
valid_sources[0x41] 2730 1 T137 2 T101 89 T48 1
valid_sources[0x42] 3291 1 T5 1 T26 1 T137 1
valid_sources[0x43] 3047 1 T25 2 T101 121 T48 42
valid_sources[0x44] 2815 1 T26 1 T71 1 T50 5
valid_sources[0x45] 3052 1 T26 1 T31 1 T50 3
valid_sources[0x46] 2672 1 T101 94 T53 2 T48 7
valid_sources[0x47] 3248 1 T32 1 T50 2 T101 88
valid_sources[0x48] 3352 1 T50 1 T101 95 T53 8
valid_sources[0x49] 3251 1 T14 1 T87 2 T101 144
valid_sources[0x4a] 3940 1 T5 1 T26 1 T13 2
valid_sources[0x4b] 3398 1 T31 1 T101 115 T65 8
valid_sources[0x4c] 2581 1 T34 1 T101 76 T53 4
valid_sources[0x4d] 3254 1 T5 2 T32 1 T33 1
valid_sources[0x4e] 2765 1 T26 1 T137 1 T87 1
valid_sources[0x4f] 3198 1 T26 1 T87 1 T101 127
valid_sources[0x50] 3172 1 T26 1 T101 87 T53 5
valid_sources[0x51] 3174 1 T32 1 T50 4 T101 114
valid_sources[0x52] 3421 1 T31 1 T87 3 T50 1
valid_sources[0x53] 2789 1 T137 1 T31 1 T87 1
valid_sources[0x54] 3055 1 T5 2 T19 1 T71 3
valid_sources[0x55] 2871 1 T20 1 T50 1 T101 96
valid_sources[0x56] 2714 1 T26 1 T13 2 T101 127
valid_sources[0x57] 2688 1 T13 1 T32 1 T50 1
valid_sources[0x58] 3488 1 T12 2 T19 2 T50 2
valid_sources[0x59] 3259 1 T71 1 T50 1 T101 108
valid_sources[0x5a] 3027 1 T137 4 T32 1 T31 1
valid_sources[0x5b] 2923 1 T31 3 T50 1 T101 93
valid_sources[0x5c] 2846 1 T12 1 T13 2 T101 97
valid_sources[0x5d] 3993 1 T32 2 T31 1 T50 1
valid_sources[0x5e] 2617 1 T26 1 T20 1 T87 1
valid_sources[0x5f] 2518 1 T26 1 T20 1 T138 1
valid_sources[0x60] 3351 1 T5 1 T13 1 T87 4
valid_sources[0x61] 3377 1 T5 1 T26 1 T50 1
valid_sources[0x62] 3243 1 T8 1 T15 6 T19 5
valid_sources[0x63] 3080 1 T20 2 T50 1 T101 103
valid_sources[0x64] 4072 1 T5 1 T26 2 T19 1
valid_sources[0x65] 4316 1 T139 4 T87 1 T50 1
valid_sources[0x66] 2826 1 T5 1 T50 1 T101 99
valid_sources[0x67] 3569 1 T7 1 T12 1 T87 1
valid_sources[0x68] 3085 1 T71 3 T50 1 T101 92
valid_sources[0x69] 3456 1 T31 1 T20 1 T71 1
valid_sources[0x6a] 3088 1 T14 1 T26 1 T13 1
valid_sources[0x6b] 3927 1 T5 1 T26 2 T19 1
valid_sources[0x6c] 3354 1 T5 1 T30 7 T31 1
valid_sources[0x6d] 2736 1 T50 1 T101 103 T48 54
valid_sources[0x6e] 3218 1 T13 2 T19 1 T71 1
valid_sources[0x6f] 3386 1 T32 1 T20 1 T87 1
valid_sources[0x70] 2939 1 T20 1 T101 104 T48 42
valid_sources[0x71] 3310 1 T87 1 T71 1 T50 4
valid_sources[0x72] 2515 1 T101 110 T53 3 T48 9
valid_sources[0x73] 2986 1 T5 2 T6 148 T71 2
valid_sources[0x74] 3911 1 T20 2 T71 1 T50 3
valid_sources[0x75] 3260 1 T13 2 T20 1 T50 1
valid_sources[0x76] 2877 1 T32 2 T20 1 T50 2
valid_sources[0x77] 2699 1 T13 1 T20 1 T87 2
valid_sources[0x78] 3503 1 T13 1 T32 1 T101 114
valid_sources[0x79] 3360 1 T101 79 T53 5 T48 32
valid_sources[0x7a] 2980 1 T26 1 T50 1 T101 140
valid_sources[0x7b] 2759 1 T12 4 T87 3 T50 1
valid_sources[0x7c] 3026 1 T71 1 T50 3 T101 100
valid_sources[0x7d] 3279 1 T30 4 T15 2 T87 1
valid_sources[0x7e] 3619 1 T32 1 T87 1 T50 1
valid_sources[0x7f] 3893 1 T31 1 T87 1 T71 1
valid_sources[0x80] 3064 1 T5 1 T101 70 T82 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 302204 1 T9 7 T6 4 T30 80
values[0x0] all_enables biggest_size 147349 1 T9 8 T5 10 T6 22
values[0x1] all_enables biggest_size 146534 1 T9 8 T4 1 T8 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2383 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 19165 1 T39 1 T42 1 T43 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 6547 1 T50 14 T47 16 T53 1
values[0x0] 7434 1 T39 6 T42 6 T43 5
values[0x1] 7567 1 T39 4 T42 6 T43 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1826 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 19722 1 T39 2 T42 2 T43 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 77 1 T140 1 T50 1 T51 6
valid_sources[0x01] 50 1 T72 2 T51 1 T78 1
valid_sources[0x02] 164 1 T50 1 T72 1 T82 2
valid_sources[0x03] 79 1 T141 1 T50 1 T72 3
valid_sources[0x04] 124 1 T140 1 T50 1 T72 4
valid_sources[0x05] 95 1 T72 3 T51 2 T68 4
valid_sources[0x06] 81 1 T50 1 T72 1 T51 2
valid_sources[0x07] 56 1 T50 1 T72 2 T82 2
valid_sources[0x08] 56 1 T50 1 T72 1 T51 4
valid_sources[0x09] 81 1 T142 1 T50 1 T72 2
valid_sources[0x0a] 63 1 T50 1 T72 8 T51 1
valid_sources[0x0b] 83 1 T140 1 T143 1 T72 4
valid_sources[0x0c] 68 1 T72 3 T82 15 T95 1
valid_sources[0x0d] 130 1 T144 1 T145 1 T72 2
valid_sources[0x0e] 98 1 T146 3 T147 1 T82 3
valid_sources[0x0f] 153 1 T51 7 T52 1 T95 1
valid_sources[0x10] 80 1 T72 2 T51 2 T52 1
valid_sources[0x11] 76 1 T50 2 T72 2 T51 4
valid_sources[0x12] 93 1 T59 1 T60 5 T82 1
valid_sources[0x13] 62 1 T148 3 T149 1 T50 1
valid_sources[0x14] 61 1 T150 2 T72 2 T48 1
valid_sources[0x15] 400 1 T151 1 T72 1 T82 5
valid_sources[0x16] 54 1 T147 1 T72 5 T51 2
valid_sources[0x17] 142 1 T72 7 T51 1 T84 2
valid_sources[0x18] 138 1 T50 1 T101 1 T47 29
valid_sources[0x19] 61 1 T51 3 T95 2 T78 1
valid_sources[0x1a] 87 1 T72 4 T48 2 T51 3
valid_sources[0x1b] 46 1 T72 1 T82 1 T95 2
valid_sources[0x1c] 71 1 T50 2 T72 2 T82 9
valid_sources[0x1d] 80 1 T43 1 T151 1 T72 1
valid_sources[0x1e] 52 1 T152 2 T72 1 T51 2
valid_sources[0x1f] 56 1 T153 1 T72 1 T51 4
valid_sources[0x20] 87 1 T72 1 T82 1 T51 2
valid_sources[0x21] 50 1 T143 1 T72 1 T82 3
valid_sources[0x22] 74 1 T72 4 T82 1 T51 2
valid_sources[0x23] 38 1 T52 1 T83 4 T95 1
valid_sources[0x24] 56 1 T72 2 T82 2 T48 1
valid_sources[0x25] 63 1 T143 2 T53 1 T72 4
valid_sources[0x26] 214 1 T43 1 T154 1 T72 2
valid_sources[0x27] 78 1 T155 1 T156 1 T72 2
valid_sources[0x28] 138 1 T143 1 T53 1 T72 1
valid_sources[0x29] 46 1 T154 2 T72 2 T82 1
valid_sources[0x2a] 100 1 T72 3 T51 4 T84 1
valid_sources[0x2b] 95 1 T141 1 T152 1 T72 2
valid_sources[0x2c] 44 1 T72 2 T51 1 T95 2
valid_sources[0x2d] 178 1 T43 1 T82 1 T51 2
valid_sources[0x2e] 57 1 T156 1 T72 1 T82 1
valid_sources[0x2f] 94 1 T72 2 T51 8 T52 1
valid_sources[0x30] 52 1 T72 2 T51 3 T95 2
valid_sources[0x31] 42 1 T39 1 T156 1 T72 1
valid_sources[0x32] 59 1 T151 1 T149 1 T50 1
valid_sources[0x33] 55 1 T150 3 T156 1 T50 2
valid_sources[0x34] 71 1 T86 2 T157 1 T50 1
valid_sources[0x35] 170 1 T156 1 T72 1 T82 1
valid_sources[0x36] 90 1 T140 1 T72 1 T82 2
valid_sources[0x37] 117 1 T59 1 T150 1 T72 2
valid_sources[0x38] 63 1 T39 1 T72 2 T82 2
valid_sources[0x39] 71 1 T158 9 T72 1 T82 1
valid_sources[0x3a] 52 1 T57 3 T51 1 T52 1
valid_sources[0x3b] 92 1 T72 1 T82 8 T65 1
valid_sources[0x3c] 54 1 T143 1 T82 1 T51 3
valid_sources[0x3d] 43 1 T55 4 T156 1 T151 2
valid_sources[0x3e] 55 1 T149 1 T82 1 T51 3
valid_sources[0x3f] 73 1 T157 3 T82 1 T51 4
valid_sources[0x40] 52 1 T50 1 T72 3 T48 1
valid_sources[0x41] 76 1 T72 3 T82 14 T51 2
valid_sources[0x42] 70 1 T150 1 T154 1 T72 3
valid_sources[0x43] 95 1 T72 2 T82 3 T51 3
valid_sources[0x44] 89 1 T157 1 T72 5 T82 1
valid_sources[0x45] 78 1 T51 1 T52 1 T85 1
valid_sources[0x46] 71 1 T142 1 T156 1 T151 1
valid_sources[0x47] 53 1 T59 1 T50 1 T72 1
valid_sources[0x48] 179 1 T72 2 T51 2 T69 138
valid_sources[0x49] 51 1 T56 1 T72 5 T82 1
valid_sources[0x4a] 49 1 T72 2 T51 4 T78 1
valid_sources[0x4b] 217 1 T59 2 T51 2 T95 1
valid_sources[0x4c] 56 1 T56 1 T50 1 T72 1
valid_sources[0x4d] 49 1 T72 1 T51 1 T95 2
valid_sources[0x4e] 77 1 T140 1 T154 1 T72 3
valid_sources[0x4f] 170 1 T82 1 T51 2 T52 1
valid_sources[0x50] 45 1 T149 1 T51 1 T95 3
valid_sources[0x51] 43 1 T50 1 T72 3 T51 5
valid_sources[0x52] 61 1 T50 1 T72 2 T48 1
valid_sources[0x53] 56 1 T72 1 T51 1 T135 8
valid_sources[0x54] 43 1 T156 1 T51 2 T135 4
valid_sources[0x55] 61 1 T51 1 T84 1 T135 2
valid_sources[0x56] 113 1 T72 2 T51 1 T95 2
valid_sources[0x57] 150 1 T156 1 T159 5 T51 2
valid_sources[0x58] 117 1 T160 1 T72 4 T51 1
valid_sources[0x59] 85 1 T156 1 T72 3 T82 1
valid_sources[0x5a] 75 1 T60 1 T50 2 T82 2
valid_sources[0x5b] 78 1 T140 1 T72 5 T51 1
valid_sources[0x5c] 54 1 T50 1 T72 1 T51 2
valid_sources[0x5d] 46 1 T39 1 T140 1 T72 4
valid_sources[0x5e] 66 1 T72 1 T82 2 T65 1
valid_sources[0x5f] 73 1 T146 7 T72 2 T52 1
valid_sources[0x60] 215 1 T157 11 T72 1 T82 1
valid_sources[0x61] 82 1 T145 2 T72 1 T52 1
valid_sources[0x62] 102 1 T150 1 T72 2 T51 1
valid_sources[0x63] 44 1 T140 1 T72 2 T82 1
valid_sources[0x64] 41 1 T72 2 T82 2 T51 1
valid_sources[0x65] 96 1 T59 2 T156 1 T82 3
valid_sources[0x66] 54 1 T72 3 T82 2 T48 1
valid_sources[0x67] 73 1 T72 2 T66 1 T95 2
valid_sources[0x68] 115 1 T59 1 T140 1 T72 2
valid_sources[0x69] 31 1 T50 1 T82 1 T161 1
valid_sources[0x6a] 64 1 T156 1 T153 1 T72 2
valid_sources[0x6b] 53 1 T162 3 T72 5 T161 1
valid_sources[0x6c] 70 1 T72 2 T51 5 T84 1
valid_sources[0x6d] 213 1 T43 1 T156 1 T50 2
valid_sources[0x6e] 103 1 T43 1 T59 1 T154 1
valid_sources[0x6f] 114 1 T50 1 T51 2 T67 1
valid_sources[0x70] 58 1 T56 1 T72 2 T51 2
valid_sources[0x71] 82 1 T48 1 T52 2 T95 1
valid_sources[0x72] 65 1 T56 1 T72 3 T51 4
valid_sources[0x73] 99 1 T48 1 T51 2 T52 1
valid_sources[0x74] 109 1 T59 1 T160 2 T72 4
valid_sources[0x75] 57 1 T72 7 T65 1 T51 1
valid_sources[0x76] 67 1 T142 1 T143 1 T72 5
valid_sources[0x77] 80 1 T148 1 T163 3 T151 1
valid_sources[0x78] 125 1 T50 1 T72 3 T51 1
valid_sources[0x79] 49 1 T59 1 T72 2 T135 3
valid_sources[0x7a] 59 1 T164 6 T50 1 T72 3
valid_sources[0x7b] 58 1 T50 1 T72 4 T82 1
valid_sources[0x7c] 64 1 T72 3 T82 1 T51 3
valid_sources[0x7d] 113 1 T153 2 T160 2 T72 2
valid_sources[0x7e] 75 1 T152 1 T50 1 T72 2
valid_sources[0x7f] 31 1 T140 1 T51 1 T78 1
valid_sources[0x80] 105 1 T58 11 T152 1 T162 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 5408 1 T50 14 T47 2 T72 133
values[0x0] all_enables biggest_size 6932 1 T39 1 T43 1 T56 2
values[0x1] all_enables biggest_size 6825 1 T42 1 T56 2 T57 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%