Module Definition
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Module : dm_mem
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.83 80.00 54.84 100.00 72.50

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dm_top.i_dm_mem 76.83 80.00 54.84 100.00 72.50



Module Instance : tb.dut.u_dm_top.i_dm_mem

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.83 80.00 54.84 100.00 72.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.55 80.71 56.25 100.00 73.26


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_dm_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rom_snd_scratch.i_debug_rom 94.44 100.00 100.00 83.33


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : dm_mem
Line No.TotalCoveredPercent
TOTAL19015280.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13811100.00
ALWAYS1453737100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22811100.00
ALWAYS236484389.58
ROUTINE37211100.00
ALWAYS385151280.00
ALWAYS40833100.00
CONT_ASSIGN41511100.00
ALWAYS419542444.44
CONT_ASSIGN55411100.00
ALWAYS58499100.00
ALWAYS59855100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
109 1 1
110 1 1
117 1 1
118 1 1
119 1 1
121 1 1
122 1 1
123 1 1
124 1 1
132 1 1
133 1 1
134 1 1
135 1 1
138 1 1
145 1 1
146 1 1
147 1 1
148 1 1
149 1 1
150 1 1
152 1 1
154 1 1
155 1 1
157 1 1
158 1 1
160 1 1
161 1 1
MISSING_ELSE
165 1 1
167 1 1
MISSING_ELSE
173 1 1
174 1 1
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
185 1 1
MISSING_ELSE
190 1 1
191 1 1
193 1 1
194 1 1
MISSING_ELSE
203 1 1
204 1 1
205 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
MISSING_ELSE
213 1 1
215 1 1
216 1 1
217 1 1
MISSING_ELSE
223 1 1
228 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1
244 1 1
245 1 1
246 1 1
247 1 1
250 1 1
251 1 1
MISSING_ELSE
254 1 1
256 1 1
257 1 1
259 1 1
260 1 1
263 1 1
267 1 1
269 1 1
272 1 1
275 1 1
276 1 1
277 1 1
278 1 1
279 1 1
280 1 1
282 0 1
283 0 1
==> MISSING_ELSE
286 1 1
==> MISSING_ELSE
MISSING_ELSE
298 1 1
302 1 1
303 1 1
MISSING_ELSE
307 1 1
310 1 1
312 0 1
315 1 1
==> MISSING_ELSE
321 1 1
331 0 1
338 0 1
344 1 1
346 1 1
==> MISSING_ELSE
348 1 1
353 1 1
MISSING_ELSE
360 1 1
362 1 1
363 1 1
MISSING_ELSE
366 1 1
372 1 1
385 1 1
386 1 1
387 1 1
388 1 1
389 1 1
390 1 1
391 1 1
392 1 1
393 1 1
394 0 1
395 0 1
396 1 1
397 1 1
401 1 1
402 0 1
MISSING_ELSE
MISSING_ELSE
408 1 1
409 1 1
411 1 1
415 1 1
419 1 1
422 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
430 1 1
431 1 1
432 1 1
433 1 1
434 1 1
437 1 1
442 1 1
444 1 1
446 1 1
447 0 1
448 0 1
451 1 1
454 0 1
456 0 1
458 0 1
460 0 1
462 1 1
464 1 1
465 0 1
468 1 1
475 0 1
477 0 1
479 0 1
481 0 1
483 1 1
485 0 1
489 0 1
490 0 1
491 0 1
494 0 1
497 0 1
499 0 1
501 0 1
503 0 1
505 0 1
507 0 1
508 0 1
511 0 1
518 0 1
520 0 1
522 0 1
524 0 1
526 1 1
530 0 1
531 0 1
MISSING_ELSE
538 1 1
540 1 1
MISSING_ELSE
554 1 1
584 1 1
585 1 1
586 1 1
587 1 1
588 1 1
590 1 1
591 1 1
592 1 1
593 1 1
598 1 1
599 1 1
600 1 1
602 1 1
603 1 1


Cond Coverage for Module : dm_mem
TotalCoveredPercent
Conditions623454.84
Logical623454.84
Non-Logical00
Event00

 LINE       155
 EXPRESSION (cmd_valid_i && halted_q_aligned[hartsel] && ((!unsupported_command)))
             -----1-----    ------------2------------    ------------3-----------
-1--2--3-StatusTests
011CoveredT7,T4,T8
101CoveredT22,T29
110CoveredT6,T25,T26
111CoveredT7,T4,T5

 LINE       165
 EXPRESSION (resumereq_aligned[hartsel] && ((!resuming_q_aligned[hartsel])) && ((!haltreq_aligned[hartsel])) && halted_q_aligned[hartsel])
             -------------1------------    ----------------2---------------    --------------3--------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT4,T5,T6
1011Not Covered
1101CoveredT6,T14,T15
1110CoveredT6,T14,T15
1111CoveredT6,T14,T15

 LINE       203
 EXPRESSION (unsupported_command && cmd_valid_i)
             ---------1---------    -----2-----
-1--2-StatusTests
01CoveredT7,T4,T22
10CoveredT24,T10,T6
11CoveredT24,T10,T6

 LINE       223
 EXPRESSION (fwd_rom_q ? rom_rdata : rdata_q)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T31

 LINE       228
 EXPRESSION (word_enable32_q ? word_mux[32+:32] : word_mux[0+:32])
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T24,T9

 LINE       277
 EXPRESSION ((addr_i[(DbgAddressBits - 1):2] - DataBaseAddr[(DbgAddressBits - 1):2]) == dc)
            ---------------------------------------1---------------------------------------
-1-StatusTests
0CoveredT9,T27,T19
1CoveredT9,T27,T19

 LINE       310
 EXPRESSION ((cmd_i.cmdtype == AccessRegister) && ((!ac_ar.transfer)) && ac_ar.postexec)
             ----------------1----------------    ---------2---------    -------3------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT6,T32,T33
111Not Covered

 LINE       310
 SUB-EXPRESSION (cmd_i.cmdtype == AccessRegister)
                ----------------1----------------
-1-StatusTests
0Not Covered
1CoveredT6,T32,T33

 LINE       344
 EXPRESSION (({addr_i[(DbgAddressBits - 1):3], 3'b0} - FlagsBaseAddr[(DbgAddressBits - 1):0]) == (12'(hartsel) & {{(DbgAddressBits - 3) {1'b1}}, 3'b0}))
            ----------------------------------------------------------------------1---------------------------------------------------------------------
-1-StatusTests
0Not Covered
1CoveredT6,T32,T33

 LINE       442
 EXPRESSION ((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer && ac_ar.write)
             --------------1--------------    -------2------    -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T34
110Not Covered
111CoveredT4,T5,T12

 LINE       446
 EXPRESSION (ac_ar.regno[15:14] != '0)
            -------------1------------
-1-StatusTests
0CoveredT4,T5,T12
1Not Covered

 LINE       451
 EXPRESSION (HasSndScratch && ac_ar.regno[12] && ((!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))
             ------1------    -------2-------    ---------3---------    -------------4-------------
-1--2--3--4-StatusTests
-011Not Covered
-101Not Covered
-110CoveredT4,T5,T12
-111Not Covered

 LINE       451
 SUB-EXPRESSION (ac_ar.regno[4:0] == 5'd10)
                -------------1-------------
-1-StatusTests
0CoveredT4,T5,T12
1Not Covered

 LINE       483
 EXPRESSION ((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer && ((!ac_ar.write)))
             --------------1--------------    -------2------    --------3-------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       489
 EXPRESSION (ac_ar.regno[15:14] != '0)
            -------------1------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       494
 EXPRESSION (HasSndScratch && ac_ar.regno[12] && ((!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))
             ------1------    -------2-------    ---------3---------    -------------4-------------
-1--2--3--4-StatusTests
-011Not Covered
-101Not Covered
-110Not Covered
-111Not Covered

 LINE       494
 SUB-EXPRESSION (ac_ar.regno[4:0] == 5'd10)
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       526
 EXPRESSION ((32'(ac_ar.aarsize) >= MaxAar) || (ac_ar.aarpostincrement == 1'b1))
             ---------------1--------------    ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       526
 SUB-EXPRESSION (ac_ar.aarpostincrement == 1'b1)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       538
 EXPRESSION (ac_ar.postexec && ((!unsupported_command)))
             -------1------    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT7,T34

 LINE       602
 EXPRESSION (SelectableHarts & halted_d)
             -------1-------   ----2---
-1--2-StatusTests
-0CoveredT1,T2,T3
-1CoveredT7,T4,T8

 LINE       603
 EXPRESSION (SelectableHarts & resuming_d)
             -------1-------   -----2----
-1--2-StatusTests
-0CoveredT1,T2,T3
-1CoveredT6,T14,T15

FSM Coverage for Module : dm_mem
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
CmdExecuting 177 Covered T6,T32,T33
Go 157 Covered T7,T4,T5
Idle 185 Covered T1,T2,T3
Resume 167 Covered T6,T14,T15


transitionsLine No.CoveredTests
CmdExecuting->Idle 194 Covered T6,T32,T33
Go->CmdExecuting 177 Covered T6,T32,T33
Go->Idle 215 Covered T5,T33
Idle->Go 157 Covered T7,T4,T5
Idle->Resume 167 Covered T6,T14,T15
Resume->Idle 185 Covered T6,T14,T15



Branch Coverage for Module : dm_mem
Line No.TotalCoveredPercent
Branches 80 58 72.50
TERNARY 223 2 2 100.00
TERNARY 228 2 2 100.00
CASE 152 12 11 91.67
IF 203 2 2 100.00
IF 208 2 2 100.00
IF 213 2 2 100.00
IF 250 2 2 100.00
IF 254 19 12 63.16
IF 360 2 2 100.00
IF 386 14 10 71.43
IF 408 2 2 100.00
CASE 437 15 5 33.33
IF 584 2 2 100.00
IF 598 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 223 (fwd_rom_q) ?

Branches:
-1-StatusTests
1 Covered T30,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 228 (word_enable32_q) ?

Branches:
-1-StatusTests
1 Covered T3,T24,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 case (state_q) -2-: 155 if (((cmd_valid_i && halted_q_aligned[hartsel]) && (!unsupported_command))) -3-: 158 if (cmd_valid_i) -4-: 165 if ((((resumereq_aligned[hartsel] && (!resuming_q_aligned[hartsel])) && (!haltreq_aligned[hartsel])) && halted_q_aligned[hartsel])) -5-: 176 if (going) -6-: 184 if (resuming_q_aligned[hartsel]) -7-: 193 if (halted_aligned[hartsel])

Branches:
-1--2--3--4--5--6--7-StatusTests
Idle 1 - - - - - Covered T7,T4,T5
Idle 0 1 - - - - Covered T24,T10,T22
Idle 0 0 - - - - Covered T1,T2,T3
Idle - - 1 - - - Covered T6,T14,T15
Idle - - 0 - - - Covered T1,T2,T3
Go - - - 1 - - Covered T6,T32,T33
Go - - - 0 - - Covered T7,T4,T5
Resume - - - - 1 - Covered T6,T14,T15
Resume - - - - 0 - Covered T6,T14,T15
CmdExecuting - - - - - 1 Covered T6,T32,T33
CmdExecuting - - - - - 0 Covered T6,T32,T33
default - - - - - - Not Covered


LineNo. Expression -1-: 203 if ((unsupported_command && cmd_valid_i))

Branches:
-1-StatusTests
1 Covered T24,T10,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 208 if (exception)

Branches:
-1-StatusTests
1 Covered T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 213 if (ndmreset_i)

Branches:
-1-StatusTests
1 Covered T9,T21,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 250 if (clear_resumeack_i)

Branches:
-1-StatusTests
1 Covered T6,T14,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 254 if (req_i) -2-: 256 if (we_i) -3-: 257 case (addr_i[(DbgAddressBits - 1):0]) -4-: 298 case (addr_i[(DbgAddressBits - 1):0]) -5-: 302 if (resumereq_wdata_aligned[wdata_hartsel]) -6-: 307 if (cmdbusy_o) -7-: 310 if ((((cmd_i.cmdtype == AccessRegister) && (!ac_ar.transfer)) && ac_ar.postexec)) -8-: 344 if ((({addr_i[(DbgAddressBits - 1):3], 3'b0} - FlagsBaseAddr[(DbgAddressBits - 1):0]) == (12'(hartsel) & {{(DbgAddressBits - 3) {1'b1}}, 3'b0})))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
1 1 HaltedAddr - - - - - Covered T7,T4,T8
1 1 GoingAddr - - - - - Covered T6,T32,T33
1 1 ResumingAddr - - - - - Covered T6,T14,T15
1 1 ExceptionAddr - - - - - Covered T4
1 1 DataBaseAddr DataEndAddr - - - - - Covered T9,T27,T19
1 1 default - - - - - Not Covered
1 0 - WhereToAddr 1 - - - Covered T6,T32,T35
1 0 - WhereToAddr 0 - - - Covered T6,T32,T33
1 0 - WhereToAddr - 1 1 - Not Covered
1 0 - WhereToAddr - 1 0 - Covered T6,T32,T33
1 0 - WhereToAddr - 0 - - Not Covered
1 0 - DataBaseAddr DataEndAddr - - - - Covered T9,T19,T20
1 0 - ProgBufBaseAddr ProgBufEndAddr - - - - Not Covered
1 0 - AbstractCmdBaseAddr AbstractCmdEndAddr - - - - Not Covered
1 0 - FlagsBaseAddr FlagsEndAddr - - - 1 Covered T6,T32,T33
1 0 - FlagsBaseAddr FlagsEndAddr - - - 0 Not Covered
1 0 - RomBaseAddr RomEndAddr - - - - Covered T30,T31
1 0 - default - - - - Not Covered
0 - - - - - - - Covered T1,T2,T3


LineNo. Expression -1-: 360 if (ndmreset_i)

Branches:
-1-StatusTests
1 Covered T9,T21,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 386 if (req_i) -2-: 387 case (addr_i[(DbgAddressBits - 1):0]) -3-: 401 if ((addr_i[($clog2(BeWidth) - 1):0] != '0))

Branches:
-1--2--3-StatusTests
1 WhereToAddr - Covered T6,T32,T33
1 HaltedAddr - Covered T7,T4,T8
1 GoingAddr - Covered T6,T32,T33
1 ResumingAddr - Covered T6,T14,T15
1 ExceptionAddr - Covered T4
1 DataBaseAddr DataEndAddr - Covered T9,T27,T19
1 ProgBufBaseAddr ProgBufEndAddr - Not Covered
1 AbstractCmdBaseAddr AbstractCmdEndAddr - Not Covered
1 FlagsBaseAddr FlagsEndAddr - Covered T6,T32,T33
1 RomBaseAddr RomEndAddr - Covered T30,T31
1 default - Not Covered
1 - 1 Not Covered
1 - 0 Covered T9,T7,T4
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 408 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 437 case (cmd_i.cmdtype) -2-: 442 if ((((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer) && ac_ar.write)) -3-: 446 if ((ac_ar.regno[15:14] != '0)) -4-: 451 if ((((HasSndScratch && ac_ar.regno[12]) && (!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))) -5-: 462 if (ac_ar.regno[12]) -6-: 464 if (ac_ar.regno[5]) -7-: 483 if ((((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer) && (!ac_ar.write))) -8-: 489 if ((ac_ar.regno[15:14] != '0)) -9-: 494 if ((((HasSndScratch && ac_ar.regno[12]) && (!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))) -10-: 505 if (ac_ar.regno[12]) -11-: 507 if (ac_ar.regno[5]) -12-: 526 if (((32'(ac_ar.aarsize) >= MaxAar) || (ac_ar.aarpostincrement == 1'b1))) -13-: 538 if ((ac_ar.postexec && (!unsupported_command)))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
AccessRegister 1 1 - - - - - - - - - - Not Covered
AccessRegister 1 0 1 - - - - - - - - - Not Covered
AccessRegister 1 0 0 1 1 - - - - - - - Not Covered
AccessRegister 1 0 0 1 0 - - - - - - - Covered T4,T5,T12
AccessRegister 1 0 0 0 - - - - - - - - Not Covered
AccessRegister 0 - - - - 1 1 - - - - - Not Covered
AccessRegister 0 - - - - 1 0 1 - - - - Not Covered
AccessRegister 0 - - - - 1 0 0 1 1 - - Not Covered
AccessRegister 0 - - - - 1 0 0 1 0 - - Not Covered
AccessRegister 0 - - - - 1 0 0 0 - - - Not Covered
AccessRegister 0 - - - - 0 - - - - 1 - Not Covered
AccessRegister 0 - - - - 0 - - - - 0 - Covered T1,T2,T3
AccessRegister - - - - - - - - - - - 1 Covered T7,T34
AccessRegister - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - Covered T24,T10,T6


LineNo. Expression -1-: 584 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 598 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%