Module Definition
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Module : tlul_adapter_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.tl_adapter_host_sba 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.tl_adapter_host_sba

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.14 100.00 100.00 75.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.97 93.33 75.86 91.19 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.93 100.00 100.00 75.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_host
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
ALWAYS13144100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
ALWAYS16600
ALWAYS17600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
95 1 1
115 1 1
117 1 1
118 1 1
119 1 1
131 1 1
132 1 1
133 1 1
134 1 1
MISSING_ELSE
140 1 1
144 1 1
148 1 1
152 1 1
166 unreachable
168 unreachable
169 unreachable
170 unreachable
171 unreachable
==> MISSING_ELSE
176 unreachable
177 unreachable
179 unreachable


Cond Coverage for Module : tlul_adapter_host
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT10,T11,T13
1CoveredT1,T2,T3

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT10,T11,T13
1CoveredT1,T2,T3

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT10,T11,T13
1CoveredT10,T11,T13

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT3,T10,T36
01CoveredT11,T14,T15
10CoveredT1,T2,T3

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T14,T15
10CoveredT11,T14,T15

Branch Coverage for Module : tlul_adapter_host
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 93 2 2 100.00
IF 131 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 93 ((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T10,T11,T13


LineNo. Expression -1-: 131 if ((!rst_ni)) -2-: 133 if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T11,T14,T15
0 0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 43906097 52289 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 43906097 52289 0 0
T7 1714 0 0 0
T10 596024 209 0 0
T11 175312 330 0 0
T13 42590 144 0 0
T14 0 137 0 0
T15 0 4329 0 0
T22 2565 0 0 0
T30 1007 0 0 0
T36 1582 0 0 0
T37 20533 0 0 0
T38 1920 0 0 0
T39 17578 104 0 0
T61 0 288 0 0
T70 0 854 0 0
T71 0 233 0 0
T86 0 53 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%