Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.97	93.33	75.86	91.19			87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	86.97	93.33	75.86	91.19			87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.97	93.33	75.86	91.19			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.78	92.68	76.55	89.19	75.64	82.89	97.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	85.28	98.68	88.16		70.00	94.57	75.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	93.27	99.00	80.90	93.33		93.10	100.00
rv_dm_regs_csr_assert	0.00						0.00
tl_adapter_host_sba	95.14	100.00	100.00	75.71		100.00	100.00
tlul_assert_device_mem	95.24	100.00				85.71	100.00
tlul_assert_device_regs	94.54	100.00				85.71	97.90
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	84.35	86.39	63.39		100.00	71.95	100.00
u_lc_en_sync	100.00	100.00				100.00	100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
u_reg_regs	94.73	93.50	93.58	93.49		93.10	100.00
u_tlul_lc_gate_rom	80.36	93.94	57.50		85.71	77.14	87.50
u_tlul_lc_gate_sba	72.24	90.15	55.00		57.14	71.43	87.50

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		15	14	93.33
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	141	1	0	0.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	412	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
109	1	1
110	1	1
115	1	1
118	1	1
141	0	1
206	1	1
207	1	1
211	1	1
294	1	1
300	1	1
302	1	1
308	1	1
309	1	1
384	1	1
412	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	29	22	75.86
Logical	29	22	75.86
Non-Logical	0	0
Event	0	0

 LINE       115
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T37,T40,T41

 LINE       118
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T17,T25

 LINE       302
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T8

 LINE       337
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T34,T35
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       412
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T17
1	0	Covered	T7,T16,T4

 LINE       428
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       428
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T34,T35
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	94	75	79.79
Total Bits	1112	1014	91.19
Total Bits 0->1	556	507	91.19
Total Bits 1->0	556	507	91.19

Ports	94	75	79.79
Port Bits	1112	1014	91.19
Port Bits 0->1	556	507	91.19
Port Bits 1->0	556	507	91.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T4,T34,T35	Yes	T4,T5,T18	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T4,T34,T35	Yes	T4,T5,T18	INPUT
scanmode_i[3:0]	No	No		No		INPUT
scan_rst_ni	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T5,T17,T25	Yes	T5,T17,T25	OUTPUT
dmactive_o	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T4,T5,T25	Yes	T7,T4,T8	OUTPUT
unavailable_i	Yes	Yes	T4,T9,T5	Yes	T4,T9,T5	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T3,T36,T11	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T36	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T2,T30,T14	Yes	T2,T30,T22	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T2,T30,T22	Yes	T2,T30,T39	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T36	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T2,T30,T14	Yes	T2,T30,T22	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T2,T30,T14	Yes	T2,T30,T14	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T36	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T2,T30,T22	Yes	T2,T30,T14	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T50,T42,T59	Yes	T69,T50,T42	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T49,T50,T55	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T48,*T69,*T49	Yes	T48,T69,T49	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T3,T36,T11	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T11,T14,T4	Yes	T11,T14,T4	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T11,T7,T13	Yes	T11,T30,T7	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T11,T14,T4	Yes	T11,T30,T13	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T11,T14,T70	Yes	T11,T30,T14	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T11,T30,T14	Yes	T11,T14,T16	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T11,T14,T70	Yes	T11,T14,T4	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T11,T30,T14	Yes	T11,T14,T4	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T11,T30,T7	Yes	T11,T7,T13	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T11,T7,T14	Yes	T11,T30,T7	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T11,T13,T14	Yes	T11,T14,T4	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T11,T30,T7	Yes	T11,T7,T14	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T7,T16,T4	Yes	T7,T16,T4	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T11,T37,T14	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T7,*T4,*T8	Yes	T7,T16,T4	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T11,T37,T7	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T7,T4,T12	Yes	T7,T16,T4	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T7,T4,T8	Yes	T7,T4,T8	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T11,T37,T14	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T7,T16,T4	Yes	T7,T16,T4	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T13	Yes	T10,T11,T13	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T11,T37	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T11,*T37,*T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T10,T11,T13	Yes	T10,T11,T13	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T10,T11,T37	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T10,T11,T13	Yes	T10,T11,T13	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T13	Yes	T10,T11,T13	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T10,T11,T37	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T10,T11,T13	Yes	T10,T11,T13	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T3,T36,T11	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T11,T39,T51	Yes	T11,T38,T7	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T13	Yes	T10,T11,T38	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T13	Yes	T3,T10,T11	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T10,T36	Yes	T10,T11,T7	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T10,T11,T13	Yes	T3,T10,T36	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T39,T71,T40	Yes	T38,T7,T39	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T39,T14,T15	Yes	T36,T7,T39	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T36,T7,T39	Yes	T38,T39,T72	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T10,T11,T13	Yes	T10,T11,T38	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T10,T11,T13	Yes	T10,T11,T13	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T11,T37,T14	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	20513535	20473311	0	0
DmactiveOKnown_A	20513535	20473311	0	0
FpvSecCmRegWeOnehotCheck_A	20513535	70	0	0
FpvSecCmRomTlLcGateFsm_A	20513535	0	0	0
FpvSecCmSbaTlLcGateFsm_A	20513535	0	0	0
JtagRspOTdoKnown_A	10726259	10725893	0	0
JtagRspOTdoOeKnown_A	10726259	10725893	0	0
NdmresetOKnown_A	20513535	20473311	0	0
RvDmLcEnDebugVal_A	20513535	20473311	0	0
TlMemAReadyKnown_A	20513535	20473311	0	0
TlMemDValidKnown_A	20513535	20473311	0	0
TlRegsAReadyKnown_A	20513535	20473311	0	0
TlRegsDValidKnown_A	20513535	20473311	0	0
TlSbaAValidKnown_A	20513535	20473311	0	0
TlSbaDReadyKnown_A	20513535	20473311	0	0
paramCheckNrHarts	161	161	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	70	0	0
T7	1714	0	0	0
T13	42590	0	0	0
T14	191868	0	0	0
T22	2565	0	0	0
T37	20533	20	0	0
T38	1920	0	0	0
T39	17578	0	0	0
T40	0	10	0	0
T41	0	10	0	0
T51	1172	0	0	0
T52	1181	0	0	0
T70	439008	0	0	0
T73	0	20	0	0
T74	0	10	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10726259	10725893	0	0
T1	109	109	0	0
T2	155	155	0	0
T3	116	116	0	0
T7	2445	2445	0	0
T10	128923	128923	0	0
T11	72451	72443	0	0
T30	107	107	0	0
T36	109	109	0	0
T37	2468	2468	0	0
T38	141	141	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10726259	10725893	0	0
T1	109	109	0	0
T2	155	155	0	0
T3	116	116	0	0
T7	2445	2445	0	0
T10	128923	128923	0	0
T11	72451	72443	0	0
T30	107	107	0	0
T36	109	109	0	0
T37	2468	2468	0	0
T38	141	141	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20513535	20473311	0	0
T1	1069	1008	0	0
T2	1436	1364	0	0
T3	1167	1104	0	0
T7	1714	1662	0	0
T10	596024	595966	0	0
T11	175312	174702	0	0
T30	1007	937	0	0
T36	1582	1511	0	0
T37	20533	19217	0	0
T38	1920	1868	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	161	161	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T30	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T38	1	1	0	0