Line Coverage for Module :
rv_dm_regs_reg_top
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 18 | 75.00 |
ALWAYS | 67 | 4 | 4 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 0 | 0.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
ALWAYS | 150 | 2 | 0 | 0.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
ALWAYS | 158 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
ALWAYS | 169 | 2 | 2 | 100.00 |
ALWAYS | 175 | 3 | 0 | 0.00 |
CONT_ASSIGN | 192 | 0 | 0 | |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
|
|
|
MISSING_ELSE |
76 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
117 |
0 |
1 |
118 |
1 |
1 |
130 |
1 |
1 |
144 |
1 |
1 |
150 |
0 |
1 |
151 |
0 |
1 |
154 |
1 |
1 |
158 |
1 |
1 |
163 |
1 |
1 |
165 |
1 |
1 |
169 |
1 |
1 |
170 |
1 |
1 |
175 |
0 |
1 |
176 |
0 |
1 |
178 |
0 |
1 |
192 |
|
unreachable |
200 |
1 |
1 |
201 |
1 |
1 |
Cond Coverage for Module :
rv_dm_regs_reg_top
| Total | Covered | Percent |
Conditions | 28 | 23 | 82.14 |
Logical | 28 | 23 | 82.14 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 57
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 69
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T37,T40,T41 |
1 | 0 | Covered | T42,T43,T44 |
LINE 76
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T37,T40,T41 |
0 | 1 | 0 | Covered | T42,T43,T44 |
1 | 0 | 0 | Covered | T37,T40,T41 |
LINE 118
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T42,T43,T44 |
0 | 1 | 0 | Covered | T45,T46,T47 |
1 | 0 | 0 | Not Covered | |
LINE 151
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Unreachable | |
1 | Not Covered | |
LINE 154
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 154
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T48,T49,T50 |
LINE 158
EXPRESSION (reg_we & addr_hit[0] & ((|(4'b1 & (~reg_be)))))
---1-- -----2----- -----------3-----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T30,T14 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T42,T45,T43 |
LINE 163
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T42,T45,T43 |
1 | 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
rv_dm_regs_reg_top
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
154 |
2 |
2 |
100.00 |
IF |
67 |
3 |
3 |
100.00 |
CASE |
176 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 154 ((reg_re || reg_we)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 67 if ((!rst_ni))
-2-: 69 if ((intg_err || reg_we_err))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T37,T40,T41 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 176 case (1'b1)
Branches:
-1- | Status | Tests |
addr_hit[0] |
Not Covered |
|
default |
Not Covered |
|
Assert Coverage for Module :
rv_dm_regs_reg_top
Assertion Details
en2addrHit
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
43906097 |
3305 |
0 |
0 |
T1 |
1069 |
5 |
0 |
0 |
T2 |
1436 |
10 |
0 |
0 |
T3 |
1167 |
11 |
0 |
0 |
T7 |
1714 |
0 |
0 |
0 |
T10 |
596024 |
0 |
0 |
0 |
T11 |
175312 |
0 |
0 |
0 |
T30 |
1007 |
11 |
0 |
0 |
T36 |
1582 |
10 |
0 |
0 |
T37 |
20533 |
0 |
0 |
0 |
T38 |
1920 |
8 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
23 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
reAfterRv
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
43906097 |
3305 |
0 |
0 |
T1 |
1069 |
5 |
0 |
0 |
T2 |
1436 |
10 |
0 |
0 |
T3 |
1167 |
11 |
0 |
0 |
T7 |
1714 |
0 |
0 |
0 |
T10 |
596024 |
0 |
0 |
0 |
T11 |
175312 |
0 |
0 |
0 |
T30 |
1007 |
11 |
0 |
0 |
T36 |
1582 |
10 |
0 |
0 |
T37 |
20533 |
0 |
0 |
0 |
T38 |
1920 |
8 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
23 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
rePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
43906097 |
1862 |
0 |
0 |
T42 |
17152 |
13 |
0 |
0 |
T48 |
50244 |
1 |
0 |
0 |
T49 |
9043 |
2 |
0 |
0 |
T50 |
5173 |
3 |
0 |
0 |
T55 |
7640 |
2 |
0 |
0 |
T56 |
5412 |
1 |
0 |
0 |
T57 |
3317 |
2 |
0 |
0 |
T58 |
328977 |
282 |
0 |
0 |
T59 |
57643 |
4 |
0 |
0 |
T60 |
3542 |
2 |
0 |
0 |
wePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
43906097 |
1443 |
0 |
0 |
T1 |
1069 |
5 |
0 |
0 |
T2 |
1436 |
10 |
0 |
0 |
T3 |
1167 |
11 |
0 |
0 |
T7 |
1714 |
0 |
0 |
0 |
T10 |
596024 |
0 |
0 |
0 |
T11 |
175312 |
0 |
0 |
0 |
T30 |
1007 |
11 |
0 |
0 |
T36 |
1582 |
10 |
0 |
0 |
T37 |
20533 |
0 |
0 |
0 |
T38 |
1920 |
8 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
6 |
0 |
0 |
T53 |
0 |
23 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |