SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.97 | 93.33 | 75.86 | 91.19 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
86.97 | 93.33 | 75.86 | 91.19 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 644 | 644 | 0 | 0 |
OutputsKnown_A | 82054140 | 81893244 | 0 | 0 |
gen_flops.OutputDelay_A | 41027070 | 40943010 | 0 | 966 |
gen_no_flops.OutputDelay_A | 41027070 | 40946622 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 644 | 644 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T7 | 4 | 4 | 0 | 0 |
T10 | 4 | 4 | 0 | 0 |
T11 | 4 | 4 | 0 | 0 |
T30 | 4 | 4 | 0 | 0 |
T36 | 4 | 4 | 0 | 0 |
T37 | 4 | 4 | 0 | 0 |
T38 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 82054140 | 81893244 | 0 | 0 |
T1 | 4276 | 4032 | 0 | 0 |
T2 | 5744 | 5456 | 0 | 0 |
T3 | 4668 | 4416 | 0 | 0 |
T7 | 6856 | 6648 | 0 | 0 |
T10 | 2384096 | 2383864 | 0 | 0 |
T11 | 701248 | 698808 | 0 | 0 |
T30 | 4028 | 3748 | 0 | 0 |
T36 | 6328 | 6044 | 0 | 0 |
T37 | 82132 | 76868 | 0 | 0 |
T38 | 7680 | 7472 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 41027070 | 40943010 | 0 | 966 |
T1 | 2138 | 2010 | 0 | 6 |
T2 | 2872 | 2722 | 0 | 6 |
T3 | 2334 | 2202 | 0 | 6 |
T7 | 3428 | 3318 | 0 | 6 |
T10 | 1192048 | 1191926 | 0 | 6 |
T11 | 350624 | 349350 | 0 | 6 |
T30 | 2014 | 1868 | 0 | 6 |
T36 | 3164 | 3016 | 0 | 6 |
T37 | 41066 | 38308 | 0 | 6 |
T38 | 3840 | 3730 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 41027070 | 40946622 | 0 | 0 |
T1 | 2138 | 2016 | 0 | 0 |
T2 | 2872 | 2728 | 0 | 0 |
T3 | 2334 | 2208 | 0 | 0 |
T7 | 3428 | 3324 | 0 | 0 |
T10 | 1192048 | 1191932 | 0 | 0 |
T11 | 350624 | 349404 | 0 | 0 |
T30 | 2014 | 1874 | 0 | 0 |
T36 | 3164 | 3022 | 0 | 0 |
T37 | 41066 | 38434 | 0 | 0 |
T38 | 3840 | 3736 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 20513535 | 20473311 | 0 | 0 |
gen_flops.OutputDelay_A | 20513535 | 20471505 | 0 | 483 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20473311 | 0 | 0 |
T1 | 1069 | 1008 | 0 | 0 |
T2 | 1436 | 1364 | 0 | 0 |
T3 | 1167 | 1104 | 0 | 0 |
T7 | 1714 | 1662 | 0 | 0 |
T10 | 596024 | 595966 | 0 | 0 |
T11 | 175312 | 174702 | 0 | 0 |
T30 | 1007 | 937 | 0 | 0 |
T36 | 1582 | 1511 | 0 | 0 |
T37 | 20533 | 19217 | 0 | 0 |
T38 | 1920 | 1868 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20471505 | 0 | 483 |
T1 | 1069 | 1005 | 0 | 3 |
T2 | 1436 | 1361 | 0 | 3 |
T3 | 1167 | 1101 | 0 | 3 |
T7 | 1714 | 1659 | 0 | 3 |
T10 | 596024 | 595963 | 0 | 3 |
T11 | 175312 | 174675 | 0 | 3 |
T30 | 1007 | 934 | 0 | 3 |
T36 | 1582 | 1508 | 0 | 3 |
T37 | 20533 | 19154 | 0 | 3 |
T38 | 1920 | 1865 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 20513535 | 20473311 | 0 | 0 |
gen_flops.OutputDelay_A | 20513535 | 20471505 | 0 | 483 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20473311 | 0 | 0 |
T1 | 1069 | 1008 | 0 | 0 |
T2 | 1436 | 1364 | 0 | 0 |
T3 | 1167 | 1104 | 0 | 0 |
T7 | 1714 | 1662 | 0 | 0 |
T10 | 596024 | 595966 | 0 | 0 |
T11 | 175312 | 174702 | 0 | 0 |
T30 | 1007 | 937 | 0 | 0 |
T36 | 1582 | 1511 | 0 | 0 |
T37 | 20533 | 19217 | 0 | 0 |
T38 | 1920 | 1868 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20471505 | 0 | 483 |
T1 | 1069 | 1005 | 0 | 3 |
T2 | 1436 | 1361 | 0 | 3 |
T3 | 1167 | 1101 | 0 | 3 |
T7 | 1714 | 1659 | 0 | 3 |
T10 | 596024 | 595963 | 0 | 3 |
T11 | 175312 | 174675 | 0 | 3 |
T30 | 1007 | 934 | 0 | 3 |
T36 | 1582 | 1508 | 0 | 3 |
T37 | 20533 | 19154 | 0 | 3 |
T38 | 1920 | 1865 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 20513535 | 20473311 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20513535 | 20473311 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20473311 | 0 | 0 |
T1 | 1069 | 1008 | 0 | 0 |
T2 | 1436 | 1364 | 0 | 0 |
T3 | 1167 | 1104 | 0 | 0 |
T7 | 1714 | 1662 | 0 | 0 |
T10 | 596024 | 595966 | 0 | 0 |
T11 | 175312 | 174702 | 0 | 0 |
T30 | 1007 | 937 | 0 | 0 |
T36 | 1582 | 1511 | 0 | 0 |
T37 | 20533 | 19217 | 0 | 0 |
T38 | 1920 | 1868 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20473311 | 0 | 0 |
T1 | 1069 | 1008 | 0 | 0 |
T2 | 1436 | 1364 | 0 | 0 |
T3 | 1167 | 1104 | 0 | 0 |
T7 | 1714 | 1662 | 0 | 0 |
T10 | 596024 | 595966 | 0 | 0 |
T11 | 175312 | 174702 | 0 | 0 |
T30 | 1007 | 937 | 0 | 0 |
T36 | 1582 | 1511 | 0 | 0 |
T37 | 20533 | 19217 | 0 | 0 |
T38 | 1920 | 1868 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 161 | 161 | 0 | 0 |
OutputsKnown_A | 20513535 | 20473311 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20513535 | 20473311 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 161 | 161 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
T37 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20473311 | 0 | 0 |
T1 | 1069 | 1008 | 0 | 0 |
T2 | 1436 | 1364 | 0 | 0 |
T3 | 1167 | 1104 | 0 | 0 |
T7 | 1714 | 1662 | 0 | 0 |
T10 | 596024 | 595966 | 0 | 0 |
T11 | 175312 | 174702 | 0 | 0 |
T30 | 1007 | 937 | 0 | 0 |
T36 | 1582 | 1511 | 0 | 0 |
T37 | 20533 | 19217 | 0 | 0 |
T38 | 1920 | 1868 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20513535 | 20473311 | 0 | 0 |
T1 | 1069 | 1008 | 0 | 0 |
T2 | 1436 | 1364 | 0 | 0 |
T3 | 1167 | 1104 | 0 | 0 |
T7 | 1714 | 1662 | 0 | 0 |
T10 | 596024 | 595966 | 0 | 0 |
T11 | 175312 | 174702 | 0 | 0 |
T30 | 1007 | 937 | 0 | 0 |
T36 | 1582 | 1511 | 0 | 0 |
T37 | 20533 | 19217 | 0 | 0 |
T38 | 1920 | 1868 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |