Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.05	100.00	75.86	92.86			87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	47232050	11967	0	0
late_debug_enable_rd_A	47232050	2711	0	0
late_debug_enable_regwen_rd_A	47232050	2415	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47232050	11967	0	0
T47	3915	160	0	0
T48	50131	44	0	0
T49	318276	32	0	0
T50	5153	702	0	0
T67	18820	1	0	0
T68	16768	320	0	0
T75	7307	137	0	0
T76	87590	204	0	0
T77	23911	1	0	0
T78	316732	47	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47232050	2711	0	0
T62	336203	16	0	0
T68	16768	190	0	0
T75	7307	10	0	0
T85	318039	245	0	0
T86	8511	7	0	0
T88	8730	3	0	0
T90	422715	919	0	0
T92	29306	30	0	0
T99	27596	30	0	0
T100	4562	4	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47232050	2415	0	0
T68	16768	89	0	0
T75	7307	27	0	0
T85	318039	168	0	0
T86	8511	7	0	0
T88	8730	10	0	0
T89	4771	4	0	0
T90	422715	894	0	0
T92	29306	15	0	0
T99	27596	24	0	0
T100	4562	1	0	0