Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.05	100.00	75.86	92.86			87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	89.05	100.00	75.86	92.86			87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.05	100.00	75.86	92.86			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.98	94.82	81.77	89.99	78.21	84.55	98.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	86.73	98.68	93.42		72.00	94.57	75.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	93.27	99.00	80.90	93.33		93.10	100.00
rv_dm_regs_csr_assert	100.00						100.00
tl_adapter_host_sba	95.14	100.00	100.00	75.71		100.00	100.00
tlul_assert_device_mem	95.24	100.00				85.71	100.00
tlul_assert_device_regs	95.24	100.00				85.71	100.00
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	85.57	87.41	66.67		100.00	73.76	100.00
u_lc_en_sync_copies	100.00	100.00					100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	100.00	100.00	100.00				100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_mubi32_sync_late_debug_enable	100.00	100.00					100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00				100.00	100.00
u_prim_rst_n_mux2	100.00	100.00	100.00				100.00
u_reg_regs	98.19	98.69	98.71	93.55		100.00	100.00
u_tlul_lc_gate_rom	83.22	93.94	57.50		100.00	77.14	87.50
u_tlul_lc_gate_sba	72.24	90.15	55.00		57.14	71.43	87.50

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	481	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
117	1	1
118	1	1
123	1	1
126	1	1
149	1	1
231	1	1
232	1	1
234	4	4
275	1	1
276	1	1
280	1	1
363	1	1
369	1	1
371	1	1
377	1	1
378	1	1
453	1	1
481	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	29	22	75.86
Logical	29	22	75.86
Non-Logical	0	0
Event	0	0

 LINE       123
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T38,T39,T40

 LINE       126
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T26
1	0	Covered	T1,T25,T26
1	1	Covered	T1,T25,T26

 LINE       276
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T15,T16

 LINE       371
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T7

 LINE       406
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T6,T15
1	1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       481
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T35,T15
1	0	Covered	T4,T5,T7

 LINE       497
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       497
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T6,T15
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	95	77	81.05
Total Bits	1120	1040	92.86
Total Bits 0->1	560	520	92.86
Total Bits 1->0	560	520	92.86

Ports	95	77	81.05
Port Bits	1120	1040	92.86
Port Bits 0->1	560	520	92.86
Port Bits 1->0	560	520	92.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T18,T6,T15	Yes	T5,T18,T6	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T18,T6,T15	Yes	T5,T18,T6	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T18,T6,T15	Yes	T5,T18,T6	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[0]	No	No		Yes	T6,T16,T46	INPUT
scanmode_i[2:1]	No	Yes	T6,T16,T46	No		INPUT
scanmode_i[3]	No	No		Yes	T6,T16,T46	INPUT
scan_rst_ni	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T5,T15,T16	Yes	T5,T15,T16	OUTPUT
dmactive_o	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T5,T6,T15	Yes	T4,T5,T7	OUTPUT
unavailable_i	Yes	Yes	T8,T5,T19	Yes	T8,T5,T19	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T26,T13,T4	Yes	T26,T13,T5	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T26,T13,T5	Yes	T26,T13,T4	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T26,T13,T5	Yes	T26,T13,T4	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T26,T13,T5	Yes	T26,T13,T5	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T26,T13,T5	Yes	T26,T13,T5	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T47,T48,T49	Yes	T50,T47,T48	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T47,T48,T51	Yes	T47,T48,T51	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T25,*T26	Yes	T1,T25,T26	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T47,T48,T51	Yes	T1,T25,T26	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T50,*T47,*T48	Yes	T50,T47,T48	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T25,T14,T17	Yes	T8,T14,T5	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T14,T17	Yes	T25,T4,T14	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T25,T14,T7	Yes	T14,T7,T52	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T14,T17,T7	Yes	T25,T14,T7	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T25,T8,T14	Yes	T14,T5,T7	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T25,T14,T5	Yes	T8,T14,T5	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T25,T8,T14	Yes	T14,T7,T52	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T8,T4,T14	Yes	T25,T4,T14	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T25,T4,T14	Yes	T8,T4,T14	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T8,T14,T7	Yes	T14,T19,T7	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T4,T14,T5	Yes	T25,T8,T4	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T11,T13,T14	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T5,T35,T15	Yes	T5,T35,T15	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T7	Yes	T4,T5,T7	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T11,T13,T4	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T11,T13,T14	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T9,T11	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T11,*T13,*T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T3,T9,T11	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T3,*T9,*T11	Yes	T3,T9,T11	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T3,T9,T11	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T2,T11,T13	Yes	T11,T13,T4	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T3,T9,T11	Yes	T2,T3,T9	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T2,T3,T9	Yes	T3,T9,T11	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T2,T14,T38	Yes	T4,T14,T38	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T2,T11,T13	Yes	T11,T13,T14	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T2,T14,T53	Yes	T4,T14,T38	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T2,T3,T9	Yes	T3,T9,T11	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T3,T9,T11	Yes	T3,T9,T11	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T25,T26	Yes	T1,T25,T26	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T11,T13,T14	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	23544567	23486955	0	0
DmactiveOKnown_A	23544567	23486955	0	0
FpvSecCmRegWeOnehotCheck_A	23544567	80	0	0
FpvSecCmRomTlLcGateFsm_A	23544567	0	0	0
FpvSecCmSbaTlLcGateFsm_A	23544567	0	0	0
JtagRspOTdoKnown_A	15807116	15806542	0	0
JtagRspOTdoOeKnown_A	15807116	15806542	0	0
NdmresetOKnown_A	23544567	23486955	0	0
RvDmLcEnDebugVal_A	23544567	23486955	0	0
TlMemAReadyKnown_A	23544567	23486955	0	0
TlMemDValidKnown_A	23544567	23486955	0	0
TlRegsAReadyKnown_A	23544567	23486955	0	0
TlRegsDValidKnown_A	23544567	23486955	0	0
TlSbaAValidKnown_A	23544567	23486955	0	0
TlSbaDReadyKnown_A	23544567	23486955	0	0
paramCheckNrHarts	175	175	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	80	0	0
T6	624095	0	0	0
T21	398255	0	0	0
T24	1857	0	0	0
T38	16376	20	0	0
T39	0	10	0	0
T40	0	10	0	0
T54	0	20	0	0
T55	0	20	0	0
T56	1894	0	0	0
T57	1789	0	0	0
T58	1188	0	0	0
T59	30105	0	0	0
T60	1101	0	0	0
T61	412086	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15807116	15806542	0	0
T1	132	132	0	0
T2	3138	3138	0	0
T3	116972	116972	0	0
T4	11178	11178	0	0
T8	1839	1839	0	0
T9	41602	41602	0	0
T11	103118	103101	0	0
T13	180059	180045	0	0
T25	181	181	0	0
T26	107	107	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15807116	15806542	0	0
T1	132	132	0	0
T2	3138	3138	0	0
T3	116972	116972	0	0
T4	11178	11178	0	0
T8	1839	1839	0	0
T9	41602	41602	0	0
T11	103118	103101	0	0
T13	180059	180045	0	0
T25	181	181	0	0
T26	107	107	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23544567	23486955	0	0
T1	1994	1943	0	0
T2	16784	16726	0	0
T3	468959	468900	0	0
T4	59744	59694	0	0
T8	2477	2411	0	0
T9	439279	439221	0	0
T11	262148	260997	0	0
T13	683002	682062	0	0
T25	1215	1158	0	0
T26	1561	1481	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0