SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.05 | 100.00 | 75.86 | 92.86 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.05 | 100.00 | 75.86 | 92.86 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.05 | 100.00 | 75.86 | 92.86 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.05 | 100.00 | 75.86 | 92.86 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 141267402 | 140921730 | 0 | 0 |
gen_flops.OutputDelay_A | 70633701 | 70453035 | 0 | 1575 |
gen_no_flops.OutputDelay_A | 70633701 | 70460865 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T25 | 6 | 6 | 0 | 0 |
T26 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 141267402 | 140921730 | 0 | 0 |
T1 | 11964 | 11658 | 0 | 0 |
T2 | 100704 | 100356 | 0 | 0 |
T3 | 2813754 | 2813400 | 0 | 0 |
T4 | 358464 | 358164 | 0 | 0 |
T8 | 14862 | 14466 | 0 | 0 |
T9 | 2635674 | 2635326 | 0 | 0 |
T11 | 1572888 | 1565982 | 0 | 0 |
T13 | 4098012 | 4092372 | 0 | 0 |
T25 | 7290 | 6948 | 0 | 0 |
T26 | 9366 | 8886 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70633701 | 70453035 | 0 | 1575 |
T1 | 5982 | 5820 | 0 | 9 |
T2 | 50352 | 50169 | 0 | 9 |
T3 | 1406877 | 1406691 | 0 | 9 |
T4 | 179232 | 179073 | 0 | 9 |
T8 | 7431 | 7224 | 0 | 9 |
T9 | 1317837 | 1317654 | 0 | 9 |
T11 | 786444 | 782829 | 0 | 9 |
T13 | 2049006 | 2046051 | 0 | 9 |
T25 | 3645 | 3465 | 0 | 9 |
T26 | 4683 | 4434 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70633701 | 70460865 | 0 | 0 |
T1 | 5982 | 5829 | 0 | 0 |
T2 | 50352 | 50178 | 0 | 0 |
T3 | 1406877 | 1406700 | 0 | 0 |
T4 | 179232 | 179082 | 0 | 0 |
T8 | 7431 | 7233 | 0 | 0 |
T9 | 1317837 | 1317663 | 0 | 0 |
T11 | 786444 | 782991 | 0 | 0 |
T13 | 2049006 | 2046186 | 0 | 0 |
T25 | 3645 | 3474 | 0 | 0 |
T26 | 4683 | 4443 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 175 | 175 | 0 | 0 |
OutputsKnown_A | 23544567 | 23486955 | 0 | 0 |
gen_flops.OutputDelay_A | 23544567 | 23484345 | 0 | 525 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 175 | 175 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23484345 | 0 | 525 |
T1 | 1994 | 1940 | 0 | 3 |
T2 | 16784 | 16723 | 0 | 3 |
T3 | 468959 | 468897 | 0 | 3 |
T4 | 59744 | 59691 | 0 | 3 |
T8 | 2477 | 2408 | 0 | 3 |
T9 | 439279 | 439218 | 0 | 3 |
T11 | 262148 | 260943 | 0 | 3 |
T13 | 683002 | 682017 | 0 | 3 |
T25 | 1215 | 1155 | 0 | 3 |
T26 | 1561 | 1478 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 175 | 175 | 0 | 0 |
OutputsKnown_A | 23544567 | 23486955 | 0 | 0 |
gen_flops.OutputDelay_A | 23544567 | 23484345 | 0 | 525 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 175 | 175 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23484345 | 0 | 525 |
T1 | 1994 | 1940 | 0 | 3 |
T2 | 16784 | 16723 | 0 | 3 |
T3 | 468959 | 468897 | 0 | 3 |
T4 | 59744 | 59691 | 0 | 3 |
T8 | 2477 | 2408 | 0 | 3 |
T9 | 439279 | 439218 | 0 | 3 |
T11 | 262148 | 260943 | 0 | 3 |
T13 | 683002 | 682017 | 0 | 3 |
T25 | 1215 | 1155 | 0 | 3 |
T26 | 1561 | 1478 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 175 | 175 | 0 | 0 |
OutputsKnown_A | 23544567 | 23486955 | 0 | 0 |
gen_no_flops.OutputDelay_A | 23544567 | 23486955 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 175 | 175 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 175 | 175 | 0 | 0 |
OutputsKnown_A | 23544567 | 23486955 | 0 | 0 |
gen_flops.OutputDelay_A | 23544567 | 23484345 | 0 | 525 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 175 | 175 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23484345 | 0 | 525 |
T1 | 1994 | 1940 | 0 | 3 |
T2 | 16784 | 16723 | 0 | 3 |
T3 | 468959 | 468897 | 0 | 3 |
T4 | 59744 | 59691 | 0 | 3 |
T8 | 2477 | 2408 | 0 | 3 |
T9 | 439279 | 439218 | 0 | 3 |
T11 | 262148 | 260943 | 0 | 3 |
T13 | 683002 | 682017 | 0 | 3 |
T25 | 1215 | 1155 | 0 | 3 |
T26 | 1561 | 1478 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 175 | 175 | 0 | 0 |
OutputsKnown_A | 23544567 | 23486955 | 0 | 0 |
gen_no_flops.OutputDelay_A | 23544567 | 23486955 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 175 | 175 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 175 | 175 | 0 | 0 |
OutputsKnown_A | 23544567 | 23486955 | 0 | 0 |
gen_no_flops.OutputDelay_A | 23544567 | 23486955 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 175 | 175 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 23544567 | 23486955 | 0 | 0 |
T1 | 1994 | 1943 | 0 | 0 |
T2 | 16784 | 16726 | 0 | 0 |
T3 | 468959 | 468900 | 0 | 0 |
T4 | 59744 | 59694 | 0 | 0 |
T8 | 2477 | 2411 | 0 | 0 |
T9 | 439279 | 439221 | 0 | 0 |
T11 | 262148 | 260997 | 0 | 0 |
T13 | 683002 | 682062 | 0 | 0 |
T25 | 1215 | 1158 | 0 | 0 |
T26 | 1561 | 1481 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |