Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.82	90.91	61.70	86.87		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	45821227	13162	0	0
late_debug_enable_rd_A	45821227	2553	0	0
late_debug_enable_regwen_rd_A	45821227	3424	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45821227	13162	0	0
T38	330314	39	0	0
T39	480146	85	0	0
T40	657201	122	0	0
T41	5037	258	0	0
T63	4470	243	0	0
T65	186444	120	0	0
T73	6354	48	0	0
T74	792960	67	0	0
T75	121147	261	0	0
T76	443080	60	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45821227	2553	0	0
T40	657201	72	0	0
T64	16497	236	0	0
T85	9451	6	0	0
T90	490659	377	0	0
T93	21128	6	0	0
T94	39126	31	0	0
T95	4420	6	0	0
T102	9337	3	0	0
T103	4745	2	0	0
T112	7806	146	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45821227	3424	0	0
T40	657201	49	0	0
T42	211532	1061	0	0
T64	16497	239	0	0
T85	9451	11	0	0
T90	490659	499	0	0
T93	21128	37	0	0
T94	39126	11	0	0
T95	4420	9	0	0
T102	9337	2	0	0
T112	7806	79	0	0