Line Coverage for Module :
rv_dm
| Line No. | Total | Covered | Percent |
TOTAL | | 33 | 30 | 90.91 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 320 | 11 | 8 | 72.73 |
CONT_ASSIGN | 345 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 438 | 1 | 1 | 100.00 |
CONT_ASSIGN | 440 | 1 | 1 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
1 |
1 |
131 |
1 |
1 |
154 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
239 |
4 |
4 |
278 |
1 |
1 |
288 |
1 |
1 |
289 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
322 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
327 |
1 |
1 |
328 |
0 |
1 |
|
|
|
MISSING_ELSE |
331 |
1 |
1 |
332 |
0 |
1 |
333 |
1 |
1 |
334 |
0 |
1 |
|
|
|
MISSING_ELSE |
345 |
1 |
1 |
432 |
1 |
1 |
438 |
1 |
1 |
440 |
1 |
1 |
446 |
1 |
1 |
447 |
1 |
1 |
523 |
1 |
1 |
551 |
1 |
1 |
Cond Coverage for Module :
rv_dm
| Total | Covered | Percent |
Conditions | 47 | 29 | 61.70 |
Logical | 47 | 29 | 61.70 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 128
EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
-------1------- -------2------ ---------3--------- ---------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T29,T30,T31 |
LINE 131
SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
------------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T27,T32 |
1 | 0 | Covered | T2,T27,T4 |
1 | 1 | Covered | T2,T27,T32 |
LINE 289
EXPRESSION (ndmreset_req_qual & reset_req_en)
--------1-------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T20,T21,T12 |
LINE 325
EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T20,T21,T12 |
1 | 1 | Covered | T20,T21,T12 |
LINE 327
EXPRESSION (ndmreset_ack && ndmreset_pending_q)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T20,T21,T12 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 331
EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
---------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T20,T21,T12 |
1 | 1 | Not Covered | |
LINE 333
EXPRESSION (ndmreset_ack && lc_rst_pending_q)
------1----- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 345
EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
---------1-------- --------2------- --------3-------- ----------4--------- ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | 1 | Covered | T20,T21,T12 |
1 | 1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | 1 | Not Covered | |
LINE 440
EXPRESSION (debug_req & debug_req_en)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T5,T7 |
LINE 476
EXPRESSION (dmi_req_ready & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T1,T2,T3 |
LINE 476
EXPRESSION (dmi_rsp_valid & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 551
EXPRESSION (device_we || device_re)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T20,T7 |
1 | 0 | Covered | T4,T5,T20 |
LINE 567
EXPRESSION (dmi_req_valid & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 567
EXPRESSION (dmi_rsp_ready & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T12,T18,T33 |
1 | 1 | Covered | T1,T2,T3 |
Toggle Coverage for Module :
rv_dm
| Total | Covered | Percent |
Totals |
98 |
76 |
77.55 |
Total Bits |
1188 |
1032 |
86.87 |
Total Bits 0->1 |
594 |
516 |
86.87 |
Total Bits 1->0 |
594 |
516 |
86.87 |
| | | |
Ports |
98 |
76 |
77.55 |
Port Bits |
1188 |
1032 |
86.87 |
Port Bits 0->1 |
594 |
516 |
86.87 |
Port Bits 1->0 |
594 |
516 |
86.87 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_lc_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
INPUT |
rst_lc_ni |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
INPUT |
next_dm_addr_i[31:0] |
No |
No |
|
No |
|
INPUT |
lc_hw_debug_en_i[0] |
No |
No |
|
Yes |
T12,T18,T34 |
INPUT |
lc_hw_debug_en_i[1] |
No |
Yes |
*T12,*T18,*T34 |
No |
|
INPUT |
lc_hw_debug_en_i[2] |
No |
No |
|
Yes |
T12,T18,T34 |
INPUT |
lc_hw_debug_en_i[3] |
No |
Yes |
T12,T18,T34 |
No |
|
INPUT |
lc_dft_en_i[0] |
No |
No |
|
Yes |
T12,T18,T34 |
INPUT |
lc_dft_en_i[1] |
No |
Yes |
*T12,*T18,*T34 |
No |
|
INPUT |
lc_dft_en_i[2] |
No |
No |
|
Yes |
T12,T18,T34 |
INPUT |
lc_dft_en_i[3] |
No |
Yes |
T12,T18,T34 |
No |
|
INPUT |
pinmux_hw_debug_en_i[0] |
No |
No |
|
Yes |
T12,T18,T34 |
INPUT |
pinmux_hw_debug_en_i[1] |
No |
Yes |
*T12,*T18,*T34 |
No |
|
INPUT |
pinmux_hw_debug_en_i[2] |
No |
No |
|
Yes |
T12,T18,T34 |
INPUT |
pinmux_hw_debug_en_i[3] |
No |
Yes |
T12,T18,T34 |
No |
|
INPUT |
otp_dis_rv_dm_late_debug_i[7:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
scanmode_i[0] |
No |
No |
|
Yes |
T12,T18,T33 |
INPUT |
scanmode_i[2:1] |
No |
Yes |
T12,T18,T33 |
No |
|
INPUT |
scanmode_i[3] |
No |
No |
|
Yes |
T12,T18,T33 |
INPUT |
scan_rst_ni |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
INPUT |
ndmreset_req_o |
Yes |
Yes |
T20,T21,T12 |
Yes |
T20,T21,T12 |
OUTPUT |
dmactive_o |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
OUTPUT |
debug_req_o |
Yes |
Yes |
T5,T21,T8 |
Yes |
T4,T5,T7 |
OUTPUT |
unavailable_i |
Yes |
Yes |
T20,T21,T35 |
Yes |
T20,T21,T35 |
INPUT |
regs_tl_d_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T2,T27,T4 |
Yes |
T2,T27,T29 |
INPUT |
regs_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T2,T27,T4 |
Yes |
T2,T27,T29 |
INPUT |
regs_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T29,T16 |
Yes |
T29,T10,T16 |
INPUT |
regs_tl_d_i.a_user.rsvd[4:0] |
Yes |
Yes |
T29,T16,T36 |
Yes |
T29,T16,T36 |
INPUT |
regs_tl_d_i.a_data[31:0] |
Yes |
Yes |
T2,T27,T4 |
Yes |
T2,T27,T29 |
INPUT |
regs_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T29,T16,T36 |
Yes |
T29,T16,T36 |
INPUT |
regs_tl_d_i.a_address[31:0] |
Yes |
Yes |
T29,T10,T16 |
Yes |
T29,T16,T37 |
INPUT |
regs_tl_d_i.a_source[7:0] |
Yes |
Yes |
T2,T27,T29 |
Yes |
T2,T27,T29 |
INPUT |
regs_tl_d_i.a_size[1:0] |
Yes |
Yes |
T2,T27,T29 |
Yes |
T2,T27,T29 |
INPUT |
regs_tl_d_i.a_param[2:0] |
Yes |
Yes |
T29,T16,T37 |
Yes |
T4,T29,T16 |
INPUT |
regs_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T2,T27,T29 |
Yes |
T2,T27,T4 |
INPUT |
regs_tl_d_i.a_valid |
Yes |
Yes |
T2,T27,T32 |
Yes |
T2,T27,T32 |
INPUT |
regs_tl_d_o.a_ready |
Yes |
Yes |
T2,T27,T32 |
Yes |
T2,T27,T32 |
OUTPUT |
regs_tl_d_o.d_error |
Yes |
Yes |
T38,T39,T40 |
Yes |
T38,T39,T41 |
OUTPUT |
regs_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T42,T43,T44 |
Yes |
T42,T43,T44 |
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T2,*T27,*T32 |
Yes |
T2,T27,T32 |
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_data[31:0] |
Yes |
Yes |
T38,T42,T43 |
Yes |
T2,T27,T32 |
OUTPUT |
regs_tl_d_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_source[7:0] |
Yes |
Yes |
T2,T27,T45 |
Yes |
T2,T27,T36 |
OUTPUT |
regs_tl_d_o.d_size[1:0] |
Yes |
Yes |
T2,T27,T32 |
Yes |
T2,T27,T32 |
OUTPUT |
regs_tl_d_o.d_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T38,*T42,*T43 |
Yes |
T38,T42,T43 |
OUTPUT |
regs_tl_d_o.d_opcode[2:1] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_valid |
Yes |
Yes |
T2,T27,T32 |
Yes |
T2,T27,T32 |
OUTPUT |
mem_tl_d_i.d_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
mem_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T5,T20 |
Yes |
T1,T5,T20 |
INPUT |
mem_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T4,T5 |
INPUT |
mem_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T1,T20,T37 |
Yes |
T27,T20,T8 |
INPUT |
mem_tl_d_i.a_user.rsvd[4:0] |
Yes |
Yes |
T1,T20,T8 |
Yes |
T20,T8,T23 |
INPUT |
mem_tl_d_i.a_data[31:0] |
Yes |
Yes |
T5,T20,T7 |
Yes |
T27,T5,T20 |
INPUT |
mem_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T1,T27,T5 |
Yes |
T1,T5,T20 |
INPUT |
mem_tl_d_i.a_address[31:0] |
Yes |
Yes |
T1,T5,T20 |
Yes |
T1,T5,T20 |
INPUT |
mem_tl_d_i.a_source[7:0] |
Yes |
Yes |
T1,T5,T20 |
Yes |
T1,T5,T20 |
INPUT |
mem_tl_d_i.a_size[1:0] |
Yes |
Yes |
T1,T5,T20 |
Yes |
T1,T4,T5 |
INPUT |
mem_tl_d_i.a_param[2:0] |
Yes |
Yes |
T20,T37,T46 |
Yes |
T1,T20,T8 |
INPUT |
mem_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T27,T4 |
INPUT |
mem_tl_d_i.a_valid |
Yes |
Yes |
T4,T5,T20 |
Yes |
T4,T5,T20 |
INPUT |
mem_tl_d_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
mem_tl_d_o.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T11,T29 |
OUTPUT |
mem_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T5,T20,T7 |
Yes |
T5,T20,T7 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
T5,*T20,*T7 |
Yes |
T4,T5,T20 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T11,T4 |
OUTPUT |
mem_tl_d_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_source[7:0] |
Yes |
Yes |
T5,T20,T8 |
Yes |
T5,T20,T7 |
OUTPUT |
mem_tl_d_o.d_size[1:0] |
Yes |
Yes |
T5,T20,T7 |
Yes |
T4,T5,T20 |
OUTPUT |
mem_tl_d_o.d_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T11,T29 |
OUTPUT |
mem_tl_d_o.d_opcode[2:1] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_valid |
Yes |
Yes |
T4,T5,T20 |
Yes |
T4,T5,T20 |
OUTPUT |
sba_tl_h_o.d_ready |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
OUTPUT |
sba_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[0] |
Yes |
Yes |
*T1,*T11,*T29 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[2:1] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_user.instr_type[3] |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.rsvd[4:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_data[31:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
OUTPUT |
sba_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_address[1:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_address[31:2] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
OUTPUT |
sba_tl_h_o.a_source[7:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_size[0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_size[1] |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_opcode[0] |
Yes |
Yes |
*T1,*T3,*T11 |
Yes |
T1,T3,T11 |
OUTPUT |
sba_tl_h_o.a_opcode[1] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_opcode[2] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_valid |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
OUTPUT |
sba_tl_h_i.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
sba_tl_h_i.d_error |
Yes |
Yes |
T1,T11,T28 |
Yes |
T1,T11,T27 |
INPUT |
sba_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_data[31:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_sink |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_source[7:0] |
Yes |
Yes |
T11,T28,T16 |
Yes |
T11,T27,T28 |
INPUT |
sba_tl_h_i.d_size[1:0] |
Yes |
Yes |
T11,T28,T16 |
Yes |
T11,T28,T16 |
INPUT |
sba_tl_h_i.d_param[2:0] |
Yes |
Yes |
T11,T28,T16 |
Yes |
T11,T28,T16 |
INPUT |
sba_tl_h_i.d_opcode[2:0] |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
INPUT |
sba_tl_h_i.d_valid |
Yes |
Yes |
T1,T3,T11 |
Yes |
T1,T3,T11 |
INPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T27,T29 |
Yes |
T2,T27,T29 |
INPUT |
alert_rx_i[0].ping_n |
No |
No |
|
No |
|
INPUT |
alert_rx_i[0].ping_p |
No |
No |
|
No |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T27,T29 |
Yes |
T2,T27,T29 |
OUTPUT |
jtag_i.tdi |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.trst_n |
Yes |
Yes |
T1,T11,T29 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.tms |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.tck |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_o.tdo_oe |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
jtag_o.tdo |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rv_dm
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
4 |
57.14 |
IF |
320 |
7 |
4 |
57.14 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 320 if ((!rst_ni))
-2-: 325 if ((ndmreset_req && (!ndmreset_pending_q)))
-3-: 327 if ((ndmreset_ack && ndmreset_pending_q))
-4-: 331 if ((ndmreset_pending_q && lc_rst_asserted))
-5-: 333 if ((ndmreset_ack && lc_rst_pending_q))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T20,T21,T12 |
0 |
0 |
1 |
- |
- |
Not Covered |
|
0 |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
0 |
- |
- |
1 |
- |
Not Covered |
|
0 |
- |
- |
0 |
1 |
Not Covered |
|
0 |
- |
- |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rv_dm
Assertion Details
DebugReqOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
DmactiveOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
60 |
0 |
0 |
T5 |
79725 |
0 |
0 |
0 |
T7 |
1970 |
0 |
0 |
0 |
T10 |
5105 |
0 |
0 |
0 |
T16 |
435306 |
0 |
0 |
0 |
T20 |
16313 |
0 |
0 |
0 |
T29 |
14745 |
20 |
0 |
0 |
T30 |
0 |
10 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T32 |
1783 |
0 |
0 |
0 |
T37 |
128608 |
0 |
0 |
0 |
T46 |
8461 |
0 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
T49 |
197756 |
0 |
0 |
0 |
FpvSecCmRomTlLcGateFsm_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
0 |
0 |
0 |
FpvSecCmSbaTlLcGateFsm_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
0 |
0 |
0 |
JtagRspOTdoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9951754 |
9951390 |
0 |
0 |
T1 |
28921 |
28918 |
0 |
0 |
T2 |
112 |
112 |
0 |
0 |
T3 |
90984 |
90984 |
0 |
0 |
T4 |
2727 |
2727 |
0 |
0 |
T5 |
8480 |
8480 |
0 |
0 |
T11 |
78193 |
78184 |
0 |
0 |
T26 |
43253 |
43253 |
0 |
0 |
T27 |
107 |
107 |
0 |
0 |
T28 |
42337 |
42337 |
0 |
0 |
T29 |
2502 |
2502 |
0 |
0 |
JtagRspOTdoOeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9951754 |
9951390 |
0 |
0 |
T1 |
28921 |
28918 |
0 |
0 |
T2 |
112 |
112 |
0 |
0 |
T3 |
90984 |
90984 |
0 |
0 |
T4 |
2727 |
2727 |
0 |
0 |
T5 |
8480 |
8480 |
0 |
0 |
T11 |
78193 |
78184 |
0 |
0 |
T26 |
43253 |
43253 |
0 |
0 |
T27 |
107 |
107 |
0 |
0 |
T28 |
42337 |
42337 |
0 |
0 |
T29 |
2502 |
2502 |
0 |
0 |
NdmresetOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
RvDmLcEnDebugVal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
TlMemAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
TlMemDValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
TlRegsAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
TlRegsDValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
TlSbaAValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
TlSbaDReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20163863 |
20123338 |
0 |
0 |
T1 |
14005 |
13751 |
0 |
0 |
T2 |
957 |
899 |
0 |
0 |
T3 |
174997 |
174933 |
0 |
0 |
T4 |
5180 |
5104 |
0 |
0 |
T5 |
79725 |
79650 |
0 |
0 |
T11 |
205214 |
204562 |
0 |
0 |
T26 |
70439 |
70365 |
0 |
0 |
T27 |
1456 |
1378 |
0 |
0 |
T28 |
222615 |
222557 |
0 |
0 |
T29 |
14745 |
13413 |
0 |
0 |
paramCheckNrHarts
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
164 |
164 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |