Unified Coverage Report :: Module :: prim_mubi8_sync

Module : prim_mubi8_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.82	90.91	61.70	86.87		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[7].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi8_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	4	4

---

Assert Coverage for Module : prim_mubi8_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	164	164	0	0
OutputsKnown_A	20163863	20123338	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	20163863	20121505	0	492

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164	164	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20163863	20123338	0	0
T1	14005	13751	0	0
T2	957	899	0	0
T3	174997	174933	0	0
T4	5180	5104	0	0
T5	79725	79650	0	0
T11	205214	204562	0	0
T26	70439	70365	0	0
T27	1456	1378	0	0
T28	222615	222557	0	0
T29	14745	13413	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20163863	20121505	0	492
T1	14005	13739	0	3
T2	957	896	0	3
T3	174997	174930	0	3
T4	5180	5101	0	3
T5	79725	79647	0	3
T11	205214	204532	0	3
T26	70439	70362	0	3
T27	1456	1375	0	3
T28	222615	222554	0	3
T29	14745	13350	0	3