SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.82 | 90.91 | 61.70 | 86.87 | 57.14 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20163863 | 20123338 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |