SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.82 | 90.91 | 61.70 | 86.87 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.82 | 90.91 | 61.70 | 86.87 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.82 | 90.91 | 61.70 | 86.87 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.82 | 90.91 | 61.70 | 86.87 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
58.07 | 78.43 | 66.67 | 28.57 | 66.67 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
75.72 | 96.08 | 77.78 | 71.43 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 984 | 984 | 0 | 0 |
OutputsKnown_A | 120983178 | 120740028 | 0 | 0 |
gen_flops.OutputDelay_A | 60491589 | 60364515 | 0 | 1476 |
gen_no_flops.OutputDelay_A | 60491589 | 60370014 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 984 | 984 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T26 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 120983178 | 120740028 | 0 | 0 |
T1 | 84030 | 82506 | 0 | 0 |
T2 | 5742 | 5394 | 0 | 0 |
T3 | 1049982 | 1049598 | 0 | 0 |
T4 | 31080 | 30624 | 0 | 0 |
T5 | 478350 | 477900 | 0 | 0 |
T11 | 1231284 | 1227372 | 0 | 0 |
T26 | 422634 | 422190 | 0 | 0 |
T27 | 8736 | 8268 | 0 | 0 |
T28 | 1335690 | 1335342 | 0 | 0 |
T29 | 88470 | 80478 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60491589 | 60364515 | 0 | 1476 |
T1 | 42015 | 41217 | 0 | 9 |
T2 | 2871 | 2688 | 0 | 9 |
T3 | 524991 | 524790 | 0 | 9 |
T4 | 15540 | 15303 | 0 | 9 |
T5 | 239175 | 238941 | 0 | 9 |
T11 | 615642 | 613596 | 0 | 9 |
T26 | 211317 | 211086 | 0 | 9 |
T27 | 4368 | 4125 | 0 | 9 |
T28 | 667845 | 667662 | 0 | 9 |
T29 | 44235 | 40050 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60491589 | 60370014 | 0 | 0 |
T1 | 42015 | 41253 | 0 | 0 |
T2 | 2871 | 2697 | 0 | 0 |
T3 | 524991 | 524799 | 0 | 0 |
T4 | 15540 | 15312 | 0 | 0 |
T5 | 239175 | 238950 | 0 | 0 |
T11 | 615642 | 613686 | 0 | 0 |
T26 | 211317 | 211095 | 0 | 0 |
T27 | 4368 | 4134 | 0 | 0 |
T28 | 667845 | 667671 | 0 | 0 |
T29 | 44235 | 40239 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_flops.OutputDelay_A | 20163863 | 20121505 | 0 | 492 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20121505 | 0 | 492 |
T1 | 14005 | 13739 | 0 | 3 |
T2 | 957 | 896 | 0 | 3 |
T3 | 174997 | 174930 | 0 | 3 |
T4 | 5180 | 5101 | 0 | 3 |
T5 | 79725 | 79647 | 0 | 3 |
T11 | 205214 | 204532 | 0 | 3 |
T26 | 70439 | 70362 | 0 | 3 |
T27 | 1456 | 1375 | 0 | 3 |
T28 | 222615 | 222554 | 0 | 3 |
T29 | 14745 | 13350 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_flops.OutputDelay_A | 20163863 | 20121505 | 0 | 492 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20121505 | 0 | 492 |
T1 | 14005 | 13739 | 0 | 3 |
T2 | 957 | 896 | 0 | 3 |
T3 | 174997 | 174930 | 0 | 3 |
T4 | 5180 | 5101 | 0 | 3 |
T5 | 79725 | 79647 | 0 | 3 |
T11 | 205214 | 204532 | 0 | 3 |
T26 | 70439 | 70362 | 0 | 3 |
T27 | 1456 | 1375 | 0 | 3 |
T28 | 222615 | 222554 | 0 | 3 |
T29 | 14745 | 13350 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20163863 | 20123338 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_flops.OutputDelay_A | 20163863 | 20121505 | 0 | 492 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20121505 | 0 | 492 |
T1 | 14005 | 13739 | 0 | 3 |
T2 | 957 | 896 | 0 | 3 |
T3 | 174997 | 174930 | 0 | 3 |
T4 | 5180 | 5101 | 0 | 3 |
T5 | 79725 | 79647 | 0 | 3 |
T11 | 205214 | 204532 | 0 | 3 |
T26 | 70439 | 70362 | 0 | 3 |
T27 | 1456 | 1375 | 0 | 3 |
T28 | 222615 | 222554 | 0 | 3 |
T29 | 14745 | 13350 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20163863 | 20123338 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 164 | 164 | 0 | 0 |
OutputsKnown_A | 20163863 | 20123338 | 0 | 0 |
gen_no_flops.OutputDelay_A | 20163863 | 20123338 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 164 | 164 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 20163863 | 20123338 | 0 | 0 |
T1 | 14005 | 13751 | 0 | 0 |
T2 | 957 | 899 | 0 | 0 |
T3 | 174997 | 174933 | 0 | 0 |
T4 | 5180 | 5104 | 0 | 0 |
T5 | 79725 | 79650 | 0 | 0 |
T11 | 205214 | 204562 | 0 | 0 |
T26 | 70439 | 70365 | 0 | 0 |
T27 | 1456 | 1378 | 0 | 0 |
T28 | 222615 | 222557 | 0 | 0 |
T29 | 14745 | 13413 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |