Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	205243	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	559266	1		T2	6		T4	2		T5	26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	485013	1		T2	8		T5	8		T6	32
values[0x0]	137619	1		T2	1		T4	4		T5	26
values[0x1]	141877	1		T4	6		T5	36		T6	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156309	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	608200	1		T2	7		T4	4		T5	31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2629	1		T15	1		T80	1		T140	3
valid_sources[0x01]	2662	1		T33	44		T35	2		T34	3
valid_sources[0x02]	3169	1		T7	42		T54	1		T33	49
valid_sources[0x03]	2737	1		T14	3		T80	3		T19	2
valid_sources[0x04]	3556	1		T5	1		T55	1		T33	44
valid_sources[0x05]	2826	1		T72	1		T15	1		T28	3
valid_sources[0x06]	2937	1		T15	1		T141	2		T33	24
valid_sources[0x07]	4844	1		T5	2		T57	1		T15	3
valid_sources[0x08]	2815	1		T15	2		T19	1		T32	6
valid_sources[0x09]	2989	1		T33	57		T35	2		T34	3
valid_sources[0x0a]	2875	1		T14	6		T15	2		T32	9
valid_sources[0x0b]	2991	1		T50	1		T15	1		T80	1
valid_sources[0x0c]	2469	1		T141	1		T33	30		T35	4
valid_sources[0x0d]	3154	1		T15	1		T33	50		T35	5
valid_sources[0x0e]	2527	1		T15	5		T32	4		T33	42
valid_sources[0x0f]	3124	1		T55	3		T15	1		T54	1
valid_sources[0x10]	2797	1		T6	4		T54	1		T32	3
valid_sources[0x11]	2792	1		T50	5		T33	52		T35	1
valid_sources[0x12]	2671	1		T57	1		T15	2		T80	1
valid_sources[0x13]	2633	1		T80	1		T33	55		T35	2
valid_sources[0x14]	3617	1		T14	4		T27	1		T53	2
valid_sources[0x15]	2734	1		T72	1		T80	1		T33	27
valid_sources[0x16]	2796	1		T5	1		T8	1		T15	2
valid_sources[0x17]	2561	1		T15	1		T80	1		T32	3
valid_sources[0x18]	2873	1		T50	1		T80	2		T142	1
valid_sources[0x19]	2623	1		T15	1		T33	64		T35	5
valid_sources[0x1a]	3138	1		T5	1		T50	1		T15	2
valid_sources[0x1b]	2636	1		T6	4		T19	1		T33	51
valid_sources[0x1c]	2964	1		T54	2		T33	51		T35	4
valid_sources[0x1d]	2418	1		T6	4		T33	64		T35	3
valid_sources[0x1e]	2435	1		T28	6		T80	1		T19	2
valid_sources[0x1f]	2750	1		T6	2		T14	1		T54	1
valid_sources[0x20]	3266	1		T72	1		T50	1		T80	1
valid_sources[0x21]	2686	1		T15	1		T54	1		T33	33
valid_sources[0x22]	2199	1		T14	1		T19	1		T54	2
valid_sources[0x23]	3150	1		T50	1		T15	1		T33	32
valid_sources[0x24]	2765	1		T4	1		T50	5		T15	1
valid_sources[0x25]	2620	1		T14	1		T15	1		T140	6
valid_sources[0x26]	3774	1		T14	1		T19	1		T33	63
valid_sources[0x27]	2504	1		T15	2		T80	1		T54	2
valid_sources[0x28]	2717	1		T50	2		T15	1		T80	1
valid_sources[0x29]	2373	1		T15	2		T142	1		T33	32
valid_sources[0x2a]	2526	1		T15	1		T33	63		T35	1
valid_sources[0x2b]	2849	1		T58	1		T15	3		T33	45
valid_sources[0x2c]	6133	1		T72	1		T50	1		T56	1
valid_sources[0x2d]	2829	1		T72	1		T140	2		T32	1
valid_sources[0x2e]	2355	1		T15	1		T33	25		T35	1
valid_sources[0x2f]	2630	1		T54	1		T33	28		T35	2
valid_sources[0x30]	2409	1		T5	1		T14	5		T19	1
valid_sources[0x31]	2842	1		T54	1		T33	66		T35	4
valid_sources[0x32]	2609	1		T14	3		T50	1		T15	1
valid_sources[0x33]	3024	1		T72	1		T15	1		T33	13
valid_sources[0x34]	3292	1		T33	50		T35	2		T34	2
valid_sources[0x35]	2543	1		T33	40		T35	3		T34	3
valid_sources[0x36]	2851	1		T50	1		T15	2		T33	58
valid_sources[0x37]	2559	1		T50	1		T15	2		T32	138
valid_sources[0x38]	2356	1		T6	1		T143	1		T142	2
valid_sources[0x39]	2753	1		T50	1		T15	4		T19	1
valid_sources[0x3a]	2468	1		T14	4		T50	2		T54	1
valid_sources[0x3b]	2359	1		T50	2		T19	1		T54	2
valid_sources[0x3c]	2740	1		T32	1		T33	70		T35	2
valid_sources[0x3d]	2516	1		T6	3		T15	1		T33	42
valid_sources[0x3e]	2722	1		T33	99		T35	1		T34	3
valid_sources[0x3f]	2954	1		T5	1		T14	1		T15	3
valid_sources[0x40]	2446	1		T14	1		T50	1		T15	1
valid_sources[0x41]	2514	1		T6	5		T57	1		T32	2
valid_sources[0x42]	2097	1		T5	1		T54	1		T32	18
valid_sources[0x43]	9344	1		T14	5		T15	3		T54	1
valid_sources[0x44]	2689	1		T32	2		T33	48		T35	5
valid_sources[0x45]	2529	1		T5	3		T80	1		T33	31
valid_sources[0x46]	2486	1		T14	2		T15	2		T33	55
valid_sources[0x47]	2799	1		T5	1		T6	3		T141	1
valid_sources[0x48]	2883	1		T33	30		T35	3		T34	6
valid_sources[0x49]	2423	1		T6	2		T8	1		T15	1
valid_sources[0x4a]	3463	1		T14	2		T54	1		T33	59
valid_sources[0x4b]	2814	1		T15	1		T28	12		T143	3
valid_sources[0x4c]	2581	1		T15	1		T142	2		T33	23
valid_sources[0x4d]	9094	1		T15	1		T54	1		T32	1
valid_sources[0x4e]	2609	1		T50	1		T15	2		T142	2
valid_sources[0x4f]	2365	1		T80	1		T33	30		T35	3
valid_sources[0x50]	3279	1		T8	2		T15	1		T32	9
valid_sources[0x51]	3133	1		T20	2		T33	47		T35	4
valid_sources[0x52]	2831	1		T142	2		T33	48		T35	1
valid_sources[0x53]	12889	1		T8	8		T55	1		T15	1
valid_sources[0x54]	2275	1		T54	1		T32	2		T33	60
valid_sources[0x55]	2086	1		T6	3		T14	1		T50	1
valid_sources[0x56]	2597	1		T33	39		T35	1		T34	4
valid_sources[0x57]	2409	1		T142	1		T33	39		T35	4
valid_sources[0x58]	2718	1		T50	1		T15	3		T80	1
valid_sources[0x59]	2935	1		T8	2		T15	1		T80	1
valid_sources[0x5a]	7761	1		T54	1		T33	49		T35	6
valid_sources[0x5b]	2182	1		T14	4		T19	1		T54	1
valid_sources[0x5c]	3058	1		T5	3		T58	2		T15	1
valid_sources[0x5d]	2758	1		T54	1		T33	57		T35	5
valid_sources[0x5e]	2825	1		T50	1		T15	1		T33	41
valid_sources[0x5f]	2945	1		T58	2		T50	1		T19	1
valid_sources[0x60]	3058	1		T80	2		T33	27		T35	3
valid_sources[0x61]	2859	1		T15	2		T33	56		T35	2
valid_sources[0x62]	2483	1		T32	3		T33	34		T35	2
valid_sources[0x63]	2701	1		T27	2		T33	49		T35	4
valid_sources[0x64]	4114	1		T8	1		T14	3		T15	3
valid_sources[0x65]	2914	1		T14	8		T57	1		T54	1
valid_sources[0x66]	2739	1		T5	1		T50	1		T15	1
valid_sources[0x67]	2386	1		T14	1		T15	1		T54	2
valid_sources[0x68]	2766	1		T140	2		T54	3		T32	3
valid_sources[0x69]	2576	1		T56	1		T33	35		T35	2
valid_sources[0x6a]	2394	1		T33	13		T35	3		T34	4
valid_sources[0x6b]	2499	1		T5	1		T19	3		T32	3
valid_sources[0x6c]	2882	1		T50	2		T15	1		T28	1
valid_sources[0x6d]	2440	1		T6	5		T15	2		T33	40
valid_sources[0x6e]	2366	1		T50	1		T15	2		T143	1
valid_sources[0x6f]	2691	1		T33	59		T35	1		T34	3
valid_sources[0x70]	2386	1		T50	1		T28	2		T33	26
valid_sources[0x71]	3116	1		T50	2		T54	1		T32	2
valid_sources[0x72]	2682	1		T15	2		T32	9		T33	58
valid_sources[0x73]	2968	1		T58	3		T15	1		T33	15
valid_sources[0x74]	3373	1		T57	1		T15	2		T80	1
valid_sources[0x75]	3361	1		T50	1		T56	2		T15	1
valid_sources[0x76]	2235	1		T8	1		T54	1		T33	33
valid_sources[0x77]	2787	1		T5	3		T14	1		T19	1
valid_sources[0x78]	2213	1		T33	21		T35	2		T34	4
valid_sources[0x79]	2588	1		T6	2		T50	1		T15	1
valid_sources[0x7a]	3038	1		T32	9		T33	49		T35	3
valid_sources[0x7b]	2426	1		T14	2		T15	1		T80	1
valid_sources[0x7c]	2199	1		T15	2		T32	20		T33	43
valid_sources[0x7d]	2777	1		T5	6		T8	2		T14	1
valid_sources[0x7e]	2799	1		T33	7		T35	1		T34	2
valid_sources[0x7f]	2423	1		T8	1		T55	1		T56	1
valid_sources[0x80]	2784	1		T8	2		T14	2		T54	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

287486

1

T2

6

T5

5

T6

15

values[0x0]

all_enables

biggest_size

135838

1

T4

1

T5

13

T6

21

values[0x1]

all_enables

biggest_size

135942

1

T4

1

T5

8

T6

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5512	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16919	1		T1	2		T24	1		T25	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10088	1		T32	200		T33	67		T35	123
values[0x0]	6143	1		T1	11		T24	3		T25	1
values[0x1]	6200	1		T1	5		T24	6		T25	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4249	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18182	1		T1	3		T24	1		T25	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63	1		T144	1		T32	3		T78	1
valid_sources[0x01]	102	1		T145	1		T32	2		T73	1
valid_sources[0x02]	69	1		T146	8		T32	1		T66	2
valid_sources[0x03]	59	1		T32	3		T66	2		T76	1
valid_sources[0x04]	63	1		T32	6		T35	3		T66	3
valid_sources[0x05]	82	1		T32	6		T33	7		T35	1
valid_sources[0x06]	70	1		T147	1		T148	1		T36	2
valid_sources[0x07]	71	1		T69	3		T32	1		T35	1
valid_sources[0x08]	55	1		T144	1		T35	2		T73	1
valid_sources[0x09]	90	1		T32	3		T35	5		T78	1
valid_sources[0x0a]	98	1		T45	1		T32	4		T34	1
valid_sources[0x0b]	75	1		T32	5		T35	4		T66	1
valid_sources[0x0c]	62	1		T29	1		T32	6		T35	3
valid_sources[0x0d]	49	1		T32	4		T35	2		T66	1
valid_sources[0x0e]	57	1		T148	1		T32	1		T35	1
valid_sources[0x0f]	67	1		T119	1		T32	5		T91	1
valid_sources[0x10]	78	1		T32	8		T35	4		T76	1
valid_sources[0x11]	65	1		T32	3		T35	3		T73	1
valid_sources[0x12]	66	1		T123	1		T32	1		T92	2
valid_sources[0x13]	185	1		T44	1		T71	4		T32	3
valid_sources[0x14]	48	1		T35	1		T77	3		T91	1
valid_sources[0x15]	64	1		T70	3		T66	3		T73	4
valid_sources[0x16]	125	1		T32	4		T35	1		T73	1
valid_sources[0x17]	93	1		T32	3		T35	2		T34	1
valid_sources[0x18]	89	1		T29	1		T32	5		T66	2
valid_sources[0x19]	73	1		T145	1		T149	2		T32	7
valid_sources[0x1a]	140	1		T45	1		T79	1		T35	3
valid_sources[0x1b]	81	1		T150	1		T144	1		T32	4
valid_sources[0x1c]	94	1		T151	1		T32	2		T35	2
valid_sources[0x1d]	81	1		T24	5		T32	3		T35	1
valid_sources[0x1e]	78	1		T32	3		T36	2		T66	2
valid_sources[0x1f]	62	1		T32	3		T35	3		T73	5
valid_sources[0x20]	94	1		T152	1		T32	5		T34	1
valid_sources[0x21]	106	1		T32	1		T35	2		T66	2
valid_sources[0x22]	64	1		T32	4		T35	2		T73	2
valid_sources[0x23]	67	1		T153	7		T32	3		T74	3
valid_sources[0x24]	81	1		T1	1		T32	4		T35	2
valid_sources[0x25]	124	1		T32	4		T33	3		T35	3
valid_sources[0x26]	103	1		T154	18		T32	5		T35	3
valid_sources[0x27]	71	1		T32	6		T73	3		T78	1
valid_sources[0x28]	67	1		T153	1		T32	5		T35	5
valid_sources[0x29]	64	1		T144	1		T32	6		T35	1
valid_sources[0x2a]	73	1		T32	5		T35	7		T73	2
valid_sources[0x2b]	161	1		T32	2		T73	2		T91	1
valid_sources[0x2c]	80	1		T25	1		T45	1		T32	4
valid_sources[0x2d]	107	1		T145	1		T155	7		T32	3
valid_sources[0x2e]	106	1		T32	2		T66	1		T77	1
valid_sources[0x2f]	71	1		T32	3		T91	1		T78	1
valid_sources[0x30]	120	1		T32	3		T35	1		T73	1
valid_sources[0x31]	187	1		T30	2		T156	2		T32	6
valid_sources[0x32]	62	1		T32	3		T35	2		T36	12
valid_sources[0x33]	76	1		T1	1		T32	5		T35	3
valid_sources[0x34]	88	1		T32	2		T35	1		T36	16
valid_sources[0x35]	106	1		T157	2		T32	1		T35	2
valid_sources[0x36]	62	1		T32	5		T35	1		T73	1
valid_sources[0x37]	95	1		T32	2		T35	6		T128	3
valid_sources[0x38]	74	1		T1	1		T32	5		T35	9
valid_sources[0x39]	81	1		T32	3		T35	2		T36	3
valid_sources[0x3a]	112	1		T1	1		T150	2		T32	1
valid_sources[0x3b]	53	1		T1	1		T150	3		T35	1
valid_sources[0x3c]	135	1		T120	9		T32	7		T35	2
valid_sources[0x3d]	75	1		T32	1		T35	1		T73	1
valid_sources[0x3e]	72	1		T32	1		T66	2		T73	1
valid_sources[0x3f]	72	1		T158	2		T32	2		T35	2
valid_sources[0x40]	61	1		T32	6		T35	1		T76	1
valid_sources[0x41]	67	1		T147	2		T32	4		T35	1
valid_sources[0x42]	76	1		T157	1		T32	8		T66	1
valid_sources[0x43]	202	1		T119	1		T124	2		T148	1
valid_sources[0x44]	72	1		T1	1		T45	1		T32	5
valid_sources[0x45]	72	1		T32	3		T73	1		T74	10
valid_sources[0x46]	127	1		T32	1		T78	2		T92	3
valid_sources[0x47]	115	1		T45	2		T150	4		T32	2
valid_sources[0x48]	103	1		T24	1		T32	1		T35	5
valid_sources[0x49]	68	1		T32	3		T33	5		T35	4
valid_sources[0x4a]	83	1		T147	1		T32	1		T35	3
valid_sources[0x4b]	70	1		T35	3		T73	2		T77	1
valid_sources[0x4c]	78	1		T32	3		T78	2		T92	1
valid_sources[0x4d]	99	1		T151	1		T32	7		T36	8
valid_sources[0x4e]	84	1		T147	1		T32	5		T35	1
valid_sources[0x4f]	72	1		T156	1		T159	1		T32	6
valid_sources[0x50]	88	1		T32	2		T33	1		T35	1
valid_sources[0x51]	70	1		T32	3		T35	3		T73	1
valid_sources[0x52]	74	1		T29	1		T32	5		T35	3
valid_sources[0x53]	57	1		T25	1		T70	2		T32	3
valid_sources[0x54]	80	1		T150	1		T159	1		T160	10
valid_sources[0x55]	58	1		T71	2		T161	2		T32	7
valid_sources[0x56]	72	1		T151	1		T123	1		T32	2
valid_sources[0x57]	50	1		T32	1		T35	1		T34	1
valid_sources[0x58]	80	1		T79	1		T162	1		T163	1
valid_sources[0x59]	59	1		T1	1		T71	6		T164	1
valid_sources[0x5a]	70	1		T1	1		T79	1		T32	6
valid_sources[0x5b]	107	1		T44	2		T32	3		T92	1
valid_sources[0x5c]	89	1		T165	14		T32	4		T35	12
valid_sources[0x5d]	58	1		T32	9		T35	1		T34	1
valid_sources[0x5e]	114	1		T32	3		T73	1		T75	42
valid_sources[0x5f]	81	1		T148	1		T32	4		T35	3
valid_sources[0x60]	100	1		T32	1		T35	2		T73	1
valid_sources[0x61]	93	1		T32	4		T35	3		T73	2
valid_sources[0x62]	76	1		T32	7		T73	1		T92	3
valid_sources[0x63]	56	1		T32	3		T66	1		T91	1
valid_sources[0x64]	86	1		T25	1		T71	1		T144	1
valid_sources[0x65]	102	1		T1	1		T29	1		T123	3
valid_sources[0x66]	54	1		T45	1		T32	4		T35	6
valid_sources[0x67]	54	1		T157	1		T148	1		T32	1
valid_sources[0x68]	215	1		T32	5		T35	2		T66	1
valid_sources[0x69]	58	1		T32	2		T35	1		T92	3
valid_sources[0x6a]	61	1		T45	2		T32	4		T66	1
valid_sources[0x6b]	64	1		T32	3		T35	1		T73	3
valid_sources[0x6c]	51	1		T144	1		T81	1		T92	1
valid_sources[0x6d]	91	1		T33	11		T35	2		T73	1
valid_sources[0x6e]	87	1		T144	1		T32	4		T35	5
valid_sources[0x6f]	77	1		T151	1		T161	4		T32	4
valid_sources[0x70]	57	1		T32	2		T35	2		T78	2
valid_sources[0x71]	79	1		T32	2		T33	7		T73	1
valid_sources[0x72]	64	1		T32	6		T35	1		T81	2
valid_sources[0x73]	124	1		T164	1		T32	2		T35	3
valid_sources[0x74]	84	1		T45	1		T166	7		T148	1
valid_sources[0x75]	112	1		T45	1		T35	3		T36	4
valid_sources[0x76]	117	1		T32	3		T35	1		T75	41
valid_sources[0x77]	104	1		T32	6		T35	2		T92	3
valid_sources[0x78]	64	1		T32	7		T35	4		T36	2
valid_sources[0x79]	76	1		T163	1		T32	1		T35	3
valid_sources[0x7a]	58	1		T79	1		T32	3		T73	1
valid_sources[0x7b]	129	1		T32	4		T34	1		T66	6
valid_sources[0x7c]	57	1		T161	1		T32	5		T73	1
valid_sources[0x7d]	50	1		T167	3		T32	1		T66	1
valid_sources[0x7e]	72	1		T151	1		T168	4		T32	5
valid_sources[0x7f]	56	1		T164	1		T32	2		T35	1
valid_sources[0x80]	87	1		T151	1		T157	1		T144	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6525

1

T32

195

T33

22

T35

114

values[0x0]

all_enables

biggest_size

5346

1

T1

1

T25

1

T29

2

values[0x1]

all_enables

biggest_size

5048

1

T1

1

T24

1

T44

3