Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	235060	1		T2	3		T4	8		T5	44
full_word	560418	1		T2	6		T4	2		T5	26

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	795158	1		T2	9		T4	10		T5	70
auto[TlIntgErrCmd]	107	1		T33	12		T66	8		T74	3
auto[TlIntgErrData]	114	1		T33	5		T66	5		T74	5
auto[TlIntgErrBoth]	99	1		T33	3		T66	7		T74	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	486357	1		T2	8		T5	8		T6	32
auto[1]	309121	1		T2	1		T4	10		T5	62

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	198611	1		T2	2		T5	3		T6	17
auto[TlIntgErrNone]	partial	auto[1]	36150	1		T2	1		T4	8		T5	41
auto[TlIntgErrNone]	full_word	auto[0]	287600	1		T2	6		T5	5		T6	15
auto[TlIntgErrNone]	full_word	auto[1]	272797	1		T4	2		T5	21		T6	31
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T33	4		T66	4		T74	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T33	8		T66	4		T91	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T128	1		T133	1		T134	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T91	1		T132	1		T135	1
auto[TlIntgErrData]	partial	auto[0]	57	1		T33	3		T66	2		T91	1
auto[TlIntgErrData]	partial	auto[1]	52	1		T33	2		T66	2		T74	5
auto[TlIntgErrData]	full_word	auto[0]	4	1		T66	1		T128	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T136	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T33	2		T66	3		T128	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T33	1		T66	4		T74	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T137	1		T131	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T127	1		T138	1		T130	1