Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.11	93.64	80.05	87.69	71.79	82.01	98.52	47.05

Total test records in report: 314

T257	/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3728466382	Apr 18 01:23:15 PM PDT 24	Apr 18 01:23:36 PM PDT 24	3511756037 ps
T258	/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2691653302	Apr 18 01:23:43 PM PDT 24	Apr 18 01:23:46 PM PDT 24	90599381 ps
T259	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.77509723	Apr 18 01:23:09 PM PDT 24	Apr 18 01:23:11 PM PDT 24	850979354 ps
T96	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4159515750	Apr 18 01:23:25 PM PDT 24	Apr 18 01:23:30 PM PDT 24	639797327 ps
T134	/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4162810347	Apr 18 01:23:12 PM PDT 24	Apr 18 01:23:20 PM PDT 24	250692290 ps
T260	/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3946826174	Apr 18 01:23:51 PM PDT 24	Apr 18 01:23:53 PM PDT 24	40393787 ps
T261	/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3375995027	Apr 18 01:23:32 PM PDT 24	Apr 18 01:23:35 PM PDT 24	2069100929 ps
T262	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2474200821	Apr 18 01:23:40 PM PDT 24	Apr 18 01:23:42 PM PDT 24	73295121 ps
T136	/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.43310584	Apr 18 01:23:42 PM PDT 24	Apr 18 01:23:59 PM PDT 24	884015620 ps
T263	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3534428204	Apr 18 01:23:44 PM PDT 24	Apr 18 01:23:45 PM PDT 24	68241385 ps
T264	/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.494268944	Apr 18 01:23:46 PM PDT 24	Apr 18 01:23:50 PM PDT 24	146808040 ps
T135	/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1926805291	Apr 18 01:23:44 PM PDT 24	Apr 18 01:23:53 PM PDT 24	220777569 ps
T265	/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1122358929	Apr 18 01:23:28 PM PDT 24	Apr 18 01:23:33 PM PDT 24	1399458759 ps
T266	/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.170914469	Apr 18 01:23:35 PM PDT 24	Apr 18 01:23:44 PM PDT 24	320007711 ps
T267	/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1934901110	Apr 18 01:23:28 PM PDT 24	Apr 18 01:23:32 PM PDT 24	370800120 ps
T268	/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2159955691	Apr 18 01:23:20 PM PDT 24	Apr 18 01:23:25 PM PDT 24	339727465 ps
T269	/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.35165846	Apr 18 01:23:44 PM PDT 24	Apr 18 01:23:51 PM PDT 24	509284458 ps
T270	/workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.476108516	Apr 18 01:23:30 PM PDT 24	Apr 18 01:24:16 PM PDT 24	13919279534 ps
T137	/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.683355762	Apr 18 01:23:55 PM PDT 24	Apr 18 01:24:16 PM PDT 24	1517276481 ps
T271	/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.419771287	Apr 18 01:23:25 PM PDT 24	Apr 18 01:23:30 PM PDT 24	132304534 ps
T272	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4138128730	Apr 18 01:23:14 PM PDT 24	Apr 18 01:23:15 PM PDT 24	66332327 ps
T273	/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1827586343	Apr 18 01:23:38 PM PDT 24	Apr 18 01:23:46 PM PDT 24	419464237 ps
T274	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.777596036	Apr 18 01:23:26 PM PDT 24	Apr 18 01:25:38 PM PDT 24	48752158264 ps
T275	/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.671084051	Apr 18 01:23:42 PM PDT 24	Apr 18 01:23:45 PM PDT 24	84235483 ps
T276	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1969825021	Apr 18 01:23:54 PM PDT 24	Apr 18 01:23:55 PM PDT 24	38708202 ps
T277	/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.937730926	Apr 18 01:23:34 PM PDT 24	Apr 18 01:23:36 PM PDT 24	114088634 ps
T278	/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.903089961	Apr 18 01:23:55 PM PDT 24	Apr 18 01:24:00 PM PDT 24	880882573 ps
T279	/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3064940161	Apr 18 01:23:28 PM PDT 24	Apr 18 01:23:31 PM PDT 24	118129896 ps
T280	/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.929496419	Apr 18 01:23:15 PM PDT 24	Apr 18 01:23:17 PM PDT 24	240922504 ps
T281	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4093026468	Apr 18 01:23:25 PM PDT 24	Apr 18 01:23:45 PM PDT 24	8753167293 ps
T282	/workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3632545613	Apr 18 01:23:51 PM PDT 24	Apr 18 01:24:03 PM PDT 24	23396605680 ps
T283	/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3480356672	Apr 18 01:23:31 PM PDT 24	Apr 18 01:23:40 PM PDT 24	408755092 ps
T284	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2347115003	Apr 18 01:23:15 PM PDT 24	Apr 18 01:23:17 PM PDT 24	117266225 ps
T285	/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3835548561	Apr 18 01:23:11 PM PDT 24	Apr 18 01:24:17 PM PDT 24	2324471440 ps
T286	/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2414262355	Apr 18 01:23:38 PM PDT 24	Apr 18 01:23:41 PM PDT 24	58895036 ps
T287	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2510027912	Apr 18 01:23:23 PM PDT 24	Apr 18 01:23:51 PM PDT 24	12171578944 ps
T288	/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.913444151	Apr 18 01:23:41 PM PDT 24	Apr 18 01:23:44 PM PDT 24	886924214 ps
T289	/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1757373100	Apr 18 01:23:34 PM PDT 24	Apr 18 01:23:35 PM PDT 24	45751478 ps
T290	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1073357686	Apr 18 01:23:54 PM PDT 24	Apr 18 01:23:56 PM PDT 24	423524767 ps
T291	/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2566408496	Apr 18 01:23:40 PM PDT 24	Apr 18 01:23:45 PM PDT 24	596506546 ps
T292	/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1817857587	Apr 18 01:23:23 PM PDT 24	Apr 18 01:23:28 PM PDT 24	219477295 ps
T293	/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2431921229	Apr 18 01:23:46 PM PDT 24	Apr 18 01:23:56 PM PDT 24	2668376142 ps
T294	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3204368743	Apr 18 01:23:35 PM PDT 24	Apr 18 01:23:37 PM PDT 24	28620357 ps
T295	/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1179203003	Apr 18 01:23:42 PM PDT 24	Apr 18 01:23:51 PM PDT 24	882849202 ps
T296	/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2903246126	Apr 18 01:23:51 PM PDT 24	Apr 18 01:23:57 PM PDT 24	99836003 ps
T297	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.544789702	Apr 18 01:23:34 PM PDT 24	Apr 18 01:23:36 PM PDT 24	106499477 ps
T97	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.88755486	Apr 18 01:23:24 PM PDT 24	Apr 18 01:23:26 PM PDT 24	224052340 ps
T298	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4236631386	Apr 18 01:23:48 PM PDT 24	Apr 18 01:23:51 PM PDT 24	1038615856 ps
T299	/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.103272568	Apr 18 01:23:43 PM PDT 24	Apr 18 01:23:46 PM PDT 24	590799811 ps
T300	/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.241621557	Apr 18 01:23:44 PM PDT 24	Apr 18 01:23:48 PM PDT 24	86369830 ps
T301	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.251637866	Apr 18 01:23:46 PM PDT 24	Apr 18 01:23:48 PM PDT 24	517308267 ps
T302	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.538937307	Apr 18 01:23:56 PM PDT 24	Apr 18 01:23:58 PM PDT 24	534612944 ps
T303	/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1008084182	Apr 18 01:23:21 PM PDT 24	Apr 18 01:23:23 PM PDT 24	295640008 ps
T304	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2372209154	Apr 18 01:23:46 PM PDT 24	Apr 18 01:23:47 PM PDT 24	54645371 ps
T305	/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2922213874	Apr 18 01:23:24 PM PDT 24	Apr 18 01:23:26 PM PDT 24	21323664 ps
T306	/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3791104753	Apr 18 01:23:17 PM PDT 24	Apr 18 01:23:24 PM PDT 24	571743508 ps
T307	/workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2831021606	Apr 18 01:23:39 PM PDT 24	Apr 18 01:23:59 PM PDT 24	11453401043 ps
T308	/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2183985114	Apr 18 01:23:10 PM PDT 24	Apr 18 01:23:12 PM PDT 24	110201446 ps
T309	/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1875939524	Apr 18 01:23:34 PM PDT 24	Apr 18 01:23:37 PM PDT 24	128589365 ps
T310	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4223416246	Apr 18 01:23:54 PM PDT 24	Apr 18 01:23:55 PM PDT 24	111664911 ps
T311	/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.991851216	Apr 18 01:23:48 PM PDT 24	Apr 18 01:23:51 PM PDT 24	72062198 ps
T312	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.518615962	Apr 18 01:23:44 PM PDT 24	Apr 18 01:23:47 PM PDT 24	452740436 ps
T313	/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4213686731	Apr 18 01:23:49 PM PDT 24	Apr 18 01:23:53 PM PDT 24	1056519145 ps
T314	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1300323692	Apr 18 01:23:27 PM PDT 24	Apr 18 01:24:33 PM PDT 24	22125070409 ps

Test location	/workspace/coverage/default/0.rv_dm_cmderr_not_supported.2757289768
Short name	T1
Test name
Test status
Simulation time	6075723635 ps
CPU time	3.43 seconds
Started	Apr 18 01:25:47 PM PDT 24
Finished	Apr 18 01:25:52 PM PDT 24
Peak memory	205420 kb
Host	smart-a712bdbe-a265-40dd-b913-ae4ff059ef66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2757289768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2757289768
Directory	/workspace/0.rv_dm_cmderr_not_supported/latest

Test location	/workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1915469471
Short name	T27
Test name
Test status
Simulation time	9440955768 ps
CPU time	20.98 seconds
Started	Apr 18 01:26:11 PM PDT 24
Finished	Apr 18 01:26:33 PM PDT 24
Peak memory	213680 kb
Host	smart-fa71f589-0b88-4d74-a4d7-4892a52d9b41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915469471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1915469471
Directory	/workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1826767489
Short name	T68
Test name
Test status
Simulation time	4980201488 ps
CPU time	5.33 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:34 PM PDT 24
Peak memory	218580 kb
Host	smart-93f5b86b-cf65-4ce6-9bd7-ef0c2487b6b5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826767489 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1826767489
Directory	/workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/37.rv_dm_alert_test.1988159129
Short name	T39
Test name
Test status
Simulation time	34201428 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:34 PM PDT 24
Finished	Apr 18 01:26:35 PM PDT 24
Peak memory	205088 kb
Host	smart-f72e4c47-dfae-4d66-89df-8d692d3dc3dd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988159129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1988159129
Directory	/workspace/37.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/47.rv_dm_stress_all.778225076
Short name	T8
Test name
Test status
Simulation time	10974782859 ps
CPU time	19.25 seconds
Started	Apr 18 01:26:43 PM PDT 24
Finished	Apr 18 01:27:03 PM PDT 24
Peak memory	205476 kb
Host	smart-16f9acf0-8077-4623-bf62-30db4ff7a1ab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778225076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.778225076
Directory	/workspace/47.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3786944170
Short name	T72
Test name
Test status
Simulation time	12240594165 ps
CPU time	15.32 seconds
Started	Apr 18 01:23:46 PM PDT 24
Finished	Apr 18 01:24:01 PM PDT 24
Peak memory	220840 kb
Host	smart-b4fb8d41-3abd-4985-816e-c8c4bd096d47
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786944170 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3786944170
Directory	/workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/default/38.rv_dm_stress_all.4194819253
Short name	T11
Test name
Test status
Simulation time	2428857539 ps
CPU time	4.38 seconds
Started	Apr 18 01:26:37 PM PDT 24
Finished	Apr 18 01:26:42 PM PDT 24
Peak memory	205408 kb
Host	smart-2e0a5beb-feda-401d-aa05-1a459c739f25
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194819253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.4194819253
Directory	/workspace/38.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2142746924
Short name	T127
Test name
Test status
Simulation time	1568031213 ps
CPU time	20.05 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	217636 kb
Host	smart-f80e9b56-cca7-41a8-8aa8-0a57c8c609d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142746924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2142746924
Directory	/workspace/4.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1745670237
Short name	T76
Test name
Test status
Simulation time	51487161 ps
CPU time	2.34 seconds
Started	Apr 18 01:23:34 PM PDT 24
Finished	Apr 18 01:23:37 PM PDT 24
Peak memory	219132 kb
Host	smart-df28c2c4-6e21-4956-983b-732779693f21
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745670237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1745670237
Directory	/workspace/8.rv_dm_csr_rw/latest

Test location	/workspace/coverage/default/13.rv_dm_sba_tl_access.3162019885
Short name	T26
Test name
Test status
Simulation time	1519058290 ps
CPU time	4.06 seconds
Started	Apr 18 01:26:21 PM PDT 24
Finished	Apr 18 01:26:26 PM PDT 24
Peak memory	205392 kb
Host	smart-8a4fda49-f394-46a4-9e38-fc9b1d969a75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162019885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3162019885
Directory	/workspace/13.rv_dm_sba_tl_access/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.898850229
Short name	T99
Test name
Test status
Simulation time	3054971728 ps
CPU time	66.07 seconds
Started	Apr 18 01:23:09 PM PDT 24
Finished	Apr 18 01:24:15 PM PDT 24
Peak memory	213176 kb
Host	smart-e84f1b3a-a35b-492f-a95c-8e8e37790f9c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898850229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.rv_dm_csr_aliasing.898850229
Directory	/workspace/0.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/default/1.rv_dm_rom_read_access.4204863531
Short name	T13
Test name
Test status
Simulation time	23639990 ps
CPU time	0.89 seconds
Started	Apr 18 01:26:02 PM PDT 24
Finished	Apr 18 01:26:03 PM PDT 24
Peak memory	213340 kb
Host	smart-a29db865-8c9b-4d34-8fba-eb00f3fc7759
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204863531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.4204863531
Directory	/workspace/1.rv_dm_rom_read_access/latest

Test location	/workspace/coverage/default/4.rv_dm_sec_cm.2683387466
Short name	T32
Test name
Test status
Simulation time	464856796 ps
CPU time	1.33 seconds
Started	Apr 18 01:26:06 PM PDT 24
Finished	Apr 18 01:26:08 PM PDT 24
Peak memory	229372 kb
Host	smart-fd4566d6-5bc2-4c50-bd3c-30715ac4722c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683387466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2683387466
Directory	/workspace/4.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2034760955
Short name	T29
Test name
Test status
Simulation time	16546191016 ps
CPU time	35.29 seconds
Started	Apr 18 01:26:18 PM PDT 24
Finished	Apr 18 01:26:54 PM PDT 24
Peak memory	213688 kb
Host	smart-706abf99-3277-4cd3-90ec-3a1891c828a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034760955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2034760955
Directory	/workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspace/coverage/default/0.rv_dm_cmderr_exception.2531247479
Short name	T19
Test name
Test status
Simulation time	405694277 ps
CPU time	1.59 seconds
Started	Apr 18 01:25:43 PM PDT 24
Finished	Apr 18 01:25:45 PM PDT 24
Peak memory	205152 kb
Host	smart-ada68aec-42ac-4740-9c81-4cf214287a7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531247479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2531247479
Directory	/workspace/0.rv_dm_cmderr_exception/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3470457847
Short name	T130
Test name
Test status
Simulation time	1074640805 ps
CPU time	19.19 seconds
Started	Apr 18 01:23:45 PM PDT 24
Finished	Apr 18 01:24:05 PM PDT 24
Peak memory	220992 kb
Host	smart-a02823f1-f313-4839-b31e-b4dba2b6c36e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470457847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3470457847
Directory	/workspace/8.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4287587979
Short name	T59
Test name
Test status
Simulation time	9399343733 ps
CPU time	16.93 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:33 PM PDT 24
Peak memory	219528 kb
Host	smart-17c5a69d-2a0f-41ad-8da6-3dfe0528eea0
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287587979 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.4287587979
Directory	/workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3901079792
Short name	T93
Test name
Test status
Simulation time	138005432 ps
CPU time	0.84 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:23:25 PM PDT 24
Peak memory	204748 kb
Host	smart-ee535a76-38e5-46ea-92d5-2cf3debe710b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901079792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3901079792
Directory	/workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/default/0.rv_dm_progbuf_busy.805422065
Short name	T17
Test name
Test status
Simulation time	556682578 ps
CPU time	1.77 seconds
Started	Apr 18 01:25:47 PM PDT 24
Finished	Apr 18 01:25:49 PM PDT 24
Peak memory	205304 kb
Host	smart-1fc30e00-eec8-4761-85fe-2def7db066fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805422065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.805422065
Directory	/workspace/0.rv_dm_progbuf_busy/latest

Test location	/workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1330803564
Short name	T23
Test name
Test status
Simulation time	80085283 ps
CPU time	0.91 seconds
Started	Apr 18 01:25:47 PM PDT 24
Finished	Apr 18 01:25:49 PM PDT 24
Peak memory	205124 kb
Host	smart-8b3fa4d5-4456-4f88-8bf3-336d5df40ad1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330803564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1330803564
Directory	/workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location	/workspace/coverage/default/5.rv_dm_alert_test.2118104645
Short name	T139
Test name
Test status
Simulation time	72946090 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:13 PM PDT 24
Finished	Apr 18 01:26:15 PM PDT 24
Peak memory	205004 kb
Host	smart-6ca0849b-2f6c-4848-abc6-7c83f17b2a3c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118104645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2118104645
Directory	/workspace/5.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/25.rv_dm_stress_all.3334116806
Short name	T36
Test name
Test status
Simulation time	2045697369 ps
CPU time	4.76 seconds
Started	Apr 18 01:26:39 PM PDT 24
Finished	Apr 18 01:26:44 PM PDT 24
Peak memory	205268 kb
Host	smart-59bf457e-c2f6-46b0-a44f-ccb0e3bcbb5d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334116806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3334116806
Directory	/workspace/25.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4162810347
Short name	T134
Test name
Test status
Simulation time	250692290 ps
CPU time	7.98 seconds
Started	Apr 18 01:23:12 PM PDT 24
Finished	Apr 18 01:23:20 PM PDT 24
Peak memory	213236 kb
Host	smart-431bc1d2-2c6a-44bd-9c48-b09673c7ed9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162810347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4162810347
Directory	/workspace/1.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1366380628
Short name	T101
Test name
Test status
Simulation time	216114255 ps
CPU time	3.95 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:20 PM PDT 24
Peak memory	204924 kb
Host	smart-fc0f00d2-1673-430b-bea2-ccb594ac1ff1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366380628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.1366380628
Directory	/workspace/0.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/default/15.rv_dm_alert_test.1103969646
Short name	T50
Test name
Test status
Simulation time	48447762 ps
CPU time	0.74 seconds
Started	Apr 18 01:26:29 PM PDT 24
Finished	Apr 18 01:26:31 PM PDT 24
Peak memory	204724 kb
Host	smart-4df1803b-218d-4841-a56f-acf93fbbe67a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103969646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1103969646
Directory	/workspace/15.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2630783741
Short name	T7
Test name
Test status
Simulation time	49512468 ps
CPU time	0.84 seconds
Started	Apr 18 01:25:46 PM PDT 24
Finished	Apr 18 01:25:47 PM PDT 24
Peak memory	204876 kb
Host	smart-1afcec81-d8d0-440d-95c4-95a7c6195735
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630783741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2630783741
Directory	/workspace/0.rv_dm_cmderr_halt_resume/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1875939524
Short name	T309
Test name
Test status
Simulation time	128589365 ps
CPU time	2.23 seconds
Started	Apr 18 01:23:34 PM PDT 24
Finished	Apr 18 01:23:37 PM PDT 24
Peak memory	218556 kb
Host	smart-0d5edbcd-fa0b-4e4a-a1cd-2c9bfc775535
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875939524 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1875939524
Directory	/workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2706481162
Short name	T243
Test name
Test status
Simulation time	5854829036 ps
CPU time	52.37 seconds
Started	Apr 18 01:23:13 PM PDT 24
Finished	Apr 18 01:24:06 PM PDT 24
Peak memory	205148 kb
Host	smart-82d196f4-5978-42b9-b012-9391695ceb04
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706481162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2706481162
Directory	/workspace/0.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2183985114
Short name	T308
Test name
Test status
Simulation time	110201446 ps
CPU time	1.61 seconds
Started	Apr 18 01:23:10 PM PDT 24
Finished	Apr 18 01:23:12 PM PDT 24
Peak memory	213164 kb
Host	smart-c4fc38a1-eef3-4ed5-9321-c0692eaa7f20
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183985114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2183985114
Directory	/workspace/0.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3132201431
Short name	T229
Test name
Test status
Simulation time	2686993884 ps
CPU time	5.91 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:22 PM PDT 24
Peak memory	221012 kb
Host	smart-8361bdc5-5c1f-4b8c-8d6a-6e80c08b5dec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132201431 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3132201431
Directory	/workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.929496419
Short name	T280
Test name
Test status
Simulation time	240922504 ps
CPU time	1.62 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:17 PM PDT 24
Peak memory	213168 kb
Host	smart-33b405f5-6605-454d-973c-9ae9fbdea0be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929496419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.929496419
Directory	/workspace/0.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3485322868
Short name	T199
Test name
Test status
Simulation time	33455536517 ps
CPU time	73.52 seconds
Started	Apr 18 01:23:11 PM PDT 24
Finished	Apr 18 01:24:25 PM PDT 24
Peak memory	204900 kb
Host	smart-0cefc302-2c82-41c6-be38-5dbef0e3e72b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485322868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3485322868
Directory	/workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.37371650
Short name	T203
Test name
Test status
Simulation time	14786160133 ps
CPU time	29.62 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	204860 kb
Host	smart-6633f2d5-e0b5-4cca-92c5-36882da43f1e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37371650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_ bit_bash.37371650
Directory	/workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4176389844
Short name	T92
Test name
Test status
Simulation time	345202718 ps
CPU time	1.2 seconds
Started	Apr 18 01:23:10 PM PDT 24
Finished	Apr 18 01:23:12 PM PDT 24
Peak memory	204908 kb
Host	smart-1ab42ea7-1358-4358-8ae8-0b71d8053d0d
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176389844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.4176389844
Directory	/workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.77509723
Short name	T259
Test name
Test status
Simulation time	850979354 ps
CPU time	2.55 seconds
Started	Apr 18 01:23:09 PM PDT 24
Finished	Apr 18 01:23:11 PM PDT 24
Peak memory	204892 kb
Host	smart-6716bb62-67f3-4781-bff4-a9f371c304c0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77509723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.77509723
Directory	/workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2632995467
Short name	T194
Test name
Test status
Simulation time	108687733 ps
CPU time	0.76 seconds
Started	Apr 18 01:23:14 PM PDT 24
Finished	Apr 18 01:23:15 PM PDT 24
Peak memory	204572 kb
Host	smart-6f2a0938-e788-43bd-b3e0-29521913b3ba
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632995467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.2632995467
Directory	/workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3388758978
Short name	T233
Test name
Test status
Simulation time	914141454 ps
CPU time	2.69 seconds
Started	Apr 18 01:23:12 PM PDT 24
Finished	Apr 18 01:23:15 PM PDT 24
Peak memory	204840 kb
Host	smart-be264829-4951-49c5-9ef6-9575e142b4cc
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388758978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.3388758978
Directory	/workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4138128730
Short name	T272
Test name
Test status
Simulation time	66332327 ps
CPU time	0.68 seconds
Started	Apr 18 01:23:14 PM PDT 24
Finished	Apr 18 01:23:15 PM PDT 24
Peak memory	204696 kb
Host	smart-71dbd719-5d3d-4260-8312-3fe2361d640a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138128730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.4138128730
Directory	/workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2347115003
Short name	T284
Test name
Test status
Simulation time	117266225 ps
CPU time	0.68 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:17 PM PDT 24
Peak memory	204612 kb
Host	smart-f217a824-81cd-42f1-a30b-78ec5542dd36
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347115003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2 347115003
Directory	/workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.681568819
Short name	T209
Test name
Test status
Simulation time	42893234 ps
CPU time	0.65 seconds
Started	Apr 18 01:23:12 PM PDT 24
Finished	Apr 18 01:23:13 PM PDT 24
Peak memory	204576 kb
Host	smart-00316d2c-c2e3-4439-8839-f4e594ae4a9a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681568819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.681568819
Directory	/workspace/0.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2314474842
Short name	T174
Test name
Test status
Simulation time	27808726 ps
CPU time	0.7 seconds
Started	Apr 18 01:23:11 PM PDT 24
Finished	Apr 18 01:23:12 PM PDT 24
Peak memory	204672 kb
Host	smart-ce873ff4-2fe9-4c58-85c3-16915d4e09dd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314474842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2314474842
Directory	/workspace/0.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1851286574
Short name	T190
Test name
Test status
Simulation time	626962487 ps
CPU time	4.71 seconds
Started	Apr 18 01:23:10 PM PDT 24
Finished	Apr 18 01:23:15 PM PDT 24
Peak memory	213172 kb
Host	smart-58cb2455-6286-4b49-899c-0537944bddee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851286574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1851286574
Directory	/workspace/0.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3728466382
Short name	T257
Test name
Test status
Simulation time	3511756037 ps
CPU time	20.13 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:36 PM PDT 24
Peak memory	221444 kb
Host	smart-2e96dd88-7f58-4d77-b807-f1fd43e965fd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728466382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3728466382
Directory	/workspace/0.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3835548561
Short name	T285
Test name
Test status
Simulation time	2324471440 ps
CPU time	65.66 seconds
Started	Apr 18 01:23:11 PM PDT 24
Finished	Apr 18 01:24:17 PM PDT 24
Peak memory	205104 kb
Host	smart-1668f496-85f3-4dfa-bc2f-484ef358f593
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835548561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3835548561
Directory	/workspace/1.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1955555125
Short name	T222
Test name
Test status
Simulation time	14597812218 ps
CPU time	36.57 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:24:01 PM PDT 24
Peak memory	213288 kb
Host	smart-7ec3f868-5b6e-4af3-a215-31e77e4838db
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955555125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1955555125
Directory	/workspace/1.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.754806459
Short name	T105
Test name
Test status
Simulation time	73245703 ps
CPU time	2.24 seconds
Started	Apr 18 01:23:13 PM PDT 24
Finished	Apr 18 01:23:15 PM PDT 24
Peak memory	213048 kb
Host	smart-c2595ad7-85bb-422d-8423-a84fc240bb97
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754806459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.754806459
Directory	/workspace/1.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3287755776
Short name	T218
Test name
Test status
Simulation time	3952552554 ps
CPU time	3.81 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:32 PM PDT 24
Peak memory	215260 kb
Host	smart-312d5f48-0d1f-4982-a6d0-d56c34589506
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287755776 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3287755776
Directory	/workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1008084182
Short name	T303
Test name
Test status
Simulation time	295640008 ps
CPU time	1.48 seconds
Started	Apr 18 01:23:21 PM PDT 24
Finished	Apr 18 01:23:23 PM PDT 24
Peak memory	218224 kb
Host	smart-01a74df5-2ca9-4fc6-a099-d5eed3769828
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008084182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1008084182
Directory	/workspace/1.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3025576464
Short name	T188
Test name
Test status
Simulation time	11887890114 ps
CPU time	15.06 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:31 PM PDT 24
Peak memory	204844 kb
Host	smart-55ab19cc-6df0-4bb0-a930-8e77cdb17ee6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025576464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.3025576464
Directory	/workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2510027912
Short name	T287
Test name
Test status
Simulation time	12171578944 ps
CPU time	27.43 seconds
Started	Apr 18 01:23:23 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	204892 kb
Host	smart-962daece-a9db-42cc-96e2-82ec6d5f8506
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510027912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_bit_bash.2510027912
Directory	/workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1243993385
Short name	T95
Test name
Test status
Simulation time	1826302581 ps
CPU time	1.81 seconds
Started	Apr 18 01:23:14 PM PDT 24
Finished	Apr 18 01:23:16 PM PDT 24
Peak memory	204932 kb
Host	smart-3b8f3e65-7ca8-49a4-bdba-63c69410f7d2
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243993385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.1243993385
Directory	/workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.718477530
Short name	T186
Test name
Test status
Simulation time	280051246 ps
CPU time	1.85 seconds
Started	Apr 18 01:23:10 PM PDT 24
Finished	Apr 18 01:23:13 PM PDT 24
Peak memory	204844 kb
Host	smart-ee31a40f-4bd5-4fd2-a7bd-2fbea0f00bbf
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718477530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.718477530
Directory	/workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2775989896
Short name	T238
Test name
Test status
Simulation time	86301542 ps
CPU time	0.79 seconds
Started	Apr 18 01:23:13 PM PDT 24
Finished	Apr 18 01:23:14 PM PDT 24
Peak memory	204612 kb
Host	smart-78311146-483e-487a-bfcd-3f90dc5d3680
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775989896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.2775989896
Directory	/workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2846204017
Short name	T64
Test name
Test status
Simulation time	728494719 ps
CPU time	2.18 seconds
Started	Apr 18 01:23:19 PM PDT 24
Finished	Apr 18 01:23:21 PM PDT 24
Peak memory	204880 kb
Host	smart-6f5b81a2-e747-4b60-a435-69d9854db748
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846204017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2846204017
Directory	/workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.729613017
Short name	T181
Test name
Test status
Simulation time	111909960 ps
CPU time	0.97 seconds
Started	Apr 18 01:23:10 PM PDT 24
Finished	Apr 18 01:23:11 PM PDT 24
Peak memory	204712 kb
Host	smart-822a2997-2cca-4dc8-be90-c78f82c409e2
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729613017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _hw_reset.729613017
Directory	/workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1967003173
Short name	T63
Test name
Test status
Simulation time	113935107 ps
CPU time	0.81 seconds
Started	Apr 18 01:23:15 PM PDT 24
Finished	Apr 18 01:23:17 PM PDT 24
Peak memory	204644 kb
Host	smart-be476a3b-3851-4412-92b1-81d6cf2f9dc2
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967003173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1 967003173
Directory	/workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2408091974
Short name	T176
Test name
Test status
Simulation time	16288431 ps
CPU time	0.68 seconds
Started	Apr 18 01:23:13 PM PDT 24
Finished	Apr 18 01:23:15 PM PDT 24
Peak memory	204652 kb
Host	smart-c78b73b3-2aed-4469-acac-c5983137cb46
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408091974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.2408091974
Directory	/workspace/1.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2922213874
Short name	T305
Test name
Test status
Simulation time	21323664 ps
CPU time	0.68 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:23:26 PM PDT 24
Peak memory	204596 kb
Host	smart-ebf18a9b-81e2-4b91-8b78-3e5ab5e864e9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922213874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2922213874
Directory	/workspace/1.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3791104753
Short name	T306
Test name
Test status
Simulation time	571743508 ps
CPU time	6.49 seconds
Started	Apr 18 01:23:17 PM PDT 24
Finished	Apr 18 01:23:24 PM PDT 24
Peak memory	204924 kb
Host	smart-24abb84f-5e5c-48f8-8e74-262d007e5fec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791104753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3791104753
Directory	/workspace/1.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2159955691
Short name	T268
Test name
Test status
Simulation time	339727465 ps
CPU time	5 seconds
Started	Apr 18 01:23:20 PM PDT 24
Finished	Apr 18 01:23:25 PM PDT 24
Peak memory	213200 kb
Host	smart-e8d2a754-6491-4590-be56-de9ea1ca103d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159955691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2159955691
Directory	/workspace/1.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4144418188
Short name	T107
Test name
Test status
Simulation time	507292695 ps
CPU time	2.24 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	213072 kb
Host	smart-2cf3c4ac-e8a9-464f-9629-09d78e244091
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144418188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4144418188
Directory	/workspace/10.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1922398373
Short name	T214
Test name
Test status
Simulation time	437999670 ps
CPU time	1.42 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:44 PM PDT 24
Peak memory	204804 kb
Host	smart-78bfef7f-5b06-4819-ae14-fb3276d863c4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922398373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1922398373
Directory	/workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2372209154
Short name	T304
Test name
Test status
Simulation time	54645371 ps
CPU time	0.78 seconds
Started	Apr 18 01:23:46 PM PDT 24
Finished	Apr 18 01:23:47 PM PDT 24
Peak memory	204604 kb
Host	smart-26d927d1-1faf-47ab-ad66-7cfbc5c26886
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372209154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 2372209154
Directory	/workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3432809584
Short name	T49
Test name
Test status
Simulation time	990047377 ps
CPU time	7.74 seconds
Started	Apr 18 01:23:45 PM PDT 24
Finished	Apr 18 01:23:53 PM PDT 24
Peak memory	205020 kb
Host	smart-e5393bbb-7afc-47e3-9b25-c32c4963f183
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432809584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.3432809584
Directory	/workspace/10.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3664886335
Short name	T239
Test name
Test status
Simulation time	32686589 ps
CPU time	1.99 seconds
Started	Apr 18 01:23:47 PM PDT 24
Finished	Apr 18 01:23:49 PM PDT 24
Peak memory	213208 kb
Host	smart-7036afe2-1cc1-463b-88ce-109610b8b20e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664886335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3664886335
Directory	/workspace/10.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2848432706
Short name	T129
Test name
Test status
Simulation time	683295386 ps
CPU time	16.17 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:24:00 PM PDT 24
Peak memory	213172 kb
Host	smart-ab1ba622-e482-42d6-a24d-39f76521157a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848432706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 848432706
Directory	/workspace/10.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1488780703
Short name	T244
Test name
Test status
Simulation time	1062959056 ps
CPU time	3.53 seconds
Started	Apr 18 01:23:50 PM PDT 24
Finished	Apr 18 01:23:54 PM PDT 24
Peak memory	214840 kb
Host	smart-923e97ae-4860-4d53-8efb-bcb3d9998b31
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488780703 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1488780703
Directory	/workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.103056220
Short name	T226
Test name
Test status
Simulation time	50397736 ps
CPU time	1.43 seconds
Started	Apr 18 01:23:41 PM PDT 24
Finished	Apr 18 01:23:43 PM PDT 24
Peak memory	218060 kb
Host	smart-4bdc32d5-6a47-4bfa-a57f-35268d058043
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103056220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.103056220
Directory	/workspace/11.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.851929589
Short name	T227
Test name
Test status
Simulation time	773121610 ps
CPU time	3.72 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	204788 kb
Host	smart-c7a367b6-d03c-4ddb-bc3b-c5b5d7720722
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851929589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.851929589
Directory	/workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.449842675
Short name	T202
Test name
Test status
Simulation time	130921445 ps
CPU time	0.81 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	204672 kb
Host	smart-1dde7cd3-8fac-422c-9ef5-a8002100b396
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449842675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.449842675
Directory	/workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1827586343
Short name	T273
Test name
Test status
Simulation time	419464237 ps
CPU time	7.5 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	204876 kb
Host	smart-d6652521-bfb3-4987-99cb-faee742fc8e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827586343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.1827586343
Directory	/workspace/11.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2414262355
Short name	T286
Test name
Test status
Simulation time	58895036 ps
CPU time	2.75 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	213060 kb
Host	smart-6f9cc9f8-303b-4c2a-be4e-e6dbd2fac323
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414262355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2414262355
Directory	/workspace/11.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1640384905
Short name	T200
Test name
Test status
Simulation time	863592492 ps
CPU time	10.36 seconds
Started	Apr 18 01:23:56 PM PDT 24
Finished	Apr 18 01:24:07 PM PDT 24
Peak memory	221224 kb
Host	smart-fcd69ba5-4d65-4600-b618-982f4a054511
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640384905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1 640384905
Directory	/workspace/11.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1050389232
Short name	T71
Test name
Test status
Simulation time	2316639267 ps
CPU time	4.22 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:44 PM PDT 24
Peak memory	218140 kb
Host	smart-d7778d9c-95f6-4252-8506-925b22785805
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050389232 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1050389232
Directory	/workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4099434997
Short name	T236
Test name
Test status
Simulation time	97632178 ps
CPU time	1.63 seconds
Started	Apr 18 01:23:52 PM PDT 24
Finished	Apr 18 01:23:54 PM PDT 24
Peak memory	213104 kb
Host	smart-66a12eb7-5610-4d6d-81d9-d073dc932e6b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099434997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4099434997
Directory	/workspace/12.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1282552206
Short name	T195
Test name
Test status
Simulation time	263296856 ps
CPU time	1.78 seconds
Started	Apr 18 01:23:55 PM PDT 24
Finished	Apr 18 01:23:57 PM PDT 24
Peak memory	204816 kb
Host	smart-db9a7a4c-c6b6-4a55-8f40-d275e130a066
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282552206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 1282552206
Directory	/workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1969825021
Short name	T276
Test name
Test status
Simulation time	38708202 ps
CPU time	0.68 seconds
Started	Apr 18 01:23:54 PM PDT 24
Finished	Apr 18 01:23:55 PM PDT 24
Peak memory	204592 kb
Host	smart-9a078155-9218-413a-beba-f27c549ddd1f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969825021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 1969825021
Directory	/workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.581661687
Short name	T114
Test name
Test status
Simulation time	591736271 ps
CPU time	7.05 seconds
Started	Apr 18 01:23:55 PM PDT 24
Finished	Apr 18 01:24:02 PM PDT 24
Peak memory	205048 kb
Host	smart-bcc835f7-72f4-4531-b884-b5366ce03ca8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581661687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_ csr_outstanding.581661687
Directory	/workspace/12.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1661733059
Short name	T212
Test name
Test status
Simulation time	25260686301 ps
CPU time	27.91 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:24:07 PM PDT 24
Peak memory	221412 kb
Host	smart-e951cf80-ab93-4152-908e-a8fc914a822e
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661733059 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.1661733059
Directory	/workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1867919164
Short name	T201
Test name
Test status
Simulation time	773640888 ps
CPU time	4.84 seconds
Started	Apr 18 01:23:49 PM PDT 24
Finished	Apr 18 01:23:55 PM PDT 24
Peak memory	213100 kb
Host	smart-e0bae49d-f842-4c33-81f1-bef865af0c55
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867919164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1867919164
Directory	/workspace/12.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2431921229
Short name	T293
Test name
Test status
Simulation time	2668376142 ps
CPU time	9.6 seconds
Started	Apr 18 01:23:46 PM PDT 24
Finished	Apr 18 01:23:56 PM PDT 24
Peak memory	213300 kb
Host	smart-50348998-3640-457f-bb5c-89a895511b18
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431921229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2 431921229
Directory	/workspace/12.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3230956972
Short name	T231
Test name
Test status
Simulation time	2479102653 ps
CPU time	5.6 seconds
Started	Apr 18 01:23:41 PM PDT 24
Finished	Apr 18 01:23:47 PM PDT 24
Peak memory	221220 kb
Host	smart-cd175d08-bf36-4ffc-afac-93d39940b9b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230956972 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3230956972
Directory	/workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.542474133
Short name	T112
Test name
Test status
Simulation time	165241996 ps
CPU time	2.29 seconds
Started	Apr 18 01:23:48 PM PDT 24
Finished	Apr 18 01:23:50 PM PDT 24
Peak memory	218420 kb
Host	smart-71d598a2-a266-49fb-8af6-cc5c83042ba7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542474133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.542474133
Directory	/workspace/13.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.251637866
Short name	T301
Test name
Test status
Simulation time	517308267 ps
CPU time	1.65 seconds
Started	Apr 18 01:23:46 PM PDT 24
Finished	Apr 18 01:23:48 PM PDT 24
Peak memory	204840 kb
Host	smart-e6fbbad7-fb90-4828-9398-c551906ebf13
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251637866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.251637866
Directory	/workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3534428204
Short name	T263
Test name
Test status
Simulation time	68241385 ps
CPU time	0.68 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	204612 kb
Host	smart-89d4fcbc-a2af-4fca-a185-e6981e8c90e6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534428204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 3534428204
Directory	/workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.786627280
Short name	T100
Test name
Test status
Simulation time	1037821147 ps
CPU time	7.54 seconds
Started	Apr 18 01:23:49 PM PDT 24
Finished	Apr 18 01:23:57 PM PDT 24
Peak memory	205052 kb
Host	smart-de3e8404-91ec-4528-99ab-f94bdbb0c092
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786627280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.786627280
Directory	/workspace/13.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1061584846
Short name	T207
Test name
Test status
Simulation time	184887833 ps
CPU time	3.4 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:23:42 PM PDT 24
Peak memory	213156 kb
Host	smart-46b0edc1-ceae-479a-ba29-924736ff52c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061584846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1061584846
Directory	/workspace/13.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3182586202
Short name	T45
Test name
Test status
Simulation time	373729910 ps
CPU time	8.35 seconds
Started	Apr 18 01:23:53 PM PDT 24
Finished	Apr 18 01:24:02 PM PDT 24
Peak memory	213176 kb
Host	smart-1cc1ab6d-6b6b-46b6-9ec5-3614ed847fcb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182586202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3 182586202
Directory	/workspace/13.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2238594383
Short name	T241
Test name
Test status
Simulation time	524736063 ps
CPU time	3.41 seconds
Started	Apr 18 01:23:36 PM PDT 24
Finished	Apr 18 01:23:40 PM PDT 24
Peak memory	221372 kb
Host	smart-2bfbad3e-a3c2-46b1-930a-9e7308ce3669
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238594383 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2238594383
Directory	/workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.890677763
Short name	T254
Test name
Test status
Simulation time	108026158 ps
CPU time	1.55 seconds
Started	Apr 18 01:23:52 PM PDT 24
Finished	Apr 18 01:23:55 PM PDT 24
Peak memory	213076 kb
Host	smart-a578d994-3975-4430-8cc3-5b4c624c8b86
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890677763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.890677763
Directory	/workspace/14.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4236631386
Short name	T298
Test name
Test status
Simulation time	1038615856 ps
CPU time	1.73 seconds
Started	Apr 18 01:23:48 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	204880 kb
Host	smart-abbeebf4-4fc8-46e2-96f7-bc96db4ebb2c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236631386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 4236631386
Directory	/workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2474200821
Short name	T262
Test name
Test status
Simulation time	73295121 ps
CPU time	0.78 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:42 PM PDT 24
Peak memory	204528 kb
Host	smart-c079e796-d9e1-4a8f-a630-ee9cead83251
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474200821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 2474200821
Directory	/workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3898243674
Short name	T115
Test name
Test status
Simulation time	689218612 ps
CPU time	4.41 seconds
Started	Apr 18 01:23:37 PM PDT 24
Finished	Apr 18 01:23:42 PM PDT 24
Peak memory	204980 kb
Host	smart-1d1501ee-c85f-4567-82a7-1081fde7ba63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898243674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3898243674
Directory	/workspace/14.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2831021606
Short name	T307
Test name
Test status
Simulation time	11453401043 ps
CPU time	19.1 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:59 PM PDT 24
Peak memory	213212 kb
Host	smart-b86efdb2-ec98-4594-91a1-4e1c020f93aa
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831021606 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.2831021606
Directory	/workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1425907326
Short name	T126
Test name
Test status
Simulation time	950100973 ps
CPU time	5.06 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	213208 kb
Host	smart-6f18ecad-f509-47cc-9757-686eb01cf87f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425907326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1425907326
Directory	/workspace/14.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1179203003
Short name	T295
Test name
Test status
Simulation time	882849202 ps
CPU time	8.46 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	221204 kb
Host	smart-81c3fb07-b64b-4942-b39f-2ccbba09fb9f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179203003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 179203003
Directory	/workspace/14.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3820267355
Short name	T204
Test name
Test status
Simulation time	163732581 ps
CPU time	2.08 seconds
Started	Apr 18 01:23:45 PM PDT 24
Finished	Apr 18 01:23:48 PM PDT 24
Peak memory	217412 kb
Host	smart-208439f1-4f6e-48b9-9c45-74267f56740d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820267355 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3820267355
Directory	/workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2598280209
Short name	T248
Test name
Test status
Simulation time	180815361 ps
CPU time	2.33 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:42 PM PDT 24
Peak memory	221572 kb
Host	smart-71e7a3f3-79af-4c00-b3a1-9a9d8c154543
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598280209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2598280209
Directory	/workspace/15.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4163560287
Short name	T182
Test name
Test status
Simulation time	464853221 ps
CPU time	1.54 seconds
Started	Apr 18 01:23:49 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	204848 kb
Host	smart-c8842f09-52ae-43f2-9683-2880337d6cdf
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163560287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 4163560287
Directory	/workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2347564843
Short name	T235
Test name
Test status
Simulation time	40900819 ps
CPU time	0.77 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:40 PM PDT 24
Peak memory	204672 kb
Host	smart-c8cf17bf-617c-4fee-9f5c-59ea495ed87e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347564843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 2347564843
Directory	/workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4213686731
Short name	T313
Test name
Test status
Simulation time	1056519145 ps
CPU time	4.23 seconds
Started	Apr 18 01:23:49 PM PDT 24
Finished	Apr 18 01:23:53 PM PDT 24
Peak memory	204916 kb
Host	smart-05da20eb-c5a8-4d16-9f81-f9042a9022f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213686731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.4213686731
Directory	/workspace/15.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3632545613
Short name	T282
Test name
Test status
Simulation time	23396605680 ps
CPU time	12.37 seconds
Started	Apr 18 01:23:51 PM PDT 24
Finished	Apr 18 01:24:03 PM PDT 24
Peak memory	221428 kb
Host	smart-b942e2ef-e979-4752-b4c1-2160db987dbd
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632545613 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.3632545613
Directory	/workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2105236135
Short name	T256
Test name
Test status
Simulation time	42996433 ps
CPU time	1.45 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	213136 kb
Host	smart-72c2b8ee-7604-4efa-a87f-959cdf23f076
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105236135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2105236135
Directory	/workspace/15.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2672796769
Short name	T47
Test name
Test status
Simulation time	670553779 ps
CPU time	9.03 seconds
Started	Apr 18 01:23:58 PM PDT 24
Finished	Apr 18 01:24:07 PM PDT 24
Peak memory	221256 kb
Host	smart-5daabc8d-859a-447f-9076-c779354c0023
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672796769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 672796769
Directory	/workspace/15.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.991851216
Short name	T311
Test name
Test status
Simulation time	72062198 ps
CPU time	2.58 seconds
Started	Apr 18 01:23:48 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	221416 kb
Host	smart-0e5554bb-87ee-4ac2-a385-beecb412e519
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991851216 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.991851216
Directory	/workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1178726544
Short name	T80
Test name
Test status
Simulation time	33643158 ps
CPU time	1.46 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	213140 kb
Host	smart-46d68d7f-b95f-460f-b6ca-fb4ac760b430
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178726544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1178726544
Directory	/workspace/16.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1981172851
Short name	T193
Test name
Test status
Simulation time	2275689135 ps
CPU time	4.58 seconds
Started	Apr 18 01:23:52 PM PDT 24
Finished	Apr 18 01:23:57 PM PDT 24
Peak memory	204872 kb
Host	smart-bd9c4f63-5449-492c-8198-7a475009267a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981172851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 1981172851
Directory	/workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.204948335
Short name	T180
Test name
Test status
Simulation time	146309759 ps
CPU time	0.83 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:40 PM PDT 24
Peak memory	204620 kb
Host	smart-45c252e3-b5b9-4e3a-8246-7a151d38b433
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204948335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.204948335
Directory	/workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.903089961
Short name	T278
Test name
Test status
Simulation time	880882573 ps
CPU time	3.8 seconds
Started	Apr 18 01:23:55 PM PDT 24
Finished	Apr 18 01:24:00 PM PDT 24
Peak memory	204996 kb
Host	smart-622162b5-f63c-4d26-b4ed-27f967492c61
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903089961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_ csr_outstanding.903089961
Directory	/workspace/16.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.992926094
Short name	T62
Test name
Test status
Simulation time	44578353973 ps
CPU time	10.65 seconds
Started	Apr 18 01:23:37 PM PDT 24
Finished	Apr 18 01:23:48 PM PDT 24
Peak memory	214852 kb
Host	smart-8fe5d1bd-4ed2-447e-a64f-2e0cc7fe9641
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992926094 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.992926094
Directory	/workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.613960738
Short name	T69
Test name
Test status
Simulation time	293471024 ps
CPU time	2.47 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:47 PM PDT 24
Peak memory	213224 kb
Host	smart-c9e8d386-79a4-41db-b8db-0e4f78b34dd8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613960738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.613960738
Directory	/workspace/16.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.43310584
Short name	T136
Test name
Test status
Simulation time	884015620 ps
CPU time	15.7 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:59 PM PDT 24
Peak memory	221244 kb
Host	smart-fbaefc0f-94cd-4220-9369-e7cd0df321ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43310584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.43310584
Directory	/workspace/16.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.735150747
Short name	T183
Test name
Test status
Simulation time	394928138 ps
CPU time	2.06 seconds
Started	Apr 18 01:23:45 PM PDT 24
Finished	Apr 18 01:23:48 PM PDT 24
Peak memory	216768 kb
Host	smart-239cca76-45e1-4f9d-b8a6-f652192ee0d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735150747 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.735150747
Directory	/workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3120677553
Short name	T108
Test name
Test status
Simulation time	197288308 ps
CPU time	1.55 seconds
Started	Apr 18 01:23:45 PM PDT 24
Finished	Apr 18 01:23:47 PM PDT 24
Peak memory	218228 kb
Host	smart-a2366036-a316-4697-bddc-c37fcd994d8e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120677553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3120677553
Directory	/workspace/17.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.538937307
Short name	T302
Test name
Test status
Simulation time	534612944 ps
CPU time	1.44 seconds
Started	Apr 18 01:23:56 PM PDT 24
Finished	Apr 18 01:23:58 PM PDT 24
Peak memory	204924 kb
Host	smart-fdda1c97-1183-437c-8d7c-177072d875c4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538937307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.538937307
Directory	/workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3286308216
Short name	T251
Test name
Test status
Simulation time	54342314 ps
CPU time	0.71 seconds
Started	Apr 18 01:23:59 PM PDT 24
Finished	Apr 18 01:24:00 PM PDT 24
Peak memory	204624 kb
Host	smart-fd57db5d-9ee1-453e-9268-2752452c8b10
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286308216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 3286308216
Directory	/workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.404196323
Short name	T113
Test name
Test status
Simulation time	277074076 ps
CPU time	4.2 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:48 PM PDT 24
Peak memory	204900 kb
Host	smart-ecd4ba50-2aa9-4bc5-ab91-bbcabfc592cd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404196323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_ csr_outstanding.404196323
Directory	/workspace/17.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2691653302
Short name	T258
Test name
Test status
Simulation time	90599381 ps
CPU time	2.59 seconds
Started	Apr 18 01:23:43 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	213144 kb
Host	smart-b0ad5f6f-566a-4434-bc84-366956131df8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691653302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2691653302
Directory	/workspace/17.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.683355762
Short name	T137
Test name
Test status
Simulation time	1517276481 ps
CPU time	19.89 seconds
Started	Apr 18 01:23:55 PM PDT 24
Finished	Apr 18 01:24:16 PM PDT 24
Peak memory	221244 kb
Host	smart-342e5e00-f8f1-4d59-a21a-1b5f8f19e476
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683355762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.683355762
Directory	/workspace/17.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3146345393
Short name	T230
Test name
Test status
Simulation time	2714331167 ps
CPU time	4.08 seconds
Started	Apr 18 01:23:52 PM PDT 24
Finished	Apr 18 01:23:56 PM PDT 24
Peak memory	216832 kb
Host	smart-1183d2e3-f390-4744-b41e-80cf320e2f6a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146345393 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3146345393
Directory	/workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.206161583
Short name	T219
Test name
Test status
Simulation time	279169040 ps
CPU time	1.61 seconds
Started	Apr 18 01:23:54 PM PDT 24
Finished	Apr 18 01:23:57 PM PDT 24
Peak memory	218348 kb
Host	smart-04a3e243-ee18-4c5c-a70a-8380afde4be0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206161583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.206161583
Directory	/workspace/18.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2976437494
Short name	T187
Test name
Test status
Simulation time	574099064 ps
CPU time	2.96 seconds
Started	Apr 18 01:23:51 PM PDT 24
Finished	Apr 18 01:23:55 PM PDT 24
Peak memory	204800 kb
Host	smart-13d98843-042d-43d0-8031-db92ae9bb0b7
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976437494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 2976437494
Directory	/workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4223416246
Short name	T310
Test name
Test status
Simulation time	111664911 ps
CPU time	0.66 seconds
Started	Apr 18 01:23:54 PM PDT 24
Finished	Apr 18 01:23:55 PM PDT 24
Peak memory	204652 kb
Host	smart-204179a4-5287-4553-84f9-85151cf86c1b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223416246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 4223416246
Directory	/workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2063690835
Short name	T116
Test name
Test status
Simulation time	517449190 ps
CPU time	4.44 seconds
Started	Apr 18 01:23:53 PM PDT 24
Finished	Apr 18 01:23:59 PM PDT 24
Peak memory	204920 kb
Host	smart-bdbdc876-d423-4b0d-b2d1-c5462349bbc3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063690835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2063690835
Directory	/workspace/18.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2768903184
Short name	T220
Test name
Test status
Simulation time	130023249 ps
CPU time	2.93 seconds
Started	Apr 18 01:23:48 PM PDT 24
Finished	Apr 18 01:23:52 PM PDT 24
Peak memory	213236 kb
Host	smart-7e6dc5d7-688f-47c3-9ab1-8029f69c5fa1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768903184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2768903184
Directory	/workspace/18.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1970576200
Short name	T133
Test name
Test status
Simulation time	2227720921 ps
CPU time	19.01 seconds
Started	Apr 18 01:23:52 PM PDT 24
Finished	Apr 18 01:24:12 PM PDT 24
Peak memory	213252 kb
Host	smart-24739321-375c-4637-8180-6505161b00ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970576200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1 970576200
Directory	/workspace/18.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3983887345
Short name	T185
Test name
Test status
Simulation time	131227296 ps
CPU time	2.01 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	214808 kb
Host	smart-8f8a10fa-722c-497c-947a-95bc936fca42
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983887345 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3983887345
Directory	/workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3946826174
Short name	T260
Test name
Test status
Simulation time	40393787 ps
CPU time	2.1 seconds
Started	Apr 18 01:23:51 PM PDT 24
Finished	Apr 18 01:23:53 PM PDT 24
Peak memory	213156 kb
Host	smart-86fc2ea9-a3d3-4a3a-9548-0db43702260b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946826174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3946826174
Directory	/workspace/19.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1073357686
Short name	T290
Test name
Test status
Simulation time	423524767 ps
CPU time	1.29 seconds
Started	Apr 18 01:23:54 PM PDT 24
Finished	Apr 18 01:23:56 PM PDT 24
Peak memory	204752 kb
Host	smart-92ed6eb8-a58b-4b73-be2f-0d22815c826c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073357686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 1073357686
Directory	/workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4109356317
Short name	T65
Test name
Test status
Simulation time	53028675 ps
CPU time	0.76 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	204560 kb
Host	smart-412f7f0a-1b38-464f-b7c3-9192e607960f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109356317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 4109356317
Directory	/workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2565670843
Short name	T103
Test name
Test status
Simulation time	365188207 ps
CPU time	3.58 seconds
Started	Apr 18 01:23:54 PM PDT 24
Finished	Apr 18 01:23:58 PM PDT 24
Peak memory	204948 kb
Host	smart-1c43039b-dcb6-4c27-b660-1c98c69f7d4d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565670843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.2565670843
Directory	/workspace/19.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2903246126
Short name	T296
Test name
Test status
Simulation time	99836003 ps
CPU time	5.83 seconds
Started	Apr 18 01:23:51 PM PDT 24
Finished	Apr 18 01:23:57 PM PDT 24
Peak memory	213176 kb
Host	smart-8cb42847-a9a4-4798-a4a5-e4ce608d0898
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903246126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2903246126
Directory	/workspace/19.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2975093607
Short name	T46
Test name
Test status
Simulation time	203620856 ps
CPU time	8.1 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:50 PM PDT 24
Peak memory	221216 kb
Host	smart-8cc597c0-9faa-4d59-8090-db2e2fa51e5a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975093607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2 975093607
Directory	/workspace/19.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.45310492
Short name	T118
Test name
Test status
Simulation time	2242334540 ps
CPU time	28.46 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:54 PM PDT 24
Peak memory	204960 kb
Host	smart-691d4f5e-ad95-4430-95db-3d35c6a11758
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45310492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.rv_dm_csr_aliasing.45310492
Directory	/workspace/2.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2156867497
Short name	T110
Test name
Test status
Simulation time	7614987970 ps
CPU time	72.47 seconds
Started	Apr 18 01:23:23 PM PDT 24
Finished	Apr 18 01:24:36 PM PDT 24
Peak memory	213280 kb
Host	smart-a0189220-944f-4921-836d-51483d3cba6c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156867497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2156867497
Directory	/workspace/2.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3354503621
Short name	T77
Test name
Test status
Simulation time	65006953 ps
CPU time	1.58 seconds
Started	Apr 18 01:23:18 PM PDT 24
Finished	Apr 18 01:23:20 PM PDT 24
Peak memory	213136 kb
Host	smart-84cd81e6-196a-49bc-ab54-afe53c69068e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354503621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3354503621
Directory	/workspace/2.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3981420115
Short name	T81
Test name
Test status
Simulation time	141029503 ps
CPU time	1.5 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:30 PM PDT 24
Peak memory	212980 kb
Host	smart-8cbf76ef-32db-4ee3-bcfe-f09feb7e0619
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981420115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3981420115
Directory	/workspace/2.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4229713732
Short name	T191
Test name
Test status
Simulation time	8181731609 ps
CPU time	32.73 seconds
Started	Apr 18 01:23:17 PM PDT 24
Finished	Apr 18 01:23:50 PM PDT 24
Peak memory	204872 kb
Host	smart-142f47d8-0130-4328-8c46-1f54b2944224
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229713732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.4229713732
Directory	/workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1336356187
Short name	T177
Test name
Test status
Simulation time	23210493078 ps
CPU time	45.25 seconds
Started	Apr 18 01:23:18 PM PDT 24
Finished	Apr 18 01:24:03 PM PDT 24
Peak memory	204912 kb
Host	smart-38b2db8e-d2b8-4b39-a7ed-341eb7b0f2f8
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336356187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_bit_bash.1336356187
Directory	/workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2971355490
Short name	T94
Test name
Test status
Simulation time	497070334 ps
CPU time	1.23 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:27 PM PDT 24
Peak memory	204868 kb
Host	smart-7ac60a97-bc42-45da-a62e-a453ba943b67
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971355490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2971355490
Directory	/workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1073766989
Short name	T246
Test name
Test status
Simulation time	961665858 ps
CPU time	1.9 seconds
Started	Apr 18 01:23:22 PM PDT 24
Finished	Apr 18 01:23:24 PM PDT 24
Peak memory	204848 kb
Host	smart-39a4666c-453d-443d-878b-1df6661704f0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073766989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1 073766989
Directory	/workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3898565077
Short name	T213
Test name
Test status
Simulation time	105985112 ps
CPU time	0.75 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:26 PM PDT 24
Peak memory	204640 kb
Host	smart-ae7663e8-e6cf-477b-a84f-a488faa2fb9d
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898565077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.3898565077
Directory	/workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.786678479
Short name	T221
Test name
Test status
Simulation time	908058588 ps
CPU time	3.22 seconds
Started	Apr 18 01:23:19 PM PDT 24
Finished	Apr 18 01:23:27 PM PDT 24
Peak memory	204840 kb
Host	smart-22db55ca-0c50-44d4-8959-78c21964934e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786678479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _bit_bash.786678479
Directory	/workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3168117624
Short name	T206
Test name
Test status
Simulation time	24549621 ps
CPU time	0.72 seconds
Started	Apr 18 01:23:17 PM PDT 24
Finished	Apr 18 01:23:18 PM PDT 24
Peak memory	204652 kb
Host	smart-b5de511f-ca95-4970-b996-1c55feafa869
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168117624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3 168117624
Directory	/workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3869103414
Short name	T211
Test name
Test status
Simulation time	21239975 ps
CPU time	0.69 seconds
Started	Apr 18 01:23:18 PM PDT 24
Finished	Apr 18 01:23:19 PM PDT 24
Peak memory	204648 kb
Host	smart-b321ecc0-f529-4b0e-92b7-eb0ee7218f51
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869103414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3869103414
Directory	/workspace/2.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1044746963
Short name	T208
Test name
Test status
Simulation time	149036320 ps
CPU time	0.65 seconds
Started	Apr 18 01:23:18 PM PDT 24
Finished	Apr 18 01:23:19 PM PDT 24
Peak memory	204652 kb
Host	smart-14aa9239-eb90-43de-a614-58b29cc4b66b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044746963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1044746963
Directory	/workspace/2.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.916392423
Short name	T102
Test name
Test status
Simulation time	176537924 ps
CPU time	6.56 seconds
Started	Apr 18 01:23:20 PM PDT 24
Finished	Apr 18 01:23:27 PM PDT 24
Peak memory	204856 kb
Host	smart-6d7f16eb-56fb-4228-af4c-e0f28244954e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916392423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c sr_outstanding.916392423
Directory	/workspace/2.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.419771287
Short name	T271
Test name
Test status
Simulation time	132304534 ps
CPU time	4.69 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:30 PM PDT 24
Peak memory	213208 kb
Host	smart-c46836f4-5d44-4821-8fb8-54ee4b49b606
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419771287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.419771287
Directory	/workspace/2.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.559069682
Short name	T131
Test name
Test status
Simulation time	470713407 ps
CPU time	16.17 seconds
Started	Apr 18 01:23:18 PM PDT 24
Finished	Apr 18 01:23:34 PM PDT 24
Peak memory	221324 kb
Host	smart-9ef08fd8-0fa7-472e-9df1-558bf6c291d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559069682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.559069682
Directory	/workspace/2.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3941326427
Short name	T73
Test name
Test status
Simulation time	7830375912 ps
CPU time	14.61 seconds
Started	Apr 18 01:23:51 PM PDT 24
Finished	Apr 18 01:24:06 PM PDT 24
Peak memory	220164 kb
Host	smart-29fa576d-6b58-48b5-b254-9f6d1cbbef7d
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941326427 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3941326427
Directory	/workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.4171981241
Short name	T125
Test name
Test status
Simulation time	13262117158 ps
CPU time	16.93 seconds
Started	Apr 18 01:23:58 PM PDT 24
Finished	Apr 18 01:24:15 PM PDT 24
Peak memory	215916 kb
Host	smart-489b3ae7-8c1e-4d69-b1cf-bf26ded28f62
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171981241 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.4171981241
Directory	/workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2609599433
Short name	T210
Test name
Test status
Simulation time	25049167899 ps
CPU time	26.53 seconds
Started	Apr 18 01:23:55 PM PDT 24
Finished	Apr 18 01:24:22 PM PDT 24
Peak memory	221496 kb
Host	smart-9cc5f3fc-07b1-4af9-88a3-4dc95abd211f
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609599433 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.2609599433
Directory	/workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.4004706567
Short name	T253
Test name
Test status
Simulation time	16275151676 ps
CPU time	14.17 seconds
Started	Apr 18 01:23:43 PM PDT 24
Finished	Apr 18 01:23:57 PM PDT 24
Peak memory	213728 kb
Host	smart-1a006142-b936-470e-b91e-147f256dbff7
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004706567 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.4004706567
Directory	/workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.1954813590
Short name	T205
Test name
Test status
Simulation time	4817497630 ps
CPU time	10.94 seconds
Started	Apr 18 01:23:54 PM PDT 24
Finished	Apr 18 01:24:06 PM PDT 24
Peak memory	221440 kb
Host	smart-11d2abea-2ed0-4dcc-90f3-a0a63dd7ebf5
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954813590 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.1954813590
Directory	/workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2739569878
Short name	T83
Test name
Test status
Simulation time	2222270225 ps
CPU time	66.75 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:24:32 PM PDT 24
Peak memory	217984 kb
Host	smart-b864c93e-428f-461d-95ca-6f5cd8552b10
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739569878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.2739569878
Directory	/workspace/3.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1008226973
Short name	T78
Test name
Test status
Simulation time	5097108080 ps
CPU time	36.53 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:24:05 PM PDT 24
Peak memory	205000 kb
Host	smart-ddc1475d-81f0-4da1-975c-1d0534114857
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008226973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1008226973
Directory	/workspace/3.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1846308196
Short name	T48
Test name
Test status
Simulation time	470619502 ps
CPU time	2.5 seconds
Started	Apr 18 01:23:23 PM PDT 24
Finished	Apr 18 01:23:26 PM PDT 24
Peak memory	213136 kb
Host	smart-982ea803-2d4d-4232-a8b9-465d7d394268
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846308196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1846308196
Directory	/workspace/3.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1934901110
Short name	T267
Test name
Test status
Simulation time	370800120 ps
CPU time	4.01 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:32 PM PDT 24
Peak memory	219532 kb
Host	smart-283e8dff-e33e-4c64-b83a-eb93c0f0e9cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934901110 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1934901110
Directory	/workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1114613922
Short name	T109
Test name
Test status
Simulation time	98962311 ps
CPU time	1.43 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:30 PM PDT 24
Peak memory	213084 kb
Host	smart-89cf44b7-bb7b-4b8b-b6b1-0fb2cb00139d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114613922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1114613922
Directory	/workspace/3.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2722646534
Short name	T179
Test name
Test status
Simulation time	6788270290 ps
CPU time	15.21 seconds
Started	Apr 18 01:23:27 PM PDT 24
Finished	Apr 18 01:23:43 PM PDT 24
Peak memory	204860 kb
Host	smart-0b4c8640-56af-42ac-bdc4-b7a5fe6688e0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722646534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.2722646534
Directory	/workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.777596036
Short name	T274
Test name
Test status
Simulation time	48752158264 ps
CPU time	131.2 seconds
Started	Apr 18 01:23:26 PM PDT 24
Finished	Apr 18 01:25:38 PM PDT 24
Peak memory	205008 kb
Host	smart-d1b4053e-26bc-4fbc-b8c6-558eb5b6e659
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777596036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _bit_bash.777596036
Directory	/workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.88755486
Short name	T97
Test name
Test status
Simulation time	224052340 ps
CPU time	1.25 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:23:26 PM PDT 24
Peak memory	204916 kb
Host	smart-3f3cfbc8-ea78-474e-bbb5-4ecd7b7f740b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88755486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_ hw_reset.88755486
Directory	/workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2254453367
Short name	T175
Test name
Test status
Simulation time	637380323 ps
CPU time	1.61 seconds
Started	Apr 18 01:23:26 PM PDT 24
Finished	Apr 18 01:23:28 PM PDT 24
Peak memory	204892 kb
Host	smart-cfa45275-7bf3-4aed-9d4e-09312d1da047
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254453367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2 254453367
Directory	/workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.582738556
Short name	T252
Test name
Test status
Simulation time	80706999 ps
CPU time	0.9 seconds
Started	Apr 18 01:23:21 PM PDT 24
Finished	Apr 18 01:23:22 PM PDT 24
Peak memory	204584 kb
Host	smart-13d8cd07-4a43-4e07-b882-1b34d3c753b0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582738556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _aliasing.582738556
Directory	/workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2676762555
Short name	T197
Test name
Test status
Simulation time	6097255003 ps
CPU time	14.85 seconds
Started	Apr 18 01:23:26 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	204924 kb
Host	smart-fa703b87-123d-4113-ac64-0233e3c16c95
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676762555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2676762555
Directory	/workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2681086215
Short name	T178
Test name
Test status
Simulation time	43493511 ps
CPU time	0.7 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:26 PM PDT 24
Peak memory	204736 kb
Host	smart-13c96722-914e-41b6-ac2c-11f804701e58
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681086215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.2681086215
Directory	/workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3184892597
Short name	T196
Test name
Test status
Simulation time	78894750 ps
CPU time	0.74 seconds
Started	Apr 18 01:23:21 PM PDT 24
Finished	Apr 18 01:23:22 PM PDT 24
Peak memory	204644 kb
Host	smart-b99be6b8-f1e2-496e-a828-bb89cef44f80
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184892597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3 184892597
Directory	/workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.333604839
Short name	T232
Test name
Test status
Simulation time	28313219 ps
CPU time	0.65 seconds
Started	Apr 18 01:23:29 PM PDT 24
Finished	Apr 18 01:23:30 PM PDT 24
Peak memory	204588 kb
Host	smart-58128388-e4ee-40d8-8f9b-911d4ef2d3fe
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333604839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part ial_access.333604839
Directory	/workspace/3.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1757373100
Short name	T289
Test name
Test status
Simulation time	45751478 ps
CPU time	0.71 seconds
Started	Apr 18 01:23:34 PM PDT 24
Finished	Apr 18 01:23:35 PM PDT 24
Peak memory	204624 kb
Host	smart-edcd855b-8fc6-4d19-ae4f-7a67e55618f8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757373100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1757373100
Directory	/workspace/3.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2025915168
Short name	T240
Test name
Test status
Simulation time	594177942 ps
CPU time	7.39 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:36 PM PDT 24
Peak memory	204876 kb
Host	smart-ba8a603d-3b59-4082-ad6e-19f8793b47e9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025915168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.2025915168
Directory	/workspace/3.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.922423011
Short name	T85
Test name
Test status
Simulation time	106124890 ps
CPU time	5.58 seconds
Started	Apr 18 01:23:43 PM PDT 24
Finished	Apr 18 01:23:49 PM PDT 24
Peak memory	213140 kb
Host	smart-4ec6186a-52cf-4d56-bb4c-b3b8279820b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922423011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.922423011
Directory	/workspace/3.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.170914469
Short name	T266
Test name
Test status
Simulation time	320007711 ps
CPU time	8.55 seconds
Started	Apr 18 01:23:35 PM PDT 24
Finished	Apr 18 01:23:44 PM PDT 24
Peak memory	213180 kb
Host	smart-8b4890fb-f9fc-4b59-a352-f7cdf4903f04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170914469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.170914469
Directory	/workspace/3.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.3931621890
Short name	T121
Test name
Test status
Simulation time	13056451198 ps
CPU time	14.95 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:55 PM PDT 24
Peak memory	214960 kb
Host	smart-54ac8901-e17e-4fa2-981f-2f28385b05e1
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931621890 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.3931621890
Directory	/workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1535558051
Short name	T237
Test name
Test status
Simulation time	16844952259 ps
CPU time	46.15 seconds
Started	Apr 18 01:23:51 PM PDT 24
Finished	Apr 18 01:24:38 PM PDT 24
Peak memory	229520 kb
Host	smart-adc4ecf5-5741-42e8-b3e5-730a45ebea46
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535558051 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1535558051
Directory	/workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.4239557426
Short name	T228
Test name
Test status
Simulation time	44751227937 ps
CPU time	11.96 seconds
Started	Apr 18 01:23:56 PM PDT 24
Finished	Apr 18 01:24:09 PM PDT 24
Peak memory	219088 kb
Host	smart-77b63943-758f-46cd-92e4-325262c0b468
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239557426 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.4239557426
Directory	/workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3816925917
Short name	T111
Test name
Test status
Simulation time	6696504171 ps
CPU time	73.27 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:24:37 PM PDT 24
Peak memory	205144 kb
Host	smart-3b3311d8-8b70-41a2-9f6b-f6903979815f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816925917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.3816925917
Directory	/workspace/4.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2593818584
Short name	T223
Test name
Test status
Simulation time	2932295089 ps
CPU time	54.82 seconds
Started	Apr 18 01:23:26 PM PDT 24
Finished	Apr 18 01:24:22 PM PDT 24
Peak memory	205136 kb
Host	smart-8cf62757-3723-4945-9547-b4f2dcb0d3c3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593818584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2593818584
Directory	/workspace/4.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2104976710
Short name	T106
Test name
Test status
Simulation time	214956576 ps
CPU time	2.44 seconds
Started	Apr 18 01:23:30 PM PDT 24
Finished	Apr 18 01:23:33 PM PDT 24
Peak memory	213176 kb
Host	smart-0c8de9c1-f8c1-4318-8795-d18101553add
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104976710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2104976710
Directory	/workspace/4.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1683420457
Short name	T84
Test name
Test status
Simulation time	73475774 ps
CPU time	1.98 seconds
Started	Apr 18 01:23:32 PM PDT 24
Finished	Apr 18 01:23:35 PM PDT 24
Peak memory	213280 kb
Host	smart-c1149d83-40e8-40a7-ab74-cb0ce049086b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683420457 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1683420457
Directory	/workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2949731468
Short name	T249
Test name
Test status
Simulation time	202883543 ps
CPU time	2.4 seconds
Started	Apr 18 01:23:26 PM PDT 24
Finished	Apr 18 01:23:29 PM PDT 24
Peak memory	213160 kb
Host	smart-0467768c-1556-44a2-82a1-286c705d8766
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949731468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2949731468
Directory	/workspace/4.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4093026468
Short name	T281
Test name
Test status
Simulation time	8753167293 ps
CPU time	19.41 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	204940 kb
Host	smart-b3321560-48ae-47df-94f7-759cdf591b9e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093026468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.4093026468
Directory	/workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1300323692
Short name	T314
Test name
Test status
Simulation time	22125070409 ps
CPU time	66.45 seconds
Started	Apr 18 01:23:27 PM PDT 24
Finished	Apr 18 01:24:33 PM PDT 24
Peak memory	204932 kb
Host	smart-c8bc0e70-7387-4e92-aafc-a389b238b323
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300323692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_bit_bash.1300323692
Directory	/workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4159515750
Short name	T96
Test name
Test status
Simulation time	639797327 ps
CPU time	3.44 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:30 PM PDT 24
Peak memory	204936 kb
Host	smart-b6cf941f-f77b-4711-86fb-82c598c9377f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159515750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.4159515750
Directory	/workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3353755981
Short name	T245
Test name
Test status
Simulation time	266514579 ps
CPU time	1.58 seconds
Started	Apr 18 01:23:26 PM PDT 24
Finished	Apr 18 01:23:28 PM PDT 24
Peak memory	204848 kb
Host	smart-abc0fde2-d82a-49b5-9df6-1606b5b6a4bd
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353755981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 353755981
Directory	/workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2708952830
Short name	T224
Test name
Test status
Simulation time	208856354 ps
CPU time	0.78 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:23:39 PM PDT 24
Peak memory	204620 kb
Host	smart-fecd6850-b052-4423-8519-903ae464741c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708952830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.2708952830
Directory	/workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2444855429
Short name	T184
Test name
Test status
Simulation time	1764305950 ps
CPU time	5.16 seconds
Started	Apr 18 01:23:23 PM PDT 24
Finished	Apr 18 01:23:29 PM PDT 24
Peak memory	204816 kb
Host	smart-d57f2bd8-50f9-4232-b4c8-bc5f5a4f1b25
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444855429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2444855429
Directory	/workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.544789702
Short name	T297
Test name
Test status
Simulation time	106499477 ps
CPU time	1.02 seconds
Started	Apr 18 01:23:34 PM PDT 24
Finished	Apr 18 01:23:36 PM PDT 24
Peak memory	204688 kb
Host	smart-ba7ad6b9-4e03-44c6-a470-aefbab228de4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544789702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _hw_reset.544789702
Directory	/workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2604748785
Short name	T192
Test name
Test status
Simulation time	92340123 ps
CPU time	0.73 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:29 PM PDT 24
Peak memory	204564 kb
Host	smart-5583e33d-995b-43a0-a73f-03f836bb46ca
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604748785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 604748785
Directory	/workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.108227833
Short name	T173
Test name
Test status
Simulation time	35201389 ps
CPU time	0.7 seconds
Started	Apr 18 01:23:25 PM PDT 24
Finished	Apr 18 01:23:26 PM PDT 24
Peak memory	204648 kb
Host	smart-10dcac17-2813-4c56-b23e-eeac7f216c3e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108227833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part ial_access.108227833
Directory	/workspace/4.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3537670410
Short name	T215
Test name
Test status
Simulation time	46259868 ps
CPU time	0.67 seconds
Started	Apr 18 01:23:24 PM PDT 24
Finished	Apr 18 01:23:25 PM PDT 24
Peak memory	204632 kb
Host	smart-a8d0f1c7-a663-4612-94b3-f517c6946a84
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537670410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3537670410
Directory	/workspace/4.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1817857587
Short name	T292
Test name
Test status
Simulation time	219477295 ps
CPU time	4.1 seconds
Started	Apr 18 01:23:23 PM PDT 24
Finished	Apr 18 01:23:28 PM PDT 24
Peak memory	205064 kb
Host	smart-fd2aca69-e4ef-45a1-bd37-b67e50b352b4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817857587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1817857587
Directory	/workspace/4.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3064940161
Short name	T279
Test name
Test status
Simulation time	118129896 ps
CPU time	1.99 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:31 PM PDT 24
Peak memory	213120 kb
Host	smart-0e5e23ed-9ed6-496b-bb16-6d2a7b3980f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064940161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3064940161
Directory	/workspace/4.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3375995027
Short name	T261
Test name
Test status
Simulation time	2069100929 ps
CPU time	3.37 seconds
Started	Apr 18 01:23:32 PM PDT 24
Finished	Apr 18 01:23:35 PM PDT 24
Peak memory	216280 kb
Host	smart-952f4cf6-2cf2-49a3-955a-b80475f351c5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375995027 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3375995027
Directory	/workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.937730926
Short name	T277
Test name
Test status
Simulation time	114088634 ps
CPU time	1.55 seconds
Started	Apr 18 01:23:34 PM PDT 24
Finished	Apr 18 01:23:36 PM PDT 24
Peak memory	213120 kb
Host	smart-0623a78c-588f-45d5-a32b-dbc8c624657d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937730926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.937730926
Directory	/workspace/5.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.518615962
Short name	T312
Test name
Test status
Simulation time	452740436 ps
CPU time	2.25 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:47 PM PDT 24
Peak memory	204776 kb
Host	smart-04f02cf4-4cee-4ad3-8987-a4f166cb8a88
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518615962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.518615962
Directory	/workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3204368743
Short name	T294
Test name
Test status
Simulation time	28620357 ps
CPU time	0.8 seconds
Started	Apr 18 01:23:35 PM PDT 24
Finished	Apr 18 01:23:37 PM PDT 24
Peak memory	204604 kb
Host	smart-db24afa2-e9fe-4b4b-a0dc-df779f52f7c8
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204368743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3 204368743
Directory	/workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1570061805
Short name	T117
Test name
Test status
Simulation time	561332538 ps
CPU time	4.18 seconds
Started	Apr 18 01:23:34 PM PDT 24
Finished	Apr 18 01:23:38 PM PDT 24
Peak memory	205060 kb
Host	smart-3e4e25d4-51db-41a5-a88a-4f723c6f59c4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570061805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1570061805
Directory	/workspace/5.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.671084051
Short name	T275
Test name
Test status
Simulation time	84235483 ps
CPU time	2.24 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	213244 kb
Host	smart-5e63413a-223b-43c3-a2a7-3d05c183f58a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671084051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.671084051
Directory	/workspace/5.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1926805291
Short name	T135
Test name
Test status
Simulation time	220777569 ps
CPU time	8.25 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:53 PM PDT 24
Peak memory	221316 kb
Host	smart-f0ce45da-eebb-4405-936a-936495700f7e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926805291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1926805291
Directory	/workspace/5.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.103272568
Short name	T299
Test name
Test status
Simulation time	590799811 ps
CPU time	2.46 seconds
Started	Apr 18 01:23:43 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	216464 kb
Host	smart-a448588c-0ae9-4a2d-82f7-201d00f07720
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103272568 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.103272568
Directory	/workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2145396817
Short name	T79
Test name
Test status
Simulation time	50637973 ps
CPU time	1.45 seconds
Started	Apr 18 01:23:33 PM PDT 24
Finished	Apr 18 01:23:35 PM PDT 24
Peak memory	212984 kb
Host	smart-2ab6cbda-bae5-4a73-923f-b6538116a00d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145396817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2145396817
Directory	/workspace/6.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1587192851
Short name	T217
Test name
Test status
Simulation time	998218529 ps
CPU time	3.83 seconds
Started	Apr 18 01:23:46 PM PDT 24
Finished	Apr 18 01:23:50 PM PDT 24
Peak memory	204548 kb
Host	smart-d531f0d3-3009-4a38-b6c6-10bb16287d2a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587192851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1 587192851
Directory	/workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.63279064
Short name	T250
Test name
Test status
Simulation time	35432995 ps
CPU time	0.7 seconds
Started	Apr 18 01:23:45 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	204660 kb
Host	smart-671e9971-0bc6-4a9f-aaef-3be7b0929e4a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63279064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.63279064
Directory	/workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1122358929
Short name	T265
Test name
Test status
Simulation time	1399458759 ps
CPU time	4.2 seconds
Started	Apr 18 01:23:28 PM PDT 24
Finished	Apr 18 01:23:33 PM PDT 24
Peak memory	204992 kb
Host	smart-ac3153d8-1b17-4d85-9395-f634634e4423
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122358929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.1122358929
Directory	/workspace/6.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.476108516
Short name	T270
Test name
Test status
Simulation time	13919279534 ps
CPU time	45.72 seconds
Started	Apr 18 01:23:30 PM PDT 24
Finished	Apr 18 01:24:16 PM PDT 24
Peak memory	221372 kb
Host	smart-0ac762c7-eb3d-4c09-90eb-560bff512385
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476108516 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.476108516
Directory	/workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.494268944
Short name	T264
Test name
Test status
Simulation time	146808040 ps
CPU time	3.24 seconds
Started	Apr 18 01:23:46 PM PDT 24
Finished	Apr 18 01:23:50 PM PDT 24
Peak memory	213256 kb
Host	smart-dcefb0b8-4c1b-44c7-8bd3-32608ba310a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494268944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.494268944
Directory	/workspace/6.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3480356672
Short name	T283
Test name
Test status
Simulation time	408755092 ps
CPU time	8 seconds
Started	Apr 18 01:23:31 PM PDT 24
Finished	Apr 18 01:23:40 PM PDT 24
Peak memory	221284 kb
Host	smart-5c38e80c-7c5c-47b6-ab95-16f02cbd4961
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480356672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3480356672
Directory	/workspace/6.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2888044446
Short name	T67
Test name
Test status
Simulation time	3347709647 ps
CPU time	3.86 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:44 PM PDT 24
Peak memory	217616 kb
Host	smart-305ed186-8d71-490a-ab84-76761b26ae56
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888044446 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2888044446
Directory	/workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1325009516
Short name	T82
Test name
Test status
Simulation time	141872851 ps
CPU time	2.07 seconds
Started	Apr 18 01:23:35 PM PDT 24
Finished	Apr 18 01:23:37 PM PDT 24
Peak memory	218584 kb
Host	smart-b8f312e2-fb0a-473c-b35d-2cb0639055a9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325009516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1325009516
Directory	/workspace/7.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3889123409
Short name	T189
Test name
Test status
Simulation time	2320614580 ps
CPU time	4.16 seconds
Started	Apr 18 01:23:32 PM PDT 24
Finished	Apr 18 01:23:37 PM PDT 24
Peak memory	204904 kb
Host	smart-2ec8b32c-aa86-4eee-b0fb-d9240ee29c95
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889123409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 889123409
Directory	/workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.86617604
Short name	T198
Test name
Test status
Simulation time	92076872 ps
CPU time	0.78 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	204656 kb
Host	smart-4f5414a5-3212-43f7-b9af-8176238ddf5e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86617604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.86617604
Directory	/workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.241621557
Short name	T300
Test name
Test status
Simulation time	86369830 ps
CPU time	3.63 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:48 PM PDT 24
Peak memory	205008 kb
Host	smart-fb6f5929-5c07-4a50-a5bf-8cab4cb544b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241621557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c sr_outstanding.241621557
Directory	/workspace/7.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.35165846
Short name	T269
Test name
Test status
Simulation time	509284458 ps
CPU time	7.02 seconds
Started	Apr 18 01:23:44 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	213228 kb
Host	smart-c88b6aa2-342e-4448-8b8f-db6cf0c44445
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35165846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.35165846
Directory	/workspace/7.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1746506659
Short name	T128
Test name
Test status
Simulation time	2633427566 ps
CPU time	9.6 seconds
Started	Apr 18 01:23:43 PM PDT 24
Finished	Apr 18 01:23:53 PM PDT 24
Peak memory	213304 kb
Host	smart-4a709814-0749-4795-b4ee-defae75ddc39
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746506659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1746506659
Directory	/workspace/7.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2163191213
Short name	T225
Test name
Test status
Simulation time	86861544 ps
CPU time	2.32 seconds
Started	Apr 18 01:23:35 PM PDT 24
Finished	Apr 18 01:23:38 PM PDT 24
Peak memory	217180 kb
Host	smart-ac2d52f2-d25b-4e53-8fca-0291570b0555
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163191213 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2163191213
Directory	/workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.639790434
Short name	T247
Test name
Test status
Simulation time	585243264 ps
CPU time	1.81 seconds
Started	Apr 18 01:23:42 PM PDT 24
Finished	Apr 18 01:23:44 PM PDT 24
Peak memory	204760 kb
Host	smart-a1908546-6813-4329-a6c4-86ea95cde39b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639790434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.639790434
Directory	/workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3244880019
Short name	T242
Test name
Test status
Simulation time	69232881 ps
CPU time	0.81 seconds
Started	Apr 18 01:23:32 PM PDT 24
Finished	Apr 18 01:23:33 PM PDT 24
Peak memory	204672 kb
Host	smart-004fe73b-cd66-4ef6-a8b0-77ca0f864a95
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244880019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 244880019
Directory	/workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4145389524
Short name	T104
Test name
Test status
Simulation time	200226209 ps
CPU time	6.4 seconds
Started	Apr 18 01:23:39 PM PDT 24
Finished	Apr 18 01:23:46 PM PDT 24
Peak memory	204980 kb
Host	smart-59f5ac5a-992c-4c89-9e40-d423430e9672
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145389524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.4145389524
Directory	/workspace/8.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3201727088
Short name	T60
Test name
Test status
Simulation time	10418641929 ps
CPU time	18.45 seconds
Started	Apr 18 01:23:35 PM PDT 24
Finished	Apr 18 01:23:54 PM PDT 24
Peak memory	214472 kb
Host	smart-8828bafb-55b1-4b97-a595-1b32f9116bca
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201727088 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3201727088
Directory	/workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2710791360
Short name	T74
Test name
Test status
Simulation time	291058087 ps
CPU time	2.49 seconds
Started	Apr 18 01:23:47 PM PDT 24
Finished	Apr 18 01:23:49 PM PDT 24
Peak memory	213188 kb
Host	smart-ee42d9d8-7a97-4b30-b2da-5a0b82bc96eb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710791360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2710791360
Directory	/workspace/8.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2850860073
Short name	T216
Test name
Test status
Simulation time	1701480758 ps
CPU time	4.7 seconds
Started	Apr 18 01:23:33 PM PDT 24
Finished	Apr 18 01:23:38 PM PDT 24
Peak memory	218956 kb
Host	smart-27fb28f4-a698-46e1-9177-3223795db2dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850860073 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2850860073
Directory	/workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1551544315
Short name	T98
Test name
Test status
Simulation time	173306223 ps
CPU time	1.59 seconds
Started	Apr 18 01:23:49 PM PDT 24
Finished	Apr 18 01:23:51 PM PDT 24
Peak memory	217908 kb
Host	smart-04477431-22cd-42ae-a9c4-a5335860d713
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551544315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1551544315
Directory	/workspace/9.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3069463702
Short name	T234
Test name
Test status
Simulation time	2151449005 ps
CPU time	2 seconds
Started	Apr 18 01:23:38 PM PDT 24
Finished	Apr 18 01:23:41 PM PDT 24
Peak memory	204540 kb
Host	smart-80e4165a-7d18-47bf-8f94-3c40b0396f93
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069463702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 069463702
Directory	/workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3970224220
Short name	T255
Test name
Test status
Simulation time	58404931 ps
CPU time	0.72 seconds
Started	Apr 18 01:23:48 PM PDT 24
Finished	Apr 18 01:23:49 PM PDT 24
Peak memory	204592 kb
Host	smart-04129f81-11f9-4e01-8dd0-9e46312d9337
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970224220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3 970224220
Directory	/workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2566408496
Short name	T291
Test name
Test status
Simulation time	596506546 ps
CPU time	4.44 seconds
Started	Apr 18 01:23:40 PM PDT 24
Finished	Apr 18 01:23:45 PM PDT 24
Peak memory	205056 kb
Host	smart-40832be4-e77b-445f-b859-a5e0698b004c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566408496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.2566408496
Directory	/workspace/9.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.913444151
Short name	T288
Test name
Test status
Simulation time	886924214 ps
CPU time	3.09 seconds
Started	Apr 18 01:23:41 PM PDT 24
Finished	Apr 18 01:23:44 PM PDT 24
Peak memory	213220 kb
Host	smart-112a7200-5cd9-4ff4-a714-24bcf19385a7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913444151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.913444151
Directory	/workspace/9.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1595266452
Short name	T132
Test name
Test status
Simulation time	4645195703 ps
CPU time	10.48 seconds
Started	Apr 18 01:23:47 PM PDT 24
Finished	Apr 18 01:23:58 PM PDT 24
Peak memory	213236 kb
Host	smart-de8d1b2c-8fde-4d9f-a1a4-c0c3d87957b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595266452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1595266452
Directory	/workspace/9.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_dm_alert_test.7204044
Short name	T156
Test name
Test status
Simulation time	19767627 ps
CPU time	0.69 seconds
Started	Apr 18 01:25:57 PM PDT 24
Finished	Apr 18 01:25:58 PM PDT 24
Peak memory	205092 kb
Host	smart-9ded21f7-a4e1-4cde-b7c7-884517bd34d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7204044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.7204044
Directory	/workspace/0.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/0.rv_dm_cmderr_busy.460954176
Short name	T10
Test name
Test status
Simulation time	2528719207 ps
CPU time	6.42 seconds
Started	Apr 18 01:25:43 PM PDT 24
Finished	Apr 18 01:25:50 PM PDT 24
Peak memory	205376 kb
Host	smart-6e8cc665-3493-40cd-b651-73e610f05213
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460954176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.460954176
Directory	/workspace/0.rv_dm_cmderr_busy/latest

Test location	/workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1944741203
Short name	T138
Test name
Test status
Simulation time	83557769 ps
CPU time	0.71 seconds
Started	Apr 18 01:25:45 PM PDT 24
Finished	Apr 18 01:25:47 PM PDT 24
Peak memory	205100 kb
Host	smart-24695f12-c5ee-4b1a-a7d9-e2888151d9d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944741203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1944741203
Directory	/workspace/0.rv_dm_dataaddr_rw_access/latest

Test location	/workspace/coverage/default/0.rv_dm_hart_unavail.3443427898
Short name	T57
Test name
Test status
Simulation time	59568494 ps
CPU time	0.74 seconds
Started	Apr 18 01:25:46 PM PDT 24
Finished	Apr 18 01:25:48 PM PDT 24
Peak memory	204980 kb
Host	smart-c74eaf30-3b69-4144-929d-a5ef55ec23a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443427898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3443427898
Directory	/workspace/0.rv_dm_hart_unavail/latest

Test location	/workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2660379102
Short name	T163
Test name
Test status
Simulation time	480084432 ps
CPU time	0.99 seconds
Started	Apr 18 01:25:48 PM PDT 24
Finished	Apr 18 01:25:50 PM PDT 24
Peak memory	204940 kb
Host	smart-da3b9172-1a29-4459-8e0e-3e70494d7d67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660379102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2660379102
Directory	/workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.509009684
Short name	T30
Test name
Test status
Simulation time	575245092 ps
CPU time	1.11 seconds
Started	Apr 18 01:25:48 PM PDT 24
Finished	Apr 18 01:25:49 PM PDT 24
Peak memory	205084 kb
Host	smart-98b093c7-b823-4b25-8fe1-f5669874151d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509009684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.509009684
Directory	/workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspace/coverage/default/0.rv_dm_mem_tl_access_halted.435970574
Short name	T5
Test name
Test status
Simulation time	232449041 ps
CPU time	1.1 seconds
Started	Apr 18 01:25:47 PM PDT 24
Finished	Apr 18 01:25:48 PM PDT 24
Peak memory	204972 kb
Host	smart-3ec282e2-32ff-40fe-b1a9-16d268563ada
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435970574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.435970574
Directory	/workspace/0.rv_dm_mem_tl_access_halted/latest

Test location	/workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3224765658
Short name	T171
Test name
Test status
Simulation time	116893188 ps
CPU time	0.79 seconds
Started	Apr 18 01:25:46 PM PDT 24
Finished	Apr 18 01:25:47 PM PDT 24
Peak memory	205096 kb
Host	smart-b909f91c-de8c-405e-8fb6-ccadf2927efe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224765658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3224765658
Directory	/workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location	/workspace/coverage/default/0.rv_dm_ndmreset_req.4246740161
Short name	T15
Test name
Test status
Simulation time	2031901974 ps
CPU time	6.94 seconds
Started	Apr 18 01:25:50 PM PDT 24
Finished	Apr 18 01:25:57 PM PDT 24
Peak memory	205288 kb
Host	smart-a8047fe9-7fed-41fc-b9a5-46542641cbd1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246740161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4246740161
Directory	/workspace/0.rv_dm_ndmreset_req/latest

Test location	/workspace/coverage/default/0.rv_dm_rom_read_access.3780687598
Short name	T14
Test name
Test status
Simulation time	27976338 ps
CPU time	0.79 seconds
Started	Apr 18 01:25:47 PM PDT 24
Finished	Apr 18 01:25:48 PM PDT 24
Peak memory	213296 kb
Host	smart-7685ce6c-f111-4167-a5c9-6a55aa644f4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780687598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3780687598
Directory	/workspace/0.rv_dm_rom_read_access/latest

Test location	/workspace/coverage/default/0.rv_dm_sba_tl_access.1483088819
Short name	T91
Test name
Test status
Simulation time	1412177759 ps
CPU time	3.56 seconds
Started	Apr 18 01:25:49 PM PDT 24
Finished	Apr 18 01:25:53 PM PDT 24
Peak memory	205260 kb
Host	smart-c5e6458f-69ab-4a63-8868-ab566d249fbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483088819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1483088819
Directory	/workspace/0.rv_dm_sba_tl_access/latest

Test location	/workspace/coverage/default/0.rv_dm_sec_cm.1339459491
Short name	T34
Test name
Test status
Simulation time	1266965067 ps
CPU time	1.29 seconds
Started	Apr 18 01:25:52 PM PDT 24
Finished	Apr 18 01:25:54 PM PDT 24
Peak memory	229300 kb
Host	smart-a38f1979-ec9f-4551-9545-ec2bf6963a6b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339459491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1339459491
Directory	/workspace/0.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/0.rv_dm_smoke.3660727725
Short name	T165
Test name
Test status
Simulation time	737195174 ps
CPU time	1.5 seconds
Started	Apr 18 01:25:44 PM PDT 24
Finished	Apr 18 01:25:46 PM PDT 24
Peak memory	205168 kb
Host	smart-9236c7b7-b839-4310-8921-f5db0e9c52df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660727725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3660727725
Directory	/workspace/0.rv_dm_smoke/latest

Test location	/workspace/coverage/default/0.rv_dm_tap_fsm.433117749
Short name	T20
Test name
Test status
Simulation time	2356158167 ps
CPU time	3.02 seconds
Started	Apr 18 01:25:44 PM PDT 24
Finished	Apr 18 01:25:48 PM PDT 24
Peak memory	205344 kb
Host	smart-2d87844a-18af-4bcc-803a-920306fdc916
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433117749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.433117749
Directory	/workspace/0.rv_dm_tap_fsm/latest

Test location	/workspace/coverage/default/1.rv_dm_alert_test.2862057380
Short name	T120
Test name
Test status
Simulation time	28415039 ps
CPU time	0.72 seconds
Started	Apr 18 01:26:00 PM PDT 24
Finished	Apr 18 01:26:01 PM PDT 24
Peak memory	205008 kb
Host	smart-9f133928-7792-49c5-8036-6dc2c08770d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862057380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2862057380
Directory	/workspace/1.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/1.rv_dm_cmderr_busy.1420049141
Short name	T25
Test name
Test status
Simulation time	5316639900 ps
CPU time	5.25 seconds
Started	Apr 18 01:25:55 PM PDT 24
Finished	Apr 18 01:26:01 PM PDT 24
Peak memory	205400 kb
Host	smart-550d2eb6-8a7d-43f2-9848-11fbc0ef9ce3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420049141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1420049141
Directory	/workspace/1.rv_dm_cmderr_busy/latest

Test location	/workspace/coverage/default/1.rv_dm_cmderr_exception.3727137320
Short name	T18
Test name
Test status
Simulation time	661317864 ps
CPU time	1.35 seconds
Started	Apr 18 01:25:54 PM PDT 24
Finished	Apr 18 01:25:56 PM PDT 24
Peak memory	205292 kb
Host	smart-0fbb2a83-76a4-4300-8145-afee80fb4199
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727137320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3727137320
Directory	/workspace/1.rv_dm_cmderr_exception/latest

Test location	/workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1883670851
Short name	T6
Test name
Test status
Simulation time	242889903 ps
CPU time	1.34 seconds
Started	Apr 18 01:25:52 PM PDT 24
Finished	Apr 18 01:25:53 PM PDT 24
Peak memory	204948 kb
Host	smart-e7e15d66-7aed-4eff-a5fc-3792cf87768b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883670851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1883670851
Directory	/workspace/1.rv_dm_cmderr_halt_resume/latest

Test location	/workspace/coverage/default/1.rv_dm_cmderr_not_supported.1639397892
Short name	T9
Test name
Test status
Simulation time	3161675962 ps
CPU time	3.09 seconds
Started	Apr 18 01:25:53 PM PDT 24
Finished	Apr 18 01:25:56 PM PDT 24
Peak memory	205404 kb
Host	smart-933aba9d-e58a-47e7-aee1-0e11023fee49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639397892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1639397892
Directory	/workspace/1.rv_dm_cmderr_not_supported/latest

Test location	/workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3495065954
Short name	T16
Test name
Test status
Simulation time	34219369 ps
CPU time	0.75 seconds
Started	Apr 18 01:25:51 PM PDT 24
Finished	Apr 18 01:25:52 PM PDT 24
Peak memory	205012 kb
Host	smart-5ba44f7a-3a7a-4dc6-99ae-f281547b61db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495065954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3495065954
Directory	/workspace/1.rv_dm_dataaddr_rw_access/latest

Test location	/workspace/coverage/default/1.rv_dm_hart_unavail.1862086802
Short name	T164
Test name
Test status
Simulation time	46487128 ps
CPU time	0.72 seconds
Started	Apr 18 01:25:58 PM PDT 24
Finished	Apr 18 01:25:59 PM PDT 24
Peak memory	204964 kb
Host	smart-8d5e25d6-40d1-4fe4-9a49-8777abfaf4eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862086802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1862086802
Directory	/workspace/1.rv_dm_hart_unavail/latest

Test location	/workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2121380739
Short name	T172
Test name
Test status
Simulation time	100269963 ps
CPU time	0.8 seconds
Started	Apr 18 01:25:57 PM PDT 24
Finished	Apr 18 01:25:58 PM PDT 24
Peak memory	204976 kb
Host	smart-84206ac9-53a6-41a5-b92f-4bba8c7e3358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121380739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2121380739
Directory	/workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location	/workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3863199294
Short name	T31
Test name
Test status
Simulation time	199962207 ps
CPU time	0.97 seconds
Started	Apr 18 01:25:53 PM PDT 24
Finished	Apr 18 01:25:54 PM PDT 24
Peak memory	205112 kb
Host	smart-ef6f942b-8204-41c5-b5bb-1a65ab1d6f09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863199294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3863199294
Directory	/workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location	/workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2499272392
Short name	T167
Test name
Test status
Simulation time	138115904 ps
CPU time	1.09 seconds
Started	Apr 18 01:25:53 PM PDT 24
Finished	Apr 18 01:25:55 PM PDT 24
Peak memory	205108 kb
Host	smart-b2539a2c-018b-4330-8dee-73985705d0f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499272392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2499272392
Directory	/workspace/1.rv_dm_mem_tl_access_halted/latest

Test location	/workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1800945765
Short name	T12
Test name
Test status
Simulation time	172495699 ps
CPU time	0.99 seconds
Started	Apr 18 01:25:53 PM PDT 24
Finished	Apr 18 01:25:55 PM PDT 24
Peak memory	205168 kb
Host	smart-8030f1c0-20d3-4c9c-a78b-e2986645aabd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800945765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1800945765
Directory	/workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location	/workspace/coverage/default/1.rv_dm_ndmreset_req.119252199
Short name	T21
Test name
Test status
Simulation time	767293775 ps
CPU time	2.68 seconds
Started	Apr 18 01:25:53 PM PDT 24
Finished	Apr 18 01:25:56 PM PDT 24
Peak memory	205240 kb
Host	smart-31e48977-ac13-4586-8e65-7f40d4409721
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119252199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.119252199
Directory	/workspace/1.rv_dm_ndmreset_req/latest

Test location	/workspace/coverage/default/1.rv_dm_progbuf_busy.1275465365
Short name	T4
Test name
Test status
Simulation time	84634051 ps
CPU time	0.89 seconds
Started	Apr 18 01:25:52 PM PDT 24
Finished	Apr 18 01:25:53 PM PDT 24
Peak memory	205084 kb
Host	smart-2bb5fe9d-8b23-41bb-abbe-c5d1913a7d53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275465365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1275465365
Directory	/workspace/1.rv_dm_progbuf_busy/latest

Test location	/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3190130946
Short name	T22
Test name
Test status
Simulation time	121839194 ps
CPU time	0.89 seconds
Started	Apr 18 01:25:59 PM PDT 24
Finished	Apr 18 01:26:00 PM PDT 24
Peak memory	205152 kb
Host	smart-9e126295-89d0-431b-9dc8-0bb6bfef1c9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190130946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3190130946
Directory	/workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location	/workspace/coverage/default/1.rv_dm_sec_cm.3573968722
Short name	T33
Test name
Test status
Simulation time	780269487 ps
CPU time	1.2 seconds
Started	Apr 18 01:26:01 PM PDT 24
Finished	Apr 18 01:26:03 PM PDT 24
Peak memory	229336 kb
Host	smart-2c3e8f03-045f-43bf-a1d5-7eba88a0bcb2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573968722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3573968722
Directory	/workspace/1.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/1.rv_dm_smoke.501935520
Short name	T37
Test name
Test status
Simulation time	1650394984 ps
CPU time	1.6 seconds
Started	Apr 18 01:25:55 PM PDT 24
Finished	Apr 18 01:25:58 PM PDT 24
Peak memory	205120 kb
Host	smart-69096660-9fc8-4508-ae5f-32b0db93ba45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501935520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.501935520
Directory	/workspace/1.rv_dm_smoke/latest

Test location	/workspace/coverage/default/10.rv_dm_alert_test.1906922046
Short name	T3
Test name
Test status
Simulation time	19437689 ps
CPU time	0.72 seconds
Started	Apr 18 01:26:16 PM PDT 24
Finished	Apr 18 01:26:17 PM PDT 24
Peak memory	205028 kb
Host	smart-1d97291f-9b3e-4667-8cd4-50f9abf2ea58
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906922046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1906922046
Directory	/workspace/10.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3959394817
Short name	T88
Test name
Test status
Simulation time	3539104756 ps
CPU time	4.65 seconds
Started	Apr 18 01:26:21 PM PDT 24
Finished	Apr 18 01:26:26 PM PDT 24
Peak memory	215112 kb
Host	smart-a27aa857-aec3-40d3-8999-4c69b0052c94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959394817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3959394817
Directory	/workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspace/coverage/default/10.rv_dm_sba_tl_access.3022787950
Short name	T89
Test name
Test status
Simulation time	1273836744 ps
CPU time	3.24 seconds
Started	Apr 18 01:26:18 PM PDT 24
Finished	Apr 18 01:26:22 PM PDT 24
Peak memory	205416 kb
Host	smart-afd44e97-6ff2-4d62-b64e-6e545cd839d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022787950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3022787950
Directory	/workspace/10.rv_dm_sba_tl_access/latest

Test location	/workspace/coverage/default/11.rv_dm_alert_test.1524615055
Short name	T51
Test name
Test status
Simulation time	76249500 ps
CPU time	0.69 seconds
Started	Apr 18 01:26:23 PM PDT 24
Finished	Apr 18 01:26:25 PM PDT 24
Peak memory	205080 kb
Host	smart-d1e1d4b9-ed9d-4767-95d1-c9a5eb258c26
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524615055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1524615055
Directory	/workspace/11.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/12.rv_dm_alert_test.2695128616
Short name	T168
Test name
Test status
Simulation time	50590329 ps
CPU time	0.69 seconds
Started	Apr 18 01:26:24 PM PDT 24
Finished	Apr 18 01:26:25 PM PDT 24
Peak memory	205096 kb
Host	smart-e22ca95e-d2ef-443a-a980-bcef02d0ae39
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695128616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2695128616
Directory	/workspace/12.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/13.rv_dm_alert_test.1147029273
Short name	T38
Test name
Test status
Simulation time	30831862 ps
CPU time	0.67 seconds
Started	Apr 18 01:26:23 PM PDT 24
Finished	Apr 18 01:26:24 PM PDT 24
Peak memory	204988 kb
Host	smart-e24cf726-4ee2-4d67-89b3-2b9e34d6434d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147029273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1147029273
Directory	/workspace/13.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/14.rv_dm_alert_test.361240442
Short name	T124
Test name
Test status
Simulation time	20519399 ps
CPU time	0.72 seconds
Started	Apr 18 01:26:24 PM PDT 24
Finished	Apr 18 01:26:26 PM PDT 24
Peak memory	205100 kb
Host	smart-debef356-0e44-4b2c-aa20-98afa22630be
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361240442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.361240442
Directory	/workspace/14.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/14.rv_dm_sba_tl_access.50765463
Short name	T87
Test name
Test status
Simulation time	271952075 ps
CPU time	1.13 seconds
Started	Apr 18 01:26:23 PM PDT 24
Finished	Apr 18 01:26:25 PM PDT 24
Peak memory	205412 kb
Host	smart-5d51896a-b6e5-4957-bbf1-f0c86f2ee1a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50765463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.50765463
Directory	/workspace/14.rv_dm_sba_tl_access/latest

Test location	/workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.515821047
Short name	T86
Test name
Test status
Simulation time	2511143074 ps
CPU time	3.76 seconds
Started	Apr 18 01:26:21 PM PDT 24
Finished	Apr 18 01:26:25 PM PDT 24
Peak memory	205564 kb
Host	smart-4ce7d6d8-c048-4363-b0a6-1971de937154
User	root
Command	/workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=515821047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t l_access.515821047
Directory	/workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location	/workspace/coverage/default/16.rv_dm_alert_test.3368751304
Short name	T2
Test name
Test status
Simulation time	30133557 ps
CPU time	0.79 seconds
Started	Apr 18 01:26:22 PM PDT 24
Finished	Apr 18 01:26:24 PM PDT 24
Peak memory	205128 kb
Host	smart-967c59b0-cdf6-47d3-8c05-1a2c5612961f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368751304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3368751304
Directory	/workspace/16.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/17.rv_dm_alert_test.1861760852
Short name	T151
Test name
Test status
Simulation time	40986947 ps
CPU time	0.77 seconds
Started	Apr 18 01:26:27 PM PDT 24
Finished	Apr 18 01:26:28 PM PDT 24
Peak memory	205100 kb
Host	smart-ac6bc8cf-9478-449b-bb4b-f75507d7b577
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861760852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1861760852
Directory	/workspace/17.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/18.rv_dm_alert_test.2977906732
Short name	T147
Test name
Test status
Simulation time	84179701 ps
CPU time	0.68 seconds
Started	Apr 18 01:26:29 PM PDT 24
Finished	Apr 18 01:26:31 PM PDT 24
Peak memory	204960 kb
Host	smart-91f28bef-6385-4fc2-8c48-b4127de89565
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977906732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2977906732
Directory	/workspace/18.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.169013084
Short name	T28
Test name
Test status
Simulation time	10757102822 ps
CPU time	20.05 seconds
Started	Apr 18 01:26:27 PM PDT 24
Finished	Apr 18 01:26:48 PM PDT 24
Peak memory	213748 kb
Host	smart-8de02d8b-e1f6-4294-a4a7-f81dc32a8d74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169013084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.169013084
Directory	/workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location	/workspace/coverage/default/19.rv_dm_alert_test.506375196
Short name	T155
Test name
Test status
Simulation time	27858075 ps
CPU time	0.76 seconds
Started	Apr 18 01:26:27 PM PDT 24
Finished	Apr 18 01:26:29 PM PDT 24
Peak memory	205096 kb
Host	smart-107d8489-bf92-4d07-bbf0-c293c4016267
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506375196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.506375196
Directory	/workspace/19.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/2.rv_dm_alert_test.3701260926
Short name	T169
Test name
Test status
Simulation time	17498137 ps
CPU time	0.74 seconds
Started	Apr 18 01:25:58 PM PDT 24
Finished	Apr 18 01:26:00 PM PDT 24
Peak memory	205132 kb
Host	smart-af1f40ed-211c-4291-9708-80f9c3872ce2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701260926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3701260926
Directory	/workspace/2.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/2.rv_dm_hart_unavail.2018644057
Short name	T40
Test name
Test status
Simulation time	76064636 ps
CPU time	0.73 seconds
Started	Apr 18 01:25:59 PM PDT 24
Finished	Apr 18 01:26:00 PM PDT 24
Peak memory	204832 kb
Host	smart-08821dea-ca0a-469d-bafd-475165b9198e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018644057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2018644057
Directory	/workspace/2.rv_dm_hart_unavail/latest

Test location	/workspace/coverage/default/2.rv_dm_sec_cm.4190541097
Short name	T53
Test name
Test status
Simulation time	347502978 ps
CPU time	1.26 seconds
Started	Apr 18 01:26:03 PM PDT 24
Finished	Apr 18 01:26:04 PM PDT 24
Peak memory	229256 kb
Host	smart-1c999c4e-4fc9-4849-8855-e2b045b2be3e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190541097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4190541097
Directory	/workspace/2.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/20.rv_dm_alert_test.2300111287
Short name	T70
Test name
Test status
Simulation time	20265503 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:29 PM PDT 24
Finished	Apr 18 01:26:32 PM PDT 24
Peak memory	205116 kb
Host	smart-028675ab-fdb8-4150-9e80-9f3dc1f3d732
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300111287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2300111287
Directory	/workspace/20.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/21.rv_dm_alert_test.231741616
Short name	T159
Test name
Test status
Simulation time	25791969 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:33 PM PDT 24
Finished	Apr 18 01:26:35 PM PDT 24
Peak memory	205144 kb
Host	smart-d62628b1-8482-40d5-932e-d4304fff9028
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231741616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.231741616
Directory	/workspace/21.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/21.rv_dm_stress_all.2838344100
Short name	T75
Test name
Test status
Simulation time	2608898006 ps
CPU time	6.11 seconds
Started	Apr 18 01:26:39 PM PDT 24
Finished	Apr 18 01:26:46 PM PDT 24
Peak memory	205364 kb
Host	smart-55eb6978-3285-4cb5-a083-1443ffe64c92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838344100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2838344100
Directory	/workspace/21.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/22.rv_dm_alert_test.761072899
Short name	T141
Test name
Test status
Simulation time	43888341 ps
CPU time	0.76 seconds
Started	Apr 18 01:26:29 PM PDT 24
Finished	Apr 18 01:26:31 PM PDT 24
Peak memory	205080 kb
Host	smart-0ff98062-1e70-493a-a80c-ebfc8f9bfa69
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761072899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.761072899
Directory	/workspace/22.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/23.rv_dm_alert_test.2459695710
Short name	T56
Test name
Test status
Simulation time	40468312 ps
CPU time	0.75 seconds
Started	Apr 18 01:26:28 PM PDT 24
Finished	Apr 18 01:26:30 PM PDT 24
Peak memory	205108 kb
Host	smart-6ce7a84d-305a-4fde-837a-75615da7fbf6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459695710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2459695710
Directory	/workspace/23.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/24.rv_dm_alert_test.2463901272
Short name	T58
Test name
Test status
Simulation time	25622461 ps
CPU time	0.72 seconds
Started	Apr 18 01:26:29 PM PDT 24
Finished	Apr 18 01:26:30 PM PDT 24
Peak memory	205112 kb
Host	smart-ce6415fe-078c-44e8-a1f8-ac445423b3b2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463901272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2463901272
Directory	/workspace/24.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/25.rv_dm_alert_test.3588119166
Short name	T154
Test name
Test status
Simulation time	175347021 ps
CPU time	0.7 seconds
Started	Apr 18 01:26:30 PM PDT 24
Finished	Apr 18 01:26:32 PM PDT 24
Peak memory	205100 kb
Host	smart-82631e65-b1de-4704-a9a4-e4a58c7f8fa3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588119166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3588119166
Directory	/workspace/25.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/26.rv_dm_alert_test.2219576509
Short name	T144
Test name
Test status
Simulation time	36935459 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:27 PM PDT 24
Finished	Apr 18 01:26:29 PM PDT 24
Peak memory	205032 kb
Host	smart-f0f8e937-d1a9-4e60-a875-ea730f298f89
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219576509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2219576509
Directory	/workspace/26.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/27.rv_dm_alert_test.3771266439
Short name	T35
Test name
Test status
Simulation time	30864642 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:37 PM PDT 24
Finished	Apr 18 01:26:38 PM PDT 24
Peak memory	205088 kb
Host	smart-7023e36e-9b7f-4be0-ae99-a813b3fd2bb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771266439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3771266439
Directory	/workspace/27.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/28.rv_dm_alert_test.2358013737
Short name	T148
Test name
Test status
Simulation time	80313421 ps
CPU time	0.74 seconds
Started	Apr 18 01:26:32 PM PDT 24
Finished	Apr 18 01:26:34 PM PDT 24
Peak memory	205108 kb
Host	smart-710527e1-e8c0-48db-88cd-92972ea1e1e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358013737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2358013737
Directory	/workspace/28.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/29.rv_dm_alert_test.512347732
Short name	T150
Test name
Test status
Simulation time	20477259 ps
CPU time	0.75 seconds
Started	Apr 18 01:26:36 PM PDT 24
Finished	Apr 18 01:26:37 PM PDT 24
Peak memory	205092 kb
Host	smart-803c4a89-eaa9-495d-bd44-af03ab298542
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512347732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.512347732
Directory	/workspace/29.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/3.rv_dm_alert_test.690115403
Short name	T166
Test name
Test status
Simulation time	118291707 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:04 PM PDT 24
Finished	Apr 18 01:26:05 PM PDT 24
Peak memory	205124 kb
Host	smart-8ae56e72-b031-496d-b9aa-a5fbe3388e43
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690115403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.690115403
Directory	/workspace/3.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/3.rv_dm_hart_unavail.638867061
Short name	T170
Test name
Test status
Simulation time	65265098 ps
CPU time	0.86 seconds
Started	Apr 18 01:26:06 PM PDT 24
Finished	Apr 18 01:26:07 PM PDT 24
Peak memory	204972 kb
Host	smart-9d0a1d56-52f2-4bcb-876a-4bb50745ac32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638867061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.638867061
Directory	/workspace/3.rv_dm_hart_unavail/latest

Test location	/workspace/coverage/default/3.rv_dm_sec_cm.1496689401
Short name	T54
Test name
Test status
Simulation time	109827352 ps
CPU time	1.31 seconds
Started	Apr 18 01:26:05 PM PDT 24
Finished	Apr 18 01:26:07 PM PDT 24
Peak memory	229512 kb
Host	smart-b5f3af9e-2d57-4e53-8501-041c3059e3c8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496689401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1496689401
Directory	/workspace/3.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/30.rv_dm_alert_test.914933109
Short name	T119
Test name
Test status
Simulation time	47091806 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:33 PM PDT 24
Finished	Apr 18 01:26:34 PM PDT 24
Peak memory	205088 kb
Host	smart-1fe1bf0f-1065-40a3-a70a-f61c014dc3f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914933109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.914933109
Directory	/workspace/30.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/31.rv_dm_alert_test.3731722996
Short name	T153
Test name
Test status
Simulation time	34138438 ps
CPU time	0.74 seconds
Started	Apr 18 01:26:33 PM PDT 24
Finished	Apr 18 01:26:34 PM PDT 24
Peak memory	205076 kb
Host	smart-0d410bea-3d59-420e-889c-c23c8d4ab8fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731722996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3731722996
Directory	/workspace/31.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/32.rv_dm_alert_test.1379692895
Short name	T162
Test name
Test status
Simulation time	20541786 ps
CPU time	0.72 seconds
Started	Apr 18 01:26:35 PM PDT 24
Finished	Apr 18 01:26:36 PM PDT 24
Peak memory	205024 kb
Host	smart-55223b6c-84cf-46cd-a212-375301744b9e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379692895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1379692895
Directory	/workspace/32.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/33.rv_dm_alert_test.570033890
Short name	T55
Test name
Test status
Simulation time	17367595 ps
CPU time	0.7 seconds
Started	Apr 18 01:26:34 PM PDT 24
Finished	Apr 18 01:26:35 PM PDT 24
Peak memory	205108 kb
Host	smart-ba0ad977-ec9f-488f-aa2d-ccb396ef3371
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570033890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.570033890
Directory	/workspace/33.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/34.rv_dm_alert_test.1502278876
Short name	T158
Test name
Test status
Simulation time	28367819 ps
CPU time	0.75 seconds
Started	Apr 18 01:26:36 PM PDT 24
Finished	Apr 18 01:26:38 PM PDT 24
Peak memory	205096 kb
Host	smart-a612efeb-354d-48ac-8f02-6abe031176ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502278876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1502278876
Directory	/workspace/34.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/35.rv_dm_alert_test.2442387763
Short name	T146
Test name
Test status
Simulation time	35400300 ps
CPU time	0.76 seconds
Started	Apr 18 01:26:34 PM PDT 24
Finished	Apr 18 01:26:35 PM PDT 24
Peak memory	205048 kb
Host	smart-a4c4831d-fd82-4775-b09f-83eb1267c434
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442387763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2442387763
Directory	/workspace/35.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/36.rv_dm_alert_test.1214137224
Short name	T61
Test name
Test status
Simulation time	155072520 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:48 PM PDT 24
Finished	Apr 18 01:26:49 PM PDT 24
Peak memory	205028 kb
Host	smart-3e43615f-a01b-472e-8f31-fdda726d3ab3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214137224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1214137224
Directory	/workspace/36.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/38.rv_dm_alert_test.2467939639
Short name	T152
Test name
Test status
Simulation time	22051437 ps
CPU time	0.83 seconds
Started	Apr 18 01:26:35 PM PDT 24
Finished	Apr 18 01:26:36 PM PDT 24
Peak memory	205072 kb
Host	smart-86cfc357-241e-4377-bdf5-0799a707dd83
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467939639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2467939639
Directory	/workspace/38.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/39.rv_dm_alert_test.1459579590
Short name	T52
Test name
Test status
Simulation time	30611996 ps
CPU time	0.74 seconds
Started	Apr 18 01:26:34 PM PDT 24
Finished	Apr 18 01:26:35 PM PDT 24
Peak memory	205072 kb
Host	smart-17a82158-4018-4231-9e20-50db3b0b96d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459579590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1459579590
Directory	/workspace/39.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/4.rv_dm_alert_test.2337589216
Short name	T149
Test name
Test status
Simulation time	30471233 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:05 PM PDT 24
Finished	Apr 18 01:26:06 PM PDT 24
Peak memory	205092 kb
Host	smart-0bd023e9-22be-4222-8821-5c9c7a5c12bd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337589216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2337589216
Directory	/workspace/4.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/4.rv_dm_hart_unavail.3741903479
Short name	T24
Test name
Test status
Simulation time	79821776 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:22 PM PDT 24
Finished	Apr 18 01:26:23 PM PDT 24
Peak memory	204896 kb
Host	smart-aa6dbe5f-3252-4384-9790-45cb0ee34e77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3741903479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3741903479
Directory	/workspace/4.rv_dm_hart_unavail/latest

Test location	/workspace/coverage/default/40.rv_dm_alert_test.4089598195
Short name	T42
Test name
Test status
Simulation time	25518886 ps
CPU time	0.68 seconds
Started	Apr 18 01:26:43 PM PDT 24
Finished	Apr 18 01:26:45 PM PDT 24
Peak memory	205104 kb
Host	smart-236f19b7-d443-4791-9463-a63d2a9d6266
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089598195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4089598195
Directory	/workspace/40.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/41.rv_dm_alert_test.2374085829
Short name	T145
Test name
Test status
Simulation time	40601662 ps
CPU time	0.68 seconds
Started	Apr 18 01:26:41 PM PDT 24
Finished	Apr 18 01:26:43 PM PDT 24
Peak memory	205004 kb
Host	smart-b6ba3522-3df7-44a1-877c-04e7e273e572
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374085829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2374085829
Directory	/workspace/41.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/42.rv_dm_alert_test.3485824321
Short name	T143
Test name
Test status
Simulation time	71192838 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:45 PM PDT 24
Finished	Apr 18 01:26:46 PM PDT 24
Peak memory	205104 kb
Host	smart-4fd10b0a-2a57-4d0d-8c49-c57fc1b98594
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485824321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3485824321
Directory	/workspace/42.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/43.rv_dm_alert_test.3922487021
Short name	T66
Test name
Test status
Simulation time	27724049 ps
CPU time	0.7 seconds
Started	Apr 18 01:26:45 PM PDT 24
Finished	Apr 18 01:26:47 PM PDT 24
Peak memory	205104 kb
Host	smart-1cb29900-a334-4e86-b0a9-b1fcd9f987ff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922487021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3922487021
Directory	/workspace/43.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/44.rv_dm_alert_test.370165952
Short name	T123
Test name
Test status
Simulation time	76740767 ps
CPU time	0.7 seconds
Started	Apr 18 01:26:41 PM PDT 24
Finished	Apr 18 01:26:42 PM PDT 24
Peak memory	205080 kb
Host	smart-cda60f3a-744a-458b-9f02-17a2b1d263c9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370165952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.370165952
Directory	/workspace/44.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/45.rv_dm_alert_test.3761239353
Short name	T142
Test name
Test status
Simulation time	30995494 ps
CPU time	0.76 seconds
Started	Apr 18 01:26:44 PM PDT 24
Finished	Apr 18 01:26:45 PM PDT 24
Peak memory	205100 kb
Host	smart-3a060ec3-38ae-4753-b509-3fbef48a0545
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761239353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3761239353
Directory	/workspace/45.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/46.rv_dm_alert_test.2412112261
Short name	T44
Test name
Test status
Simulation time	90308395 ps
CPU time	0.71 seconds
Started	Apr 18 01:26:41 PM PDT 24
Finished	Apr 18 01:26:43 PM PDT 24
Peak memory	205024 kb
Host	smart-84b488a0-7661-4288-b8a1-36c41fc43133
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412112261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2412112261
Directory	/workspace/46.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/47.rv_dm_alert_test.41477600
Short name	T41
Test name
Test status
Simulation time	37443932 ps
CPU time	0.73 seconds
Started	Apr 18 01:26:40 PM PDT 24
Finished	Apr 18 01:26:41 PM PDT 24
Peak memory	205136 kb
Host	smart-f583bb65-a49b-40ee-a84e-314af78ece0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41477600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.41477600
Directory	/workspace/47.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/48.rv_dm_alert_test.455258796
Short name	T43
Test name
Test status
Simulation time	28283623 ps
CPU time	0.76 seconds
Started	Apr 18 01:26:40 PM PDT 24
Finished	Apr 18 01:26:42 PM PDT 24
Peak memory	205108 kb
Host	smart-ad4db0cf-21f2-4cb0-a1eb-50a21c96d1e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455258796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.455258796
Directory	/workspace/48.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/49.rv_dm_alert_test.3151588725
Short name	T157
Test name
Test status
Simulation time	40246861 ps
CPU time	0.75 seconds
Started	Apr 18 01:26:40 PM PDT 24
Finished	Apr 18 01:26:41 PM PDT 24
Peak memory	205104 kb
Host	smart-8e10b538-0832-438f-ad63-899f4f01ed19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151588725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3151588725
Directory	/workspace/49.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/6.rv_dm_alert_test.93314755
Short name	T161
Test name
Test status
Simulation time	27205420 ps
CPU time	0.7 seconds
Started	Apr 18 01:26:12 PM PDT 24
Finished	Apr 18 01:26:13 PM PDT 24
Peak memory	205068 kb
Host	smart-f3d103af-6eac-43fa-9e78-359e37252326
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93314755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.93314755
Directory	/workspace/6.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/6.rv_dm_sba_tl_access.3673408854
Short name	T90
Test name
Test status
Simulation time	4317885436 ps
CPU time	7.73 seconds
Started	Apr 18 01:26:12 PM PDT 24
Finished	Apr 18 01:26:20 PM PDT 24
Peak memory	205420 kb
Host	smart-71761a23-3be6-42ac-a27c-5fbbf4f9cc26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673408854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3673408854
Directory	/workspace/6.rv_dm_sba_tl_access/latest

Test location	/workspace/coverage/default/7.rv_dm_alert_test.1418839650
Short name	T122
Test name
Test status
Simulation time	31151915 ps
CPU time	0.72 seconds
Started	Apr 18 01:26:12 PM PDT 24
Finished	Apr 18 01:26:13 PM PDT 24
Peak memory	205040 kb
Host	smart-8de0b2ae-42ea-4551-94d2-c537b1a4b618
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418839650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1418839650
Directory	/workspace/7.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/8.rv_dm_alert_test.4020498522
Short name	T140
Test name
Test status
Simulation time	40461314 ps
CPU time	0.69 seconds
Started	Apr 18 01:26:20 PM PDT 24
Finished	Apr 18 01:26:21 PM PDT 24
Peak memory	205060 kb
Host	smart-9e3c764a-6fac-4702-9d30-a73e9de8ac2f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020498522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4020498522
Directory	/workspace/8.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/9.rv_dm_alert_test.3533901691
Short name	T160
Test name
Test status
Simulation time	28378321 ps
CPU time	0.67 seconds
Started	Apr 18 01:26:16 PM PDT 24
Finished	Apr 18 01:26:18 PM PDT 24
Peak memory	205116 kb
Host	smart-14365c81-d964-4ea9-9ce7-58896b97b25b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533901691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3533901691
Directory	/workspace/9.rv_dm_alert_test/latest