Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.11 93.64 80.05 87.69 71.79 82.01 98.52 47.05


Total tests in report: 314
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.87 51.87 82.16 82.16 49.20 49.20 34.96 34.96 42.31 42.31 61.06 61.06 91.45 91.45 1.93 1.93 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2757289768
59.09 7.23 85.82 3.66 54.79 5.59 56.40 21.44 52.56 10.26 67.66 6.60 93.35 1.90 3.07 1.14 /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1915469471
64.60 5.51 86.12 0.30 60.77 5.98 59.13 2.74 52.56 0.00 69.31 1.65 94.40 1.06 29.89 26.82 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1826767489
69.34 4.74 88.18 2.05 67.02 6.25 79.04 19.91 52.56 0.00 71.45 2.15 95.88 1.48 31.25 1.36 /workspace/coverage/default/37.rv_dm_alert_test.1988159129
73.04 3.70 91.98 3.81 75.27 8.24 81.13 2.09 57.69 5.13 77.39 5.94 95.99 0.11 31.82 0.57 /workspace/coverage/default/47.rv_dm_stress_all.778225076
75.49 2.45 92.23 0.25 75.66 0.40 81.21 0.08 65.38 7.69 78.05 0.66 95.99 0.00 39.89 8.07 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3786944170
77.09 1.60 92.89 0.65 76.99 1.33 82.70 1.49 71.79 6.41 79.37 1.32 95.99 0.00 39.89 0.00 /workspace/coverage/default/38.rv_dm_stress_all.4194819253
77.97 0.88 92.94 0.05 77.53 0.53 84.96 2.25 71.79 0.00 79.54 0.17 95.99 0.00 43.07 3.18 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2142746924
78.33 0.36 92.94 0.00 77.66 0.13 85.00 0.04 71.79 0.00 79.54 0.00 96.94 0.95 44.43 1.36 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1745670237
78.61 0.28 92.94 0.00 78.32 0.66 86.32 1.33 71.79 0.00 79.54 0.00 96.94 0.00 44.43 0.00 /workspace/coverage/default/13.rv_dm_sba_tl_access.3162019885
78.87 0.26 92.94 0.00 78.32 0.00 86.48 0.16 71.79 0.00 79.54 0.00 97.78 0.84 45.23 0.80 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.898850229
79.09 0.22 93.14 0.20 78.46 0.13 86.69 0.20 71.79 0.00 80.53 0.99 97.78 0.00 45.23 0.00 /workspace/coverage/default/1.rv_dm_rom_read_access.4204863531
79.29 0.20 93.14 0.00 78.99 0.53 87.21 0.52 71.79 0.00 80.53 0.00 97.89 0.11 45.45 0.23 /workspace/coverage/default/4.rv_dm_sec_cm.2683387466
79.39 0.10 93.19 0.05 79.26 0.27 87.45 0.24 71.79 0.00 80.69 0.17 97.89 0.00 45.45 0.00 /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2034760955
79.49 0.10 93.39 0.20 79.26 0.00 87.45 0.00 71.79 0.00 81.19 0.50 97.89 0.00 45.45 0.00 /workspace/coverage/default/0.rv_dm_cmderr_exception.2531247479
79.59 0.10 93.39 0.00 79.26 0.00 87.45 0.00 71.79 0.00 81.19 0.00 97.89 0.00 46.14 0.68 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3470457847
79.68 0.10 93.39 0.00 79.26 0.00 87.45 0.00 71.79 0.00 81.19 0.00 98.10 0.21 46.59 0.45 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4287587979
79.76 0.08 93.44 0.05 79.39 0.13 87.45 0.00 71.79 0.00 81.35 0.17 98.31 0.21 46.59 0.00 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3901079792
79.83 0.07 93.49 0.05 79.65 0.27 87.45 0.00 71.79 0.00 81.52 0.17 98.31 0.00 46.59 0.00 /workspace/coverage/default/0.rv_dm_progbuf_busy.805422065
79.89 0.06 93.59 0.10 79.65 0.00 87.45 0.00 71.79 0.00 81.85 0.33 98.31 0.00 46.59 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1330803564
79.95 0.06 93.59 0.00 79.65 0.00 87.45 0.00 71.79 0.00 82.01 0.17 98.31 0.00 46.82 0.23 /workspace/coverage/default/5.rv_dm_alert_test.2118104645
79.98 0.04 93.59 0.00 79.92 0.27 87.45 0.00 71.79 0.00 82.01 0.00 98.31 0.00 46.82 0.00 /workspace/coverage/default/25.rv_dm_stress_all.3334116806
80.02 0.03 93.59 0.00 79.92 0.00 87.45 0.00 71.79 0.00 82.01 0.00 98.31 0.00 47.05 0.23 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4162810347
80.05 0.03 93.59 0.00 79.92 0.00 87.45 0.00 71.79 0.00 82.01 0.00 98.52 0.21 47.05 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1366380628
80.08 0.03 93.64 0.05 79.92 0.00 87.61 0.16 71.79 0.00 82.01 0.00 98.52 0.00 47.05 0.00 /workspace/coverage/default/15.rv_dm_alert_test.1103969646
80.10 0.02 93.64 0.00 80.05 0.13 87.61 0.00 71.79 0.00 82.01 0.00 98.52 0.00 47.05 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2630783741
80.11 0.01 93.64 0.00 80.05 0.00 87.69 0.08 71.79 0.00 82.01 0.00 98.52 0.00 47.05 0.00 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1875939524

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2706481162
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2183985114
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3132201431
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.929496419
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3485322868
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.37371650
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4176389844
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.77509723
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2632995467
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3388758978
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4138128730
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2347115003
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.681568819
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2314474842
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1851286574
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3728466382
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3835548561
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1955555125
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.754806459
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3287755776
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1008084182
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3025576464
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2510027912
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1243993385
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.718477530
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2775989896
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2846204017
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.729613017
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1967003173
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2408091974
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2922213874
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3791104753
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2159955691
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4144418188
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1922398373
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2372209154
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3432809584
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3664886335
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2848432706
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1488780703
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.103056220
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.851929589
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.449842675
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1827586343
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2414262355
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1640384905
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1050389232
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4099434997
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1282552206
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1969825021
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.581661687
/workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1661733059
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1867919164
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2431921229
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3230956972
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.542474133
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.251637866
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3534428204
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.786627280
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1061584846
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3182586202
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2238594383
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.890677763
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4236631386
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2474200821
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3898243674
/workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2831021606
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1425907326
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1179203003
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3820267355
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2598280209
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4163560287
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2347564843
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4213686731
/workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.3632545613
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2105236135
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2672796769
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.991851216
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1178726544
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1981172851
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.204948335
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.903089961
/workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.992926094
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.613960738
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.43310584
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.735150747
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3120677553
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.538937307
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3286308216
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.404196323
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2691653302
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.683355762
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3146345393
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.206161583
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2976437494
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4223416246
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2063690835
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2768903184
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1970576200
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3983887345
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3946826174
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1073357686
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4109356317
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2565670843
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2903246126
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2975093607
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.45310492
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2156867497
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3354503621
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3981420115
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4229713732
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1336356187
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2971355490
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1073766989
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3898565077
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.786678479
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3168117624
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3869103414
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1044746963
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.916392423
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.419771287
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.559069682
/workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3941326427
/workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.4171981241
/workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2609599433
/workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.4004706567
/workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.1954813590
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2739569878
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1008226973
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1846308196
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1934901110
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1114613922
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2722646534
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.777596036
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.88755486
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2254453367
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.582738556
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2676762555
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2681086215
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3184892597
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.333604839
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1757373100
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2025915168
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.922423011
/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.170914469
/workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.3931621890
/workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1535558051
/workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.4239557426
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3816925917
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2593818584
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2104976710
/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1683420457
/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2949731468
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4093026468
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1300323692
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4159515750
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3353755981
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2708952830
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2444855429
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.544789702
/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2604748785
/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.108227833
/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3537670410
/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1817857587
/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3064940161
/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3375995027
/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.937730926
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.518615962
/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3204368743
/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1570061805
/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.671084051
/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1926805291
/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.103272568
/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2145396817
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1587192851
/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.63279064
/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1122358929
/workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.476108516
/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.494268944
/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3480356672
/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2888044446
/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1325009516
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3889123409
/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.86617604
/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.241621557
/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.35165846
/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1746506659
/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2163191213
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.639790434
/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3244880019
/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4145389524
/workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3201727088
/workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2710791360
/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2850860073
/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1551544315
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3069463702
/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3970224220
/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2566408496
/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.913444151
/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1595266452
/workspace/coverage/default/0.rv_dm_alert_test.7204044
/workspace/coverage/default/0.rv_dm_cmderr_busy.460954176
/workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1944741203
/workspace/coverage/default/0.rv_dm_hart_unavail.3443427898
/workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2660379102
/workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.509009684
/workspace/coverage/default/0.rv_dm_mem_tl_access_halted.435970574
/workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3224765658
/workspace/coverage/default/0.rv_dm_ndmreset_req.4246740161
/workspace/coverage/default/0.rv_dm_rom_read_access.3780687598
/workspace/coverage/default/0.rv_dm_sba_tl_access.1483088819
/workspace/coverage/default/0.rv_dm_sec_cm.1339459491
/workspace/coverage/default/0.rv_dm_smoke.3660727725
/workspace/coverage/default/0.rv_dm_tap_fsm.433117749
/workspace/coverage/default/1.rv_dm_alert_test.2862057380
/workspace/coverage/default/1.rv_dm_cmderr_busy.1420049141
/workspace/coverage/default/1.rv_dm_cmderr_exception.3727137320
/workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1883670851
/workspace/coverage/default/1.rv_dm_cmderr_not_supported.1639397892
/workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3495065954
/workspace/coverage/default/1.rv_dm_hart_unavail.1862086802
/workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2121380739
/workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3863199294
/workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2499272392
/workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1800945765
/workspace/coverage/default/1.rv_dm_ndmreset_req.119252199
/workspace/coverage/default/1.rv_dm_progbuf_busy.1275465365
/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3190130946
/workspace/coverage/default/1.rv_dm_sec_cm.3573968722
/workspace/coverage/default/1.rv_dm_smoke.501935520
/workspace/coverage/default/10.rv_dm_alert_test.1906922046
/workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3959394817
/workspace/coverage/default/10.rv_dm_sba_tl_access.3022787950
/workspace/coverage/default/11.rv_dm_alert_test.1524615055
/workspace/coverage/default/12.rv_dm_alert_test.2695128616
/workspace/coverage/default/13.rv_dm_alert_test.1147029273
/workspace/coverage/default/14.rv_dm_alert_test.361240442
/workspace/coverage/default/14.rv_dm_sba_tl_access.50765463
/workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.515821047
/workspace/coverage/default/16.rv_dm_alert_test.3368751304
/workspace/coverage/default/17.rv_dm_alert_test.1861760852
/workspace/coverage/default/18.rv_dm_alert_test.2977906732
/workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.169013084
/workspace/coverage/default/19.rv_dm_alert_test.506375196
/workspace/coverage/default/2.rv_dm_alert_test.3701260926
/workspace/coverage/default/2.rv_dm_hart_unavail.2018644057
/workspace/coverage/default/2.rv_dm_sec_cm.4190541097
/workspace/coverage/default/20.rv_dm_alert_test.2300111287
/workspace/coverage/default/21.rv_dm_alert_test.231741616
/workspace/coverage/default/21.rv_dm_stress_all.2838344100
/workspace/coverage/default/22.rv_dm_alert_test.761072899
/workspace/coverage/default/23.rv_dm_alert_test.2459695710
/workspace/coverage/default/24.rv_dm_alert_test.2463901272
/workspace/coverage/default/25.rv_dm_alert_test.3588119166
/workspace/coverage/default/26.rv_dm_alert_test.2219576509
/workspace/coverage/default/27.rv_dm_alert_test.3771266439
/workspace/coverage/default/28.rv_dm_alert_test.2358013737
/workspace/coverage/default/29.rv_dm_alert_test.512347732
/workspace/coverage/default/3.rv_dm_alert_test.690115403
/workspace/coverage/default/3.rv_dm_hart_unavail.638867061
/workspace/coverage/default/3.rv_dm_sec_cm.1496689401
/workspace/coverage/default/30.rv_dm_alert_test.914933109
/workspace/coverage/default/31.rv_dm_alert_test.3731722996
/workspace/coverage/default/32.rv_dm_alert_test.1379692895
/workspace/coverage/default/33.rv_dm_alert_test.570033890
/workspace/coverage/default/34.rv_dm_alert_test.1502278876
/workspace/coverage/default/35.rv_dm_alert_test.2442387763
/workspace/coverage/default/36.rv_dm_alert_test.1214137224
/workspace/coverage/default/38.rv_dm_alert_test.2467939639
/workspace/coverage/default/39.rv_dm_alert_test.1459579590
/workspace/coverage/default/4.rv_dm_alert_test.2337589216
/workspace/coverage/default/4.rv_dm_hart_unavail.3741903479
/workspace/coverage/default/40.rv_dm_alert_test.4089598195
/workspace/coverage/default/41.rv_dm_alert_test.2374085829
/workspace/coverage/default/42.rv_dm_alert_test.3485824321
/workspace/coverage/default/43.rv_dm_alert_test.3922487021
/workspace/coverage/default/44.rv_dm_alert_test.370165952
/workspace/coverage/default/45.rv_dm_alert_test.3761239353
/workspace/coverage/default/46.rv_dm_alert_test.2412112261
/workspace/coverage/default/47.rv_dm_alert_test.41477600
/workspace/coverage/default/48.rv_dm_alert_test.455258796
/workspace/coverage/default/49.rv_dm_alert_test.3151588725
/workspace/coverage/default/6.rv_dm_alert_test.93314755
/workspace/coverage/default/6.rv_dm_sba_tl_access.3673408854
/workspace/coverage/default/7.rv_dm_alert_test.1418839650
/workspace/coverage/default/8.rv_dm_alert_test.4020498522
/workspace/coverage/default/9.rv_dm_alert_test.3533901691



Total test records in report: 314
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2757289768 Apr 18 01:25:47 PM PDT 24 Apr 18 01:25:52 PM PDT 24 6075723635 ps
T2 /workspace/coverage/default/16.rv_dm_alert_test.3368751304 Apr 18 01:26:22 PM PDT 24 Apr 18 01:26:24 PM PDT 24 30133557 ps
T3 /workspace/coverage/default/10.rv_dm_alert_test.1906922046 Apr 18 01:26:16 PM PDT 24 Apr 18 01:26:17 PM PDT 24 19437689 ps
T24 /workspace/coverage/default/4.rv_dm_hart_unavail.3741903479 Apr 18 01:26:22 PM PDT 24 Apr 18 01:26:23 PM PDT 24 79821776 ps
T6 /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1883670851 Apr 18 01:25:52 PM PDT 24 Apr 18 01:25:53 PM PDT 24 242889903 ps
T35 /workspace/coverage/default/27.rv_dm_alert_test.3771266439 Apr 18 01:26:37 PM PDT 24 Apr 18 01:26:38 PM PDT 24 30864642 ps
T4 /workspace/coverage/default/1.rv_dm_progbuf_busy.1275465365 Apr 18 01:25:52 PM PDT 24 Apr 18 01:25:53 PM PDT 24 84634051 ps
T38 /workspace/coverage/default/13.rv_dm_alert_test.1147029273 Apr 18 01:26:23 PM PDT 24 Apr 18 01:26:24 PM PDT 24 30831862 ps
T51 /workspace/coverage/default/11.rv_dm_alert_test.1524615055 Apr 18 01:26:23 PM PDT 24 Apr 18 01:26:25 PM PDT 24 76249500 ps
T13 /workspace/coverage/default/1.rv_dm_rom_read_access.4204863531 Apr 18 01:26:02 PM PDT 24 Apr 18 01:26:03 PM PDT 24 23639990 ps
T66 /workspace/coverage/default/43.rv_dm_alert_test.3922487021 Apr 18 01:26:45 PM PDT 24 Apr 18 01:26:47 PM PDT 24 27724049 ps
T5 /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.435970574 Apr 18 01:25:47 PM PDT 24 Apr 18 01:25:48 PM PDT 24 232449041 ps
T22 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3190130946 Apr 18 01:25:59 PM PDT 24 Apr 18 01:26:00 PM PDT 24 121839194 ps
T26 /workspace/coverage/default/13.rv_dm_sba_tl_access.3162019885 Apr 18 01:26:21 PM PDT 24 Apr 18 01:26:26 PM PDT 24 1519058290 ps
T39 /workspace/coverage/default/37.rv_dm_alert_test.1988159129 Apr 18 01:26:34 PM PDT 24 Apr 18 01:26:35 PM PDT 24 34201428 ps
T15 /workspace/coverage/default/0.rv_dm_ndmreset_req.4246740161 Apr 18 01:25:50 PM PDT 24 Apr 18 01:25:57 PM PDT 24 2031901974 ps
T10 /workspace/coverage/default/0.rv_dm_cmderr_busy.460954176 Apr 18 01:25:43 PM PDT 24 Apr 18 01:25:50 PM PDT 24 2528719207 ps
T70 /workspace/coverage/default/20.rv_dm_alert_test.2300111287 Apr 18 01:26:29 PM PDT 24 Apr 18 01:26:32 PM PDT 24 20265503 ps
T8 /workspace/coverage/default/47.rv_dm_stress_all.778225076 Apr 18 01:26:43 PM PDT 24 Apr 18 01:27:03 PM PDT 24 10974782859 ps
T44 /workspace/coverage/default/46.rv_dm_alert_test.2412112261 Apr 18 01:26:41 PM PDT 24 Apr 18 01:26:43 PM PDT 24 90308395 ps
T40 /workspace/coverage/default/2.rv_dm_hart_unavail.2018644057 Apr 18 01:25:59 PM PDT 24 Apr 18 01:26:00 PM PDT 24 76064636 ps
T27 /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1915469471 Apr 18 01:26:11 PM PDT 24 Apr 18 01:26:33 PM PDT 24 9440955768 ps
T41 /workspace/coverage/default/47.rv_dm_alert_test.41477600 Apr 18 01:26:40 PM PDT 24 Apr 18 01:26:41 PM PDT 24 37443932 ps
T16 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3495065954 Apr 18 01:25:51 PM PDT 24 Apr 18 01:25:52 PM PDT 24 34219369 ps
T30 /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.509009684 Apr 18 01:25:48 PM PDT 24 Apr 18 01:25:49 PM PDT 24 575245092 ps
T50 /workspace/coverage/default/15.rv_dm_alert_test.1103969646 Apr 18 01:26:29 PM PDT 24 Apr 18 01:26:31 PM PDT 24 48447762 ps
T119 /workspace/coverage/default/30.rv_dm_alert_test.914933109 Apr 18 01:26:33 PM PDT 24 Apr 18 01:26:34 PM PDT 24 47091806 ps
T122 /workspace/coverage/default/7.rv_dm_alert_test.1418839650 Apr 18 01:26:12 PM PDT 24 Apr 18 01:26:13 PM PDT 24 31151915 ps
T120 /workspace/coverage/default/1.rv_dm_alert_test.2862057380 Apr 18 01:26:00 PM PDT 24 Apr 18 01:26:01 PM PDT 24 28415039 ps
T9 /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1639397892 Apr 18 01:25:53 PM PDT 24 Apr 18 01:25:56 PM PDT 24 3161675962 ps
T42 /workspace/coverage/default/40.rv_dm_alert_test.4089598195 Apr 18 01:26:43 PM PDT 24 Apr 18 01:26:45 PM PDT 24 25518886 ps
T20 /workspace/coverage/default/0.rv_dm_tap_fsm.433117749 Apr 18 01:25:44 PM PDT 24 Apr 18 01:25:48 PM PDT 24 2356158167 ps
T28 /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.169013084 Apr 18 01:26:27 PM PDT 24 Apr 18 01:26:48 PM PDT 24 10757102822 ps
T52 /workspace/coverage/default/39.rv_dm_alert_test.1459579590 Apr 18 01:26:34 PM PDT 24 Apr 18 01:26:35 PM PDT 24 30611996 ps
T149 /workspace/coverage/default/4.rv_dm_alert_test.2337589216 Apr 18 01:26:05 PM PDT 24 Apr 18 01:26:06 PM PDT 24 30471233 ps
T23 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1330803564 Apr 18 01:25:47 PM PDT 24 Apr 18 01:25:49 PM PDT 24 80085283 ps
T43 /workspace/coverage/default/48.rv_dm_alert_test.455258796 Apr 18 01:26:40 PM PDT 24 Apr 18 01:26:42 PM PDT 24 28283623 ps
T124 /workspace/coverage/default/14.rv_dm_alert_test.361240442 Apr 18 01:26:24 PM PDT 24 Apr 18 01:26:26 PM PDT 24 20519399 ps
T86 /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.515821047 Apr 18 01:26:21 PM PDT 24 Apr 18 01:26:25 PM PDT 24 2511143074 ps
T123 /workspace/coverage/default/44.rv_dm_alert_test.370165952 Apr 18 01:26:41 PM PDT 24 Apr 18 01:26:42 PM PDT 24 76740767 ps
T158 /workspace/coverage/default/34.rv_dm_alert_test.1502278876 Apr 18 01:26:36 PM PDT 24 Apr 18 01:26:38 PM PDT 24 28367819 ps
T32 /workspace/coverage/default/4.rv_dm_sec_cm.2683387466 Apr 18 01:26:06 PM PDT 24 Apr 18 01:26:08 PM PDT 24 464856796 ps
T55 /workspace/coverage/default/33.rv_dm_alert_test.570033890 Apr 18 01:26:34 PM PDT 24 Apr 18 01:26:35 PM PDT 24 17367595 ps
T7 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2630783741 Apr 18 01:25:46 PM PDT 24 Apr 18 01:25:47 PM PDT 24 49512468 ps
T31 /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3863199294 Apr 18 01:25:53 PM PDT 24 Apr 18 01:25:54 PM PDT 24 199962207 ps
T18 /workspace/coverage/default/1.rv_dm_cmderr_exception.3727137320 Apr 18 01:25:54 PM PDT 24 Apr 18 01:25:56 PM PDT 24 661317864 ps
T56 /workspace/coverage/default/23.rv_dm_alert_test.2459695710 Apr 18 01:26:28 PM PDT 24 Apr 18 01:26:30 PM PDT 24 40468312 ps
T57 /workspace/coverage/default/0.rv_dm_hart_unavail.3443427898 Apr 18 01:25:46 PM PDT 24 Apr 18 01:25:48 PM PDT 24 59568494 ps
T37 /workspace/coverage/default/1.rv_dm_smoke.501935520 Apr 18 01:25:55 PM PDT 24 Apr 18 01:25:58 PM PDT 24 1650394984 ps
T33 /workspace/coverage/default/1.rv_dm_sec_cm.3573968722 Apr 18 01:26:01 PM PDT 24 Apr 18 01:26:03 PM PDT 24 780269487 ps
T58 /workspace/coverage/default/24.rv_dm_alert_test.2463901272 Apr 18 01:26:29 PM PDT 24 Apr 18 01:26:30 PM PDT 24 25622461 ps
T146 /workspace/coverage/default/35.rv_dm_alert_test.2442387763 Apr 18 01:26:34 PM PDT 24 Apr 18 01:26:35 PM PDT 24 35400300 ps
T11 /workspace/coverage/default/38.rv_dm_stress_all.4194819253 Apr 18 01:26:37 PM PDT 24 Apr 18 01:26:42 PM PDT 24 2428857539 ps
T156 /workspace/coverage/default/0.rv_dm_alert_test.7204044 Apr 18 01:25:57 PM PDT 24 Apr 18 01:25:58 PM PDT 24 19767627 ps
T21 /workspace/coverage/default/1.rv_dm_ndmreset_req.119252199 Apr 18 01:25:53 PM PDT 24 Apr 18 01:25:56 PM PDT 24 767293775 ps
T163 /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2660379102 Apr 18 01:25:48 PM PDT 24 Apr 18 01:25:50 PM PDT 24 480084432 ps
T164 /workspace/coverage/default/1.rv_dm_hart_unavail.1862086802 Apr 18 01:25:58 PM PDT 24 Apr 18 01:25:59 PM PDT 24 46487128 ps
T143 /workspace/coverage/default/42.rv_dm_alert_test.3485824321 Apr 18 01:26:45 PM PDT 24 Apr 18 01:26:46 PM PDT 24 71192838 ps
T139 /workspace/coverage/default/5.rv_dm_alert_test.2118104645 Apr 18 01:26:13 PM PDT 24 Apr 18 01:26:15 PM PDT 24 72946090 ps
T29 /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2034760955 Apr 18 01:26:18 PM PDT 24 Apr 18 01:26:54 PM PDT 24 16546191016 ps
T153 /workspace/coverage/default/31.rv_dm_alert_test.3731722996 Apr 18 01:26:33 PM PDT 24 Apr 18 01:26:34 PM PDT 24 34138438 ps
T155 /workspace/coverage/default/19.rv_dm_alert_test.506375196 Apr 18 01:26:27 PM PDT 24 Apr 18 01:26:29 PM PDT 24 27858075 ps
T36 /workspace/coverage/default/25.rv_dm_stress_all.3334116806 Apr 18 01:26:39 PM PDT 24 Apr 18 01:26:44 PM PDT 24 2045697369 ps
T87 /workspace/coverage/default/14.rv_dm_sba_tl_access.50765463 Apr 18 01:26:23 PM PDT 24 Apr 18 01:26:25 PM PDT 24 271952075 ps
T88 /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3959394817 Apr 18 01:26:21 PM PDT 24 Apr 18 01:26:26 PM PDT 24 3539104756 ps
T165 /workspace/coverage/default/0.rv_dm_smoke.3660727725 Apr 18 01:25:44 PM PDT 24 Apr 18 01:25:46 PM PDT 24 737195174 ps
T17 /workspace/coverage/default/0.rv_dm_progbuf_busy.805422065 Apr 18 01:25:47 PM PDT 24 Apr 18 01:25:49 PM PDT 24 556682578 ps
T142 /workspace/coverage/default/45.rv_dm_alert_test.3761239353 Apr 18 01:26:44 PM PDT 24 Apr 18 01:26:45 PM PDT 24 30995494 ps
T34 /workspace/coverage/default/0.rv_dm_sec_cm.1339459491 Apr 18 01:25:52 PM PDT 24 Apr 18 01:25:54 PM PDT 24 1266965067 ps
T25 /workspace/coverage/default/1.rv_dm_cmderr_busy.1420049141 Apr 18 01:25:55 PM PDT 24 Apr 18 01:26:01 PM PDT 24 5316639900 ps
T75 /workspace/coverage/default/21.rv_dm_stress_all.2838344100 Apr 18 01:26:39 PM PDT 24 Apr 18 01:26:46 PM PDT 24 2608898006 ps
T147 /workspace/coverage/default/18.rv_dm_alert_test.2977906732 Apr 18 01:26:29 PM PDT 24 Apr 18 01:26:31 PM PDT 24 84179701 ps
T53 /workspace/coverage/default/2.rv_dm_sec_cm.4190541097 Apr 18 01:26:03 PM PDT 24 Apr 18 01:26:04 PM PDT 24 347502978 ps
T144 /workspace/coverage/default/26.rv_dm_alert_test.2219576509 Apr 18 01:26:27 PM PDT 24 Apr 18 01:26:29 PM PDT 24 36935459 ps
T54 /workspace/coverage/default/3.rv_dm_sec_cm.1496689401 Apr 18 01:26:05 PM PDT 24 Apr 18 01:26:07 PM PDT 24 109827352 ps
T141 /workspace/coverage/default/22.rv_dm_alert_test.761072899 Apr 18 01:26:29 PM PDT 24 Apr 18 01:26:31 PM PDT 24 43888341 ps
T89 /workspace/coverage/default/10.rv_dm_sba_tl_access.3022787950 Apr 18 01:26:18 PM PDT 24 Apr 18 01:26:22 PM PDT 24 1273836744 ps
T166 /workspace/coverage/default/3.rv_dm_alert_test.690115403 Apr 18 01:26:04 PM PDT 24 Apr 18 01:26:05 PM PDT 24 118291707 ps
T159 /workspace/coverage/default/21.rv_dm_alert_test.231741616 Apr 18 01:26:33 PM PDT 24 Apr 18 01:26:35 PM PDT 24 25791969 ps
T90 /workspace/coverage/default/6.rv_dm_sba_tl_access.3673408854 Apr 18 01:26:12 PM PDT 24 Apr 18 01:26:20 PM PDT 24 4317885436 ps
T151 /workspace/coverage/default/17.rv_dm_alert_test.1861760852 Apr 18 01:26:27 PM PDT 24 Apr 18 01:26:28 PM PDT 24 40986947 ps
T161 /workspace/coverage/default/6.rv_dm_alert_test.93314755 Apr 18 01:26:12 PM PDT 24 Apr 18 01:26:13 PM PDT 24 27205420 ps
T154 /workspace/coverage/default/25.rv_dm_alert_test.3588119166 Apr 18 01:26:30 PM PDT 24 Apr 18 01:26:32 PM PDT 24 175347021 ps
T167 /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2499272392 Apr 18 01:25:53 PM PDT 24 Apr 18 01:25:55 PM PDT 24 138115904 ps
T14 /workspace/coverage/default/0.rv_dm_rom_read_access.3780687598 Apr 18 01:25:47 PM PDT 24 Apr 18 01:25:48 PM PDT 24 27976338 ps
T145 /workspace/coverage/default/41.rv_dm_alert_test.2374085829 Apr 18 01:26:41 PM PDT 24 Apr 18 01:26:43 PM PDT 24 40601662 ps
T168 /workspace/coverage/default/12.rv_dm_alert_test.2695128616 Apr 18 01:26:24 PM PDT 24 Apr 18 01:26:25 PM PDT 24 50590329 ps
T169 /workspace/coverage/default/2.rv_dm_alert_test.3701260926 Apr 18 01:25:58 PM PDT 24 Apr 18 01:26:00 PM PDT 24 17498137 ps
T170 /workspace/coverage/default/3.rv_dm_hart_unavail.638867061 Apr 18 01:26:06 PM PDT 24 Apr 18 01:26:07 PM PDT 24 65265098 ps
T12 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1800945765 Apr 18 01:25:53 PM PDT 24 Apr 18 01:25:55 PM PDT 24 172495699 ps
T162 /workspace/coverage/default/32.rv_dm_alert_test.1379692895 Apr 18 01:26:35 PM PDT 24 Apr 18 01:26:36 PM PDT 24 20541786 ps
T148 /workspace/coverage/default/28.rv_dm_alert_test.2358013737 Apr 18 01:26:32 PM PDT 24 Apr 18 01:26:34 PM PDT 24 80313421 ps
T152 /workspace/coverage/default/38.rv_dm_alert_test.2467939639 Apr 18 01:26:35 PM PDT 24 Apr 18 01:26:36 PM PDT 24 22051437 ps
T61 /workspace/coverage/default/36.rv_dm_alert_test.1214137224 Apr 18 01:26:48 PM PDT 24 Apr 18 01:26:49 PM PDT 24 155072520 ps
T91 /workspace/coverage/default/0.rv_dm_sba_tl_access.1483088819 Apr 18 01:25:49 PM PDT 24 Apr 18 01:25:53 PM PDT 24 1412177759 ps
T140 /workspace/coverage/default/8.rv_dm_alert_test.4020498522 Apr 18 01:26:20 PM PDT 24 Apr 18 01:26:21 PM PDT 24 40461314 ps
T171 /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3224765658 Apr 18 01:25:46 PM PDT 24 Apr 18 01:25:47 PM PDT 24 116893188 ps
T150 /workspace/coverage/default/29.rv_dm_alert_test.512347732 Apr 18 01:26:36 PM PDT 24 Apr 18 01:26:37 PM PDT 24 20477259 ps
T157 /workspace/coverage/default/49.rv_dm_alert_test.3151588725 Apr 18 01:26:40 PM PDT 24 Apr 18 01:26:41 PM PDT 24 40246861 ps
T160 /workspace/coverage/default/9.rv_dm_alert_test.3533901691 Apr 18 01:26:16 PM PDT 24 Apr 18 01:26:18 PM PDT 24 28378321 ps
T172 /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2121380739 Apr 18 01:25:57 PM PDT 24 Apr 18 01:25:58 PM PDT 24 100269963 ps
T19 /workspace/coverage/default/0.rv_dm_cmderr_exception.2531247479 Apr 18 01:25:43 PM PDT 24 Apr 18 01:25:45 PM PDT 24 405694277 ps
T138 /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1944741203 Apr 18 01:25:45 PM PDT 24 Apr 18 01:25:47 PM PDT 24 83557769 ps
T48 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1846308196 Apr 18 01:23:23 PM PDT 24 Apr 18 01:23:26 PM PDT 24 470619502 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4176389844 Apr 18 01:23:10 PM PDT 24 Apr 18 01:23:12 PM PDT 24 345202718 ps
T45 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3182586202 Apr 18 01:23:53 PM PDT 24 Apr 18 01:24:02 PM PDT 24 373729910 ps
T49 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3432809584 Apr 18 01:23:45 PM PDT 24 Apr 18 01:23:53 PM PDT 24 990047377 ps
T46 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2975093607 Apr 18 01:23:42 PM PDT 24 Apr 18 01:23:50 PM PDT 24 203620856 ps
T76 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1745670237 Apr 18 01:23:34 PM PDT 24 Apr 18 01:23:37 PM PDT 24 51487161 ps
T47 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2672796769 Apr 18 01:23:58 PM PDT 24 Apr 18 01:24:07 PM PDT 24 670553779 ps
T77 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3354503621 Apr 18 01:23:18 PM PDT 24 Apr 18 01:23:20 PM PDT 24 65006953 ps
T173 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.108227833 Apr 18 01:23:25 PM PDT 24 Apr 18 01:23:26 PM PDT 24 35201389 ps
T67 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2888044446 Apr 18 01:23:40 PM PDT 24 Apr 18 01:23:44 PM PDT 24 3347709647 ps
T68 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1826767489 Apr 18 01:23:28 PM PDT 24 Apr 18 01:23:34 PM PDT 24 4980201488 ps
T63 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1967003173 Apr 18 01:23:15 PM PDT 24 Apr 18 01:23:17 PM PDT 24 113935107 ps
T69 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.613960738 Apr 18 01:23:44 PM PDT 24 Apr 18 01:23:47 PM PDT 24 293471024 ps
T59 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4287587979 Apr 18 01:23:15 PM PDT 24 Apr 18 01:23:33 PM PDT 24 9399343733 ps
T174 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2314474842 Apr 18 01:23:11 PM PDT 24 Apr 18 01:23:12 PM PDT 24 27808726 ps
T175 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2254453367 Apr 18 01:23:26 PM PDT 24 Apr 18 01:23:28 PM PDT 24 637380323 ps
T64 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2846204017 Apr 18 01:23:19 PM PDT 24 Apr 18 01:23:21 PM PDT 24 728494719 ps
T78 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1008226973 Apr 18 01:23:28 PM PDT 24 Apr 18 01:24:05 PM PDT 24 5097108080 ps
T65 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4109356317 Apr 18 01:23:44 PM PDT 24 Apr 18 01:23:45 PM PDT 24 53028675 ps
T176 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2408091974 Apr 18 01:23:13 PM PDT 24 Apr 18 01:23:15 PM PDT 24 16288431 ps
T177 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1336356187 Apr 18 01:23:18 PM PDT 24 Apr 18 01:24:03 PM PDT 24 23210493078 ps
T178 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2681086215 Apr 18 01:23:25 PM PDT 24 Apr 18 01:23:26 PM PDT 24 43493511 ps
T79 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2145396817 Apr 18 01:23:33 PM PDT 24 Apr 18 01:23:35 PM PDT 24 50637973 ps
T60 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3201727088 Apr 18 01:23:35 PM PDT 24 Apr 18 01:23:54 PM PDT 24 10418641929 ps
T71 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1050389232 Apr 18 01:23:40 PM PDT 24 Apr 18 01:23:44 PM PDT 24 2316639267 ps
T179 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2722646534 Apr 18 01:23:27 PM PDT 24 Apr 18 01:23:43 PM PDT 24 6788270290 ps
T72 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3786944170 Apr 18 01:23:46 PM PDT 24 Apr 18 01:24:01 PM PDT 24 12240594165 ps
T73 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3941326427 Apr 18 01:23:51 PM PDT 24 Apr 18 01:24:06 PM PDT 24 7830375912 ps
T93 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3901079792 Apr 18 01:23:24 PM PDT 24 Apr 18 01:23:25 PM PDT 24 138005432 ps
T180 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.204948335 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:40 PM PDT 24 146309759 ps
T80 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1178726544 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:41 PM PDT 24 33643158 ps
T181 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.729613017 Apr 18 01:23:10 PM PDT 24 Apr 18 01:23:11 PM PDT 24 111909960 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2971355490 Apr 18 01:23:25 PM PDT 24 Apr 18 01:23:27 PM PDT 24 497070334 ps
T74 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2710791360 Apr 18 01:23:47 PM PDT 24 Apr 18 01:23:49 PM PDT 24 291058087 ps
T81 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3981420115 Apr 18 01:23:28 PM PDT 24 Apr 18 01:23:30 PM PDT 24 141029503 ps
T84 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1683420457 Apr 18 01:23:32 PM PDT 24 Apr 18 01:23:35 PM PDT 24 73475774 ps
T85 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.922423011 Apr 18 01:23:43 PM PDT 24 Apr 18 01:23:49 PM PDT 24 106124890 ps
T121 /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.3931621890 Apr 18 01:23:40 PM PDT 24 Apr 18 01:23:55 PM PDT 24 13056451198 ps
T82 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1325009516 Apr 18 01:23:35 PM PDT 24 Apr 18 01:23:37 PM PDT 24 141872851 ps
T127 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2142746924 Apr 18 01:23:24 PM PDT 24 Apr 18 01:23:45 PM PDT 24 1568031213 ps
T182 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4163560287 Apr 18 01:23:49 PM PDT 24 Apr 18 01:23:51 PM PDT 24 464853221 ps
T183 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.735150747 Apr 18 01:23:45 PM PDT 24 Apr 18 01:23:48 PM PDT 24 394928138 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1243993385 Apr 18 01:23:14 PM PDT 24 Apr 18 01:23:16 PM PDT 24 1826302581 ps
T184 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2444855429 Apr 18 01:23:23 PM PDT 24 Apr 18 01:23:29 PM PDT 24 1764305950 ps
T185 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3983887345 Apr 18 01:23:44 PM PDT 24 Apr 18 01:23:46 PM PDT 24 131227296 ps
T83 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2739569878 Apr 18 01:23:24 PM PDT 24 Apr 18 01:24:32 PM PDT 24 2222270225 ps
T98 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1551544315 Apr 18 01:23:49 PM PDT 24 Apr 18 01:23:51 PM PDT 24 173306223 ps
T186 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.718477530 Apr 18 01:23:10 PM PDT 24 Apr 18 01:23:13 PM PDT 24 280051246 ps
T118 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.45310492 Apr 18 01:23:25 PM PDT 24 Apr 18 01:23:54 PM PDT 24 2242334540 ps
T187 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2976437494 Apr 18 01:23:51 PM PDT 24 Apr 18 01:23:55 PM PDT 24 574099064 ps
T188 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3025576464 Apr 18 01:23:15 PM PDT 24 Apr 18 01:23:31 PM PDT 24 11887890114 ps
T128 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1746506659 Apr 18 01:23:43 PM PDT 24 Apr 18 01:23:53 PM PDT 24 2633427566 ps
T113 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.404196323 Apr 18 01:23:44 PM PDT 24 Apr 18 01:23:48 PM PDT 24 277074076 ps
T189 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3889123409 Apr 18 01:23:32 PM PDT 24 Apr 18 01:23:37 PM PDT 24 2320614580 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.898850229 Apr 18 01:23:09 PM PDT 24 Apr 18 01:24:15 PM PDT 24 3054971728 ps
T190 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1851286574 Apr 18 01:23:10 PM PDT 24 Apr 18 01:23:15 PM PDT 24 626962487 ps
T191 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4229713732 Apr 18 01:23:17 PM PDT 24 Apr 18 01:23:50 PM PDT 24 8181731609 ps
T100 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.786627280 Apr 18 01:23:49 PM PDT 24 Apr 18 01:23:57 PM PDT 24 1037821147 ps
T192 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2604748785 Apr 18 01:23:28 PM PDT 24 Apr 18 01:23:29 PM PDT 24 92340123 ps
T193 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1981172851 Apr 18 01:23:52 PM PDT 24 Apr 18 01:23:57 PM PDT 24 2275689135 ps
T108 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3120677553 Apr 18 01:23:45 PM PDT 24 Apr 18 01:23:47 PM PDT 24 197288308 ps
T194 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2632995467 Apr 18 01:23:14 PM PDT 24 Apr 18 01:23:15 PM PDT 24 108687733 ps
T195 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1282552206 Apr 18 01:23:55 PM PDT 24 Apr 18 01:23:57 PM PDT 24 263296856 ps
T114 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.581661687 Apr 18 01:23:55 PM PDT 24 Apr 18 01:24:02 PM PDT 24 591736271 ps
T196 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3184892597 Apr 18 01:23:21 PM PDT 24 Apr 18 01:23:22 PM PDT 24 78894750 ps
T197 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2676762555 Apr 18 01:23:26 PM PDT 24 Apr 18 01:23:41 PM PDT 24 6097255003 ps
T110 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2156867497 Apr 18 01:23:23 PM PDT 24 Apr 18 01:24:36 PM PDT 24 7614987970 ps
T198 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.86617604 Apr 18 01:23:40 PM PDT 24 Apr 18 01:23:41 PM PDT 24 92076872 ps
T132 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1595266452 Apr 18 01:23:47 PM PDT 24 Apr 18 01:23:58 PM PDT 24 4645195703 ps
T199 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3485322868 Apr 18 01:23:11 PM PDT 24 Apr 18 01:24:25 PM PDT 24 33455536517 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1366380628 Apr 18 01:23:15 PM PDT 24 Apr 18 01:23:20 PM PDT 24 216114255 ps
T200 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1640384905 Apr 18 01:23:56 PM PDT 24 Apr 18 01:24:07 PM PDT 24 863592492 ps
T201 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1867919164 Apr 18 01:23:49 PM PDT 24 Apr 18 01:23:55 PM PDT 24 773640888 ps
T115 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3898243674 Apr 18 01:23:37 PM PDT 24 Apr 18 01:23:42 PM PDT 24 689218612 ps
T202 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.449842675 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:41 PM PDT 24 130921445 ps
T203 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.37371650 Apr 18 01:23:15 PM PDT 24 Apr 18 01:23:45 PM PDT 24 14786160133 ps
T116 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2063690835 Apr 18 01:23:53 PM PDT 24 Apr 18 01:23:59 PM PDT 24 517449190 ps
T117 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1570061805 Apr 18 01:23:34 PM PDT 24 Apr 18 01:23:38 PM PDT 24 561332538 ps
T204 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3820267355 Apr 18 01:23:45 PM PDT 24 Apr 18 01:23:48 PM PDT 24 163732581 ps
T205 /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.1954813590 Apr 18 01:23:54 PM PDT 24 Apr 18 01:24:06 PM PDT 24 4817497630 ps
T206 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3168117624 Apr 18 01:23:17 PM PDT 24 Apr 18 01:23:18 PM PDT 24 24549621 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.916392423 Apr 18 01:23:20 PM PDT 24 Apr 18 01:23:27 PM PDT 24 176537924 ps
T207 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1061584846 Apr 18 01:23:38 PM PDT 24 Apr 18 01:23:42 PM PDT 24 184887833 ps
T208 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1044746963 Apr 18 01:23:18 PM PDT 24 Apr 18 01:23:19 PM PDT 24 149036320 ps
T209 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.681568819 Apr 18 01:23:12 PM PDT 24 Apr 18 01:23:13 PM PDT 24 42893234 ps
T125 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.4171981241 Apr 18 01:23:58 PM PDT 24 Apr 18 01:24:15 PM PDT 24 13262117158 ps
T210 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2609599433 Apr 18 01:23:55 PM PDT 24 Apr 18 01:24:22 PM PDT 24 25049167899 ps
T211 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3869103414 Apr 18 01:23:18 PM PDT 24 Apr 18 01:23:19 PM PDT 24 21239975 ps
T212 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1661733059 Apr 18 01:23:38 PM PDT 24 Apr 18 01:24:07 PM PDT 24 25260686301 ps
T213 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3898565077 Apr 18 01:23:25 PM PDT 24 Apr 18 01:23:26 PM PDT 24 105985112 ps
T103 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2565670843 Apr 18 01:23:54 PM PDT 24 Apr 18 01:23:58 PM PDT 24 365188207 ps
T214 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1922398373 Apr 18 01:23:42 PM PDT 24 Apr 18 01:23:44 PM PDT 24 437999670 ps
T215 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3537670410 Apr 18 01:23:24 PM PDT 24 Apr 18 01:23:25 PM PDT 24 46259868 ps
T126 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1425907326 Apr 18 01:23:40 PM PDT 24 Apr 18 01:23:45 PM PDT 24 950100973 ps
T129 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2848432706 Apr 18 01:23:44 PM PDT 24 Apr 18 01:24:00 PM PDT 24 683295386 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3816925917 Apr 18 01:23:24 PM PDT 24 Apr 18 01:24:37 PM PDT 24 6696504171 ps
T216 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2850860073 Apr 18 01:23:33 PM PDT 24 Apr 18 01:23:38 PM PDT 24 1701480758 ps
T112 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.542474133 Apr 18 01:23:48 PM PDT 24 Apr 18 01:23:50 PM PDT 24 165241996 ps
T217 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1587192851 Apr 18 01:23:46 PM PDT 24 Apr 18 01:23:50 PM PDT 24 998218529 ps
T218 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3287755776 Apr 18 01:23:28 PM PDT 24 Apr 18 01:23:32 PM PDT 24 3952552554 ps
T219 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.206161583 Apr 18 01:23:54 PM PDT 24 Apr 18 01:23:57 PM PDT 24 279169040 ps
T220 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2768903184 Apr 18 01:23:48 PM PDT 24 Apr 18 01:23:52 PM PDT 24 130023249 ps
T221 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.786678479 Apr 18 01:23:19 PM PDT 24 Apr 18 01:23:27 PM PDT 24 908058588 ps
T222 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1955555125 Apr 18 01:23:24 PM PDT 24 Apr 18 01:24:01 PM PDT 24 14597812218 ps
T223 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2593818584 Apr 18 01:23:26 PM PDT 24 Apr 18 01:24:22 PM PDT 24 2932295089 ps
T224 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2708952830 Apr 18 01:23:38 PM PDT 24 Apr 18 01:23:39 PM PDT 24 208856354 ps
T62 /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.992926094 Apr 18 01:23:37 PM PDT 24 Apr 18 01:23:48 PM PDT 24 44578353973 ps
T225 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2163191213 Apr 18 01:23:35 PM PDT 24 Apr 18 01:23:38 PM PDT 24 86861544 ps
T226 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.103056220 Apr 18 01:23:41 PM PDT 24 Apr 18 01:23:43 PM PDT 24 50397736 ps
T227 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.851929589 Apr 18 01:23:42 PM PDT 24 Apr 18 01:23:46 PM PDT 24 773121610 ps
T228 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.4239557426 Apr 18 01:23:56 PM PDT 24 Apr 18 01:24:09 PM PDT 24 44751227937 ps
T130 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3470457847 Apr 18 01:23:45 PM PDT 24 Apr 18 01:24:05 PM PDT 24 1074640805 ps
T229 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3132201431 Apr 18 01:23:15 PM PDT 24 Apr 18 01:23:22 PM PDT 24 2686993884 ps
T230 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3146345393 Apr 18 01:23:52 PM PDT 24 Apr 18 01:23:56 PM PDT 24 2714331167 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1114613922 Apr 18 01:23:28 PM PDT 24 Apr 18 01:23:30 PM PDT 24 98962311 ps
T231 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3230956972 Apr 18 01:23:41 PM PDT 24 Apr 18 01:23:47 PM PDT 24 2479102653 ps
T232 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.333604839 Apr 18 01:23:29 PM PDT 24 Apr 18 01:23:30 PM PDT 24 28313219 ps
T233 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3388758978 Apr 18 01:23:12 PM PDT 24 Apr 18 01:23:15 PM PDT 24 914141454 ps
T104 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4145389524 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:46 PM PDT 24 200226209 ps
T234 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3069463702 Apr 18 01:23:38 PM PDT 24 Apr 18 01:23:41 PM PDT 24 2151449005 ps
T235 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2347564843 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:40 PM PDT 24 40900819 ps
T236 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4099434997 Apr 18 01:23:52 PM PDT 24 Apr 18 01:23:54 PM PDT 24 97632178 ps
T133 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1970576200 Apr 18 01:23:52 PM PDT 24 Apr 18 01:24:12 PM PDT 24 2227720921 ps
T131 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.559069682 Apr 18 01:23:18 PM PDT 24 Apr 18 01:23:34 PM PDT 24 470713407 ps
T237 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1535558051 Apr 18 01:23:51 PM PDT 24 Apr 18 01:24:38 PM PDT 24 16844952259 ps
T238 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2775989896 Apr 18 01:23:13 PM PDT 24 Apr 18 01:23:14 PM PDT 24 86301542 ps
T105 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.754806459 Apr 18 01:23:13 PM PDT 24 Apr 18 01:23:15 PM PDT 24 73245703 ps
T239 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3664886335 Apr 18 01:23:47 PM PDT 24 Apr 18 01:23:49 PM PDT 24 32686589 ps
T106 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2104976710 Apr 18 01:23:30 PM PDT 24 Apr 18 01:23:33 PM PDT 24 214956576 ps
T240 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2025915168 Apr 18 01:23:28 PM PDT 24 Apr 18 01:23:36 PM PDT 24 594177942 ps
T241 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2238594383 Apr 18 01:23:36 PM PDT 24 Apr 18 01:23:40 PM PDT 24 524736063 ps
T242 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3244880019 Apr 18 01:23:32 PM PDT 24 Apr 18 01:23:33 PM PDT 24 69232881 ps
T107 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4144418188 Apr 18 01:23:38 PM PDT 24 Apr 18 01:23:41 PM PDT 24 507292695 ps
T243 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2706481162 Apr 18 01:23:13 PM PDT 24 Apr 18 01:24:06 PM PDT 24 5854829036 ps
T244 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1488780703 Apr 18 01:23:50 PM PDT 24 Apr 18 01:23:54 PM PDT 24 1062959056 ps
T245 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3353755981 Apr 18 01:23:26 PM PDT 24 Apr 18 01:23:28 PM PDT 24 266514579 ps
T246 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1073766989 Apr 18 01:23:22 PM PDT 24 Apr 18 01:23:24 PM PDT 24 961665858 ps
T247 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.639790434 Apr 18 01:23:42 PM PDT 24 Apr 18 01:23:44 PM PDT 24 585243264 ps
T248 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2598280209 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:42 PM PDT 24 180815361 ps
T249 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2949731468 Apr 18 01:23:26 PM PDT 24 Apr 18 01:23:29 PM PDT 24 202883543 ps
T250 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.63279064 Apr 18 01:23:45 PM PDT 24 Apr 18 01:23:46 PM PDT 24 35432995 ps
T251 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3286308216 Apr 18 01:23:59 PM PDT 24 Apr 18 01:24:00 PM PDT 24 54342314 ps
T252 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.582738556 Apr 18 01:23:21 PM PDT 24 Apr 18 01:23:22 PM PDT 24 80706999 ps
T253 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.4004706567 Apr 18 01:23:43 PM PDT 24 Apr 18 01:23:57 PM PDT 24 16275151676 ps
T254 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.890677763 Apr 18 01:23:52 PM PDT 24 Apr 18 01:23:55 PM PDT 24 108026158 ps
T255 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3970224220 Apr 18 01:23:48 PM PDT 24 Apr 18 01:23:49 PM PDT 24 58404931 ps
T256 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2105236135 Apr 18 01:23:39 PM PDT 24 Apr 18 01:23:41 PM PDT 24 42996433 ps
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