Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.46 93.81 79.40 87.53 73.08 82.67 98.52 41.24


Total test records in report: 306
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html
T258 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.952129826 Apr 21 12:39:07 PM PDT 24 Apr 21 12:39:09 PM PDT 24 112676494 ps
T259 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2969095020 Apr 21 12:39:33 PM PDT 24 Apr 21 12:39:43 PM PDT 24 285155185 ps
T260 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3903522298 Apr 21 12:39:29 PM PDT 24 Apr 21 12:39:32 PM PDT 24 393855871 ps
T131 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3808793859 Apr 21 12:39:23 PM PDT 24 Apr 21 12:39:32 PM PDT 24 811047534 ps
T261 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.843723493 Apr 21 12:39:25 PM PDT 24 Apr 21 12:39:33 PM PDT 24 1053158287 ps
T262 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.172163574 Apr 21 12:39:28 PM PDT 24 Apr 21 12:39:37 PM PDT 24 2400274470 ps
T263 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3617444669 Apr 21 12:39:08 PM PDT 24 Apr 21 12:40:48 PM PDT 24 28047285767 ps
T264 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.309465356 Apr 21 12:39:39 PM PDT 24 Apr 21 12:39:47 PM PDT 24 432828078 ps
T265 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1076942257 Apr 21 12:39:29 PM PDT 24 Apr 21 12:39:32 PM PDT 24 198954254 ps
T266 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4230539213 Apr 21 12:39:26 PM PDT 24 Apr 21 12:39:34 PM PDT 24 2165739549 ps
T124 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3102017352 Apr 21 12:39:41 PM PDT 24 Apr 21 12:39:47 PM PDT 24 266818065 ps
T267 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.735297407 Apr 21 12:39:41 PM PDT 24 Apr 21 12:39:43 PM PDT 24 101588722 ps
T268 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3873565019 Apr 21 12:39:33 PM PDT 24 Apr 21 12:39:34 PM PDT 24 67405491 ps
T269 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2059855200 Apr 21 12:39:36 PM PDT 24 Apr 21 12:40:12 PM PDT 24 17142249786 ps
T270 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1555694994 Apr 21 12:39:37 PM PDT 24 Apr 21 12:39:40 PM PDT 24 347229095 ps
T271 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1708582441 Apr 21 12:39:38 PM PDT 24 Apr 21 12:39:41 PM PDT 24 653981836 ps
T272 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.346670789 Apr 21 12:39:24 PM PDT 24 Apr 21 12:39:25 PM PDT 24 73018457 ps
T273 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.667375917 Apr 21 12:39:05 PM PDT 24 Apr 21 12:39:06 PM PDT 24 21521016 ps
T274 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3264744914 Apr 21 12:39:19 PM PDT 24 Apr 21 12:39:21 PM PDT 24 84181386 ps
T275 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2649996603 Apr 21 12:39:41 PM PDT 24 Apr 21 12:39:50 PM PDT 24 898324594 ps
T276 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3788753691 Apr 21 12:39:19 PM PDT 24 Apr 21 12:39:28 PM PDT 24 701091096 ps
T277 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3149429724 Apr 21 12:39:39 PM PDT 24 Apr 21 12:39:41 PM PDT 24 35779123 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3959821771 Apr 21 12:39:30 PM PDT 24 Apr 21 12:39:32 PM PDT 24 210123978 ps
T279 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2034043133 Apr 21 12:39:29 PM PDT 24 Apr 21 12:39:57 PM PDT 24 10077700971 ps
T280 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.517059505 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:17 PM PDT 24 913676078 ps
T281 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1892288301 Apr 21 12:39:27 PM PDT 24 Apr 21 12:39:29 PM PDT 24 112313830 ps
T129 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3432773352 Apr 21 12:39:24 PM PDT 24 Apr 21 12:39:34 PM PDT 24 1120857120 ps
T282 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4005528983 Apr 21 12:39:14 PM PDT 24 Apr 21 12:39:17 PM PDT 24 441996177 ps
T283 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3370482797 Apr 21 12:39:30 PM PDT 24 Apr 21 12:39:32 PM PDT 24 201777538 ps
T284 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.208100261 Apr 21 12:39:38 PM PDT 24 Apr 21 12:39:40 PM PDT 24 63930709 ps
T285 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1438442115 Apr 21 12:39:21 PM PDT 24 Apr 21 12:39:24 PM PDT 24 108782585 ps
T130 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2613397244 Apr 21 12:39:42 PM PDT 24 Apr 21 12:40:04 PM PDT 24 3054006714 ps
T70 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2914739658 Apr 21 12:39:26 PM PDT 24 Apr 21 12:39:28 PM PDT 24 1076325766 ps
T286 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3774679168 Apr 21 12:39:05 PM PDT 24 Apr 21 12:39:47 PM PDT 24 33118864332 ps
T287 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.87716550 Apr 21 12:39:27 PM PDT 24 Apr 21 12:39:31 PM PDT 24 399991731 ps
T288 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3605003417 Apr 21 12:39:33 PM PDT 24 Apr 21 12:39:53 PM PDT 24 1869675136 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3087456173 Apr 21 12:39:24 PM PDT 24 Apr 21 12:39:25 PM PDT 24 178004434 ps
T290 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2507012910 Apr 21 12:39:35 PM PDT 24 Apr 21 12:39:37 PM PDT 24 467566957 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1891245932 Apr 21 12:39:18 PM PDT 24 Apr 21 12:39:20 PM PDT 24 47722909 ps
T110 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1149730325 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:41 PM PDT 24 2170001375 ps
T292 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3811438191 Apr 21 12:39:01 PM PDT 24 Apr 21 12:39:33 PM PDT 24 3248228333 ps
T293 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2131446614 Apr 21 12:39:48 PM PDT 24 Apr 21 12:39:50 PM PDT 24 43047470 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3282647455 Apr 21 12:39:21 PM PDT 24 Apr 21 12:39:26 PM PDT 24 6364691840 ps
T295 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2399406041 Apr 21 12:39:36 PM PDT 24 Apr 21 12:39:43 PM PDT 24 145661910 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3823674104 Apr 21 12:39:36 PM PDT 24 Apr 21 12:39:52 PM PDT 24 14527519610 ps
T297 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2471632231 Apr 21 12:39:48 PM PDT 24 Apr 21 12:39:51 PM PDT 24 72039088 ps
T298 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.602122368 Apr 21 12:39:30 PM PDT 24 Apr 21 12:39:32 PM PDT 24 70068444 ps
T299 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2236139858 Apr 21 12:39:33 PM PDT 24 Apr 21 12:39:39 PM PDT 24 2932115148 ps
T300 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1108309424 Apr 21 12:39:41 PM PDT 24 Apr 21 12:39:43 PM PDT 24 207431874 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1868595068 Apr 21 12:39:10 PM PDT 24 Apr 21 12:39:12 PM PDT 24 361245248 ps
T301 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2208364948 Apr 21 12:39:45 PM PDT 24 Apr 21 12:39:48 PM PDT 24 69324208 ps
T302 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3371552490 Apr 21 12:39:08 PM PDT 24 Apr 21 12:40:19 PM PDT 24 15245025046 ps
T303 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1502182170 Apr 21 12:39:48 PM PDT 24 Apr 21 12:39:51 PM PDT 24 76716658 ps
T304 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1100213359 Apr 21 12:39:19 PM PDT 24 Apr 21 12:39:22 PM PDT 24 137156644 ps
T305 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2973400159 Apr 21 12:39:54 PM PDT 24 Apr 21 12:39:59 PM PDT 24 1831887544 ps
T306 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4093423808 Apr 21 12:39:20 PM PDT 24 Apr 21 12:39:21 PM PDT 24 73571303 ps

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3598251634
Short name T28
Test name
Test status
Simulation time 30253096768 ps
CPU time 55.34 seconds
Started Apr 21 12:41:19 PM PDT 24
Finished Apr 21 12:42:15 PM PDT 24
Peak memory 213620 kb
Host smart-1370cba3-5c4c-41fc-bace-e7970ac65c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598251634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3598251634
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.840351334
Short name T11
Test name
Test status
Simulation time 3000414386 ps
CPU time 10.65 seconds
Started Apr 21 12:40:37 PM PDT 24
Finished Apr 21 12:40:48 PM PDT 24
Peak memory 205248 kb
Host smart-bfb0691b-a07f-49ff-a080-a90a763ff30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840351334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.840351334
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3302728023
Short name T3
Test name
Test status
Simulation time 111887924 ps
CPU time 0.73 seconds
Started Apr 21 12:41:00 PM PDT 24
Finished Apr 21 12:41:02 PM PDT 24
Peak memory 204952 kb
Host smart-eaa114ab-a48c-4cb2-80f3-eed90d99bdfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302728023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3302728023
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.613142624
Short name T66
Test name
Test status
Simulation time 37364151034 ps
CPU time 22.03 seconds
Started Apr 21 12:39:42 PM PDT 24
Finished Apr 21 12:40:05 PM PDT 24
Peak memory 221276 kb
Host smart-a4e73923-6854-4ba6-93e9-7633470b8778
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613142624 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.613142624
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2327276898
Short name T46
Test name
Test status
Simulation time 1637351227 ps
CPU time 22.37 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 221096 kb
Host smart-3af07ee6-e709-45cf-8c8c-ff683c23cc08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327276898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2327276898
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2188443635
Short name T23
Test name
Test status
Simulation time 2973832052 ps
CPU time 4.24 seconds
Started Apr 21 12:41:39 PM PDT 24
Finished Apr 21 12:41:43 PM PDT 24
Peak memory 205276 kb
Host smart-fd64f45f-59d4-4a57-a5f2-8e9d45ac49f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188443635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2188443635
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3741269682
Short name T12
Test name
Test status
Simulation time 233045039 ps
CPU time 1.19 seconds
Started Apr 21 12:40:39 PM PDT 24
Finished Apr 21 12:40:41 PM PDT 24
Peak memory 205324 kb
Host smart-8768413b-0d23-43c2-becb-a1b08418dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741269682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3741269682
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2162489997
Short name T32
Test name
Test status
Simulation time 186199054 ps
CPU time 1.1 seconds
Started Apr 21 12:40:40 PM PDT 24
Finished Apr 21 12:40:41 PM PDT 24
Peak memory 204848 kb
Host smart-0df59599-7754-4ca1-8635-eee55fe06e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162489997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2162489997
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3954269103
Short name T123
Test name
Test status
Simulation time 1321611331 ps
CPU time 6.44 seconds
Started Apr 21 12:39:35 PM PDT 24
Finished Apr 21 12:39:42 PM PDT 24
Peak memory 213040 kb
Host smart-3a71a6d6-bac6-4c65-854e-4d27bd5da01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954269103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3954269103
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3756962443
Short name T27
Test name
Test status
Simulation time 38190489 ps
CPU time 0.81 seconds
Started Apr 21 12:40:44 PM PDT 24
Finished Apr 21 12:40:45 PM PDT 24
Peak memory 205096 kb
Host smart-b65cfe3c-109a-4143-a849-c508eae30863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756962443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3756962443
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1018785075
Short name T84
Test name
Test status
Simulation time 4129674784 ps
CPU time 73.9 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:40:40 PM PDT 24
Peak memory 213032 kb
Host smart-a11c4b98-b45e-4eb3-93e8-d685da20c1a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018785075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1018785075
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2091794441
Short name T75
Test name
Test status
Simulation time 285293611 ps
CPU time 3.87 seconds
Started Apr 21 12:40:02 PM PDT 24
Finished Apr 21 12:40:06 PM PDT 24
Peak memory 213000 kb
Host smart-d591cd7e-8fc0-4a88-973e-e47285e4a04c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091794441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2091794441
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1046211363
Short name T60
Test name
Test status
Simulation time 2723550225 ps
CPU time 5.05 seconds
Started Apr 21 12:40:47 PM PDT 24
Finished Apr 21 12:40:52 PM PDT 24
Peak memory 205116 kb
Host smart-3cb9170d-49bf-4cc9-920c-5388a9fc1928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046211363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1046211363
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.866948780
Short name T55
Test name
Test status
Simulation time 175588977 ps
CPU time 1.48 seconds
Started Apr 21 12:40:54 PM PDT 24
Finished Apr 21 12:40:56 PM PDT 24
Peak memory 229656 kb
Host smart-a725cb86-ffda-4638-9c47-23a673fb533f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866948780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.866948780
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2613397244
Short name T130
Test name
Test status
Simulation time 3054006714 ps
CPU time 20.38 seconds
Started Apr 21 12:39:42 PM PDT 24
Finished Apr 21 12:40:04 PM PDT 24
Peak memory 221216 kb
Host smart-af2f51a0-1d6d-4c69-9b82-5b51e2282a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613397244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
613397244
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3495915339
Short name T14
Test name
Test status
Simulation time 72481666 ps
CPU time 0.84 seconds
Started Apr 21 12:40:41 PM PDT 24
Finished Apr 21 12:40:42 PM PDT 24
Peak memory 213164 kb
Host smart-4a03635e-44fb-48ab-973a-fa72a34dcdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495915339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3495915339
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3475272145
Short name T69
Test name
Test status
Simulation time 767497898 ps
CPU time 1.5 seconds
Started Apr 21 12:39:34 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 204684 kb
Host smart-6a12b515-8362-457d-a301-7071d4ea10b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475272145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3475272145
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3058678246
Short name T21
Test name
Test status
Simulation time 683673085 ps
CPU time 1.47 seconds
Started Apr 21 12:40:41 PM PDT 24
Finished Apr 21 12:40:44 PM PDT 24
Peak memory 204988 kb
Host smart-dba60666-7327-42d0-8e48-81486b742da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058678246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3058678246
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1149730325
Short name T110
Test name
Test status
Simulation time 2170001375 ps
CPU time 27.08 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 214140 kb
Host smart-f468ce40-e87e-4459-9eac-385a158b76be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149730325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1149730325
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.4034758360
Short name T229
Test name
Test status
Simulation time 4085499966 ps
CPU time 21.8 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 219340 kb
Host smart-079db499-41da-40d1-a8ee-0e6d846831a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034758360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.4
034758360
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.665988952
Short name T18
Test name
Test status
Simulation time 216045232 ps
CPU time 1.39 seconds
Started Apr 21 12:40:25 PM PDT 24
Finished Apr 21 12:40:27 PM PDT 24
Peak memory 205188 kb
Host smart-fc6cf813-b427-4225-984a-d49680466c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665988952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.665988952
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1751025369
Short name T126
Test name
Test status
Simulation time 942174661 ps
CPU time 8.5 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 220892 kb
Host smart-f9fe1804-c596-47c6-b8e3-163268712ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751025369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1751025369
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2843163300
Short name T24
Test name
Test status
Simulation time 54019475 ps
CPU time 0.84 seconds
Started Apr 21 12:40:36 PM PDT 24
Finished Apr 21 12:40:38 PM PDT 24
Peak memory 204952 kb
Host smart-92e9f6c6-3e3c-496e-a70b-21aae4cf8d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843163300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2843163300
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3488822748
Short name T71
Test name
Test status
Simulation time 54396453 ps
CPU time 0.83 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:25 PM PDT 24
Peak memory 204408 kb
Host smart-df3c07d6-3525-462d-a189-77d7382c0c6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488822748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3488822748
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3605003417
Short name T288
Test name
Test status
Simulation time 1869675136 ps
CPU time 19.75 seconds
Started Apr 21 12:39:33 PM PDT 24
Finished Apr 21 12:39:53 PM PDT 24
Peak memory 212992 kb
Host smart-11cc2f50-58b0-42fe-ac97-54a9f31af05e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605003417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
605003417
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.807827152
Short name T48
Test name
Test status
Simulation time 163374680 ps
CPU time 6.75 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:19 PM PDT 24
Peak memory 204812 kb
Host smart-67eb4415-d68c-4b37-80a6-8d9568fc0b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807827152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.807827152
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1129047479
Short name T128
Test name
Test status
Simulation time 1327669521 ps
CPU time 19.19 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:49 PM PDT 24
Peak memory 216932 kb
Host smart-39b22a72-765f-4c35-9a7a-58a3518398d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129047479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
129047479
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2025581438
Short name T7
Test name
Test status
Simulation time 893373933 ps
CPU time 1.43 seconds
Started Apr 21 12:40:43 PM PDT 24
Finished Apr 21 12:40:45 PM PDT 24
Peak memory 204932 kb
Host smart-8c9469b9-690f-4f68-964c-0b0efcff33f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025581438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2025581438
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1904866735
Short name T15
Test name
Test status
Simulation time 27124673 ps
CPU time 0.68 seconds
Started Apr 21 12:41:38 PM PDT 24
Finished Apr 21 12:41:39 PM PDT 24
Peak memory 204936 kb
Host smart-9e6cdc88-9866-4bf5-83e4-ee9e30c04170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904866735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1904866735
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3104486765
Short name T105
Test name
Test status
Simulation time 334847087 ps
CPU time 2.12 seconds
Started Apr 21 12:39:45 PM PDT 24
Finished Apr 21 12:39:48 PM PDT 24
Peak memory 218248 kb
Host smart-7fbe9f41-30ba-47c6-8e35-9c570506e04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104486765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3104486765
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2585877847
Short name T250
Test name
Test status
Simulation time 803815931 ps
CPU time 9.62 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:30 PM PDT 24
Peak memory 213040 kb
Host smart-55121a0c-fdeb-46b2-a154-270e3a721222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585877847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
585877847
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1988284891
Short name T45
Test name
Test status
Simulation time 2033160692 ps
CPU time 10.6 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:29 PM PDT 24
Peak memory 212984 kb
Host smart-54e996ac-2337-41c0-b265-61690087ff50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988284891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1988284891
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3010233183
Short name T210
Test name
Test status
Simulation time 11413258294 ps
CPU time 40.11 seconds
Started Apr 21 12:39:22 PM PDT 24
Finished Apr 21 12:40:03 PM PDT 24
Peak memory 220820 kb
Host smart-83d0c43d-12e0-47d2-b4b4-79cc0e276964
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010233183 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3010233183
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3379315269
Short name T74
Test name
Test status
Simulation time 7704620697 ps
CPU time 5.14 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:55 PM PDT 24
Peak memory 219768 kb
Host smart-2f5c7786-bf5d-40f3-b9e4-922168f22120
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379315269 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3379315269
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1604599949
Short name T62
Test name
Test status
Simulation time 81080253 ps
CPU time 0.7 seconds
Started Apr 21 12:41:31 PM PDT 24
Finished Apr 21 12:41:32 PM PDT 24
Peak memory 205020 kb
Host smart-be2cc239-a773-4a93-b13d-1ccfa89048ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604599949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1604599949
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3811438191
Short name T292
Test name
Test status
Simulation time 3248228333 ps
CPU time 30.63 seconds
Started Apr 21 12:39:01 PM PDT 24
Finished Apr 21 12:39:33 PM PDT 24
Peak memory 214020 kb
Host smart-39d5ff68-1279-404f-8c16-3ff7a1cbfed0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811438191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3811438191
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3371552490
Short name T302
Test name
Test status
Simulation time 15245025046 ps
CPU time 70.44 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:40:19 PM PDT 24
Peak memory 213184 kb
Host smart-693b764e-d46b-4a7b-8d7f-e802a086f341
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371552490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3371552490
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2881950743
Short name T83
Test name
Test status
Simulation time 259668693 ps
CPU time 1.59 seconds
Started Apr 21 12:39:14 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 212960 kb
Host smart-9cd319b9-3347-41ed-8cf8-2525b18cb734
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881950743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2881950743
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1555694994
Short name T270
Test name
Test status
Simulation time 347229095 ps
CPU time 2.24 seconds
Started Apr 21 12:39:37 PM PDT 24
Finished Apr 21 12:39:40 PM PDT 24
Peak memory 216112 kb
Host smart-b607a508-ee6c-4312-9abd-63a632e0c807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555694994 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1555694994
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.952129826
Short name T258
Test name
Test status
Simulation time 112676494 ps
CPU time 1.53 seconds
Started Apr 21 12:39:07 PM PDT 24
Finished Apr 21 12:39:09 PM PDT 24
Peak memory 213032 kb
Host smart-3dd46804-f9ba-4abe-a2c3-b77f01e56251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952129826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.952129826
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.148989754
Short name T181
Test name
Test status
Simulation time 9044021216 ps
CPU time 10.26 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 204864 kb
Host smart-74176545-452c-4b34-970a-6d4ee937d126
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148989754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.148989754
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3774679168
Short name T286
Test name
Test status
Simulation time 33118864332 ps
CPU time 41.42 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 204752 kb
Host smart-df73a8af-ae7d-4900-8e7c-0401b0fadefe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774679168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.3774679168
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3244998571
Short name T96
Test name
Test status
Simulation time 1619446876 ps
CPU time 1.81 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 204744 kb
Host smart-951d9490-fac6-4b9f-ad83-cbfb504b2546
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244998571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3244998571
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3436616075
Short name T252
Test name
Test status
Simulation time 281301012 ps
CPU time 1.77 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:08 PM PDT 24
Peak memory 204612 kb
Host smart-f954b8fa-a1eb-43a9-91a2-3e567d6b46fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436616075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
436616075
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3934211496
Short name T174
Test name
Test status
Simulation time 832811407 ps
CPU time 4.26 seconds
Started Apr 21 12:39:21 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 204668 kb
Host smart-561ee170-5718-4418-befc-becda0c8ce64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934211496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3934211496
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3264744914
Short name T274
Test name
Test status
Simulation time 84181386 ps
CPU time 0.74 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 204452 kb
Host smart-390976d4-8fa2-4188-be30-b6eb364523f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264744914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3264744914
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1877885072
Short name T200
Test name
Test status
Simulation time 75396489 ps
CPU time 0.72 seconds
Started Apr 21 12:39:11 PM PDT 24
Finished Apr 21 12:39:12 PM PDT 24
Peak memory 204424 kb
Host smart-541a15d0-c3f3-44eb-9055-1703336a04a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877885072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
877885072
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3761016360
Short name T254
Test name
Test status
Simulation time 26466673 ps
CPU time 0.74 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203536 kb
Host smart-b815c47b-2bfd-42b0-96d9-eb8014918386
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761016360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3761016360
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3391878120
Short name T222
Test name
Test status
Simulation time 30410453 ps
CPU time 0.65 seconds
Started Apr 21 12:39:14 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 204324 kb
Host smart-43f995bb-365d-43c1-9509-15263daa1d05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391878120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3391878120
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.520529246
Short name T214
Test name
Test status
Simulation time 293956747 ps
CPU time 2.7 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 213016 kb
Host smart-60f61731-cee5-4450-8a72-701a18d38f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520529246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.520529246
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1896878098
Short name T231
Test name
Test status
Simulation time 21155286337 ps
CPU time 29.89 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204832 kb
Host smart-add2ce2f-aca4-41e1-8542-dcd1c1468d42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896878098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1896878098
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1008131280
Short name T194
Test name
Test status
Simulation time 7596046231 ps
CPU time 72.5 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:40:21 PM PDT 24
Peak memory 204964 kb
Host smart-aa84a4f1-14ea-4458-81f2-0aad876c8f79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008131280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1008131280
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.247385048
Short name T103
Test name
Test status
Simulation time 144823407 ps
CPU time 2.48 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 212920 kb
Host smart-c66d6823-4099-41b2-83db-7403e2e2f056
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247385048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.247385048
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1279105927
Short name T187
Test name
Test status
Simulation time 227794505 ps
CPU time 2.44 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:30 PM PDT 24
Peak memory 212964 kb
Host smart-16aa18af-859f-4670-856e-1dfda979ee1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279105927 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1279105927
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2373582810
Short name T107
Test name
Test status
Simulation time 85755392 ps
CPU time 2.03 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 218392 kb
Host smart-21d98bc5-0d05-4370-a7ee-a8d5e952bc28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373582810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2373582810
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1328657572
Short name T221
Test name
Test status
Simulation time 17774776056 ps
CPU time 35.84 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204720 kb
Host smart-9d2b080a-70cc-41fc-a157-dc6e8da4393e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328657572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1328657572
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3617444669
Short name T263
Test name
Test status
Simulation time 28047285767 ps
CPU time 99.58 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:40:48 PM PDT 24
Peak memory 204776 kb
Host smart-0134e79d-916b-4eb6-bf51-85f5b4cc3722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617444669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3617444669
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1868595068
Short name T98
Test name
Test status
Simulation time 361245248 ps
CPU time 1.52 seconds
Started Apr 21 12:39:10 PM PDT 24
Finished Apr 21 12:39:12 PM PDT 24
Peak memory 204628 kb
Host smart-57c03500-4249-498e-a92d-e919c66af373
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868595068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1868595068
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1655690402
Short name T185
Test name
Test status
Simulation time 1653112540 ps
CPU time 2.56 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:30 PM PDT 24
Peak memory 204596 kb
Host smart-34877882-bc4a-44b0-bb1a-dbbaff341b75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655690402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
655690402
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1934208307
Short name T177
Test name
Test status
Simulation time 157074118 ps
CPU time 0.94 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203532 kb
Host smart-9570f6c3-0785-4a19-9d11-598cab388c5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934208307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1934208307
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.517059505
Short name T280
Test name
Test status
Simulation time 913676078 ps
CPU time 2.38 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 204716 kb
Host smart-b0f320ea-47d7-4033-84c4-3b4ba5f6f950
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517059505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.517059505
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2091346294
Short name T228
Test name
Test status
Simulation time 58053807 ps
CPU time 0.73 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:30 PM PDT 24
Peak memory 204472 kb
Host smart-ad9c8170-2f02-4f23-8249-93a8bdc860af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091346294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2091346294
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2175124976
Short name T188
Test name
Test status
Simulation time 88084872 ps
CPU time 0.93 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 204416 kb
Host smart-0a57105a-ba35-46e3-8a50-c46999d2bcea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175124976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
175124976
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.667375917
Short name T273
Test name
Test status
Simulation time 21521016 ps
CPU time 0.68 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:06 PM PDT 24
Peak memory 204408 kb
Host smart-1a8fee66-be67-46eb-86d0-ddadfff71082
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667375917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.667375917
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2286749585
Short name T219
Test name
Test status
Simulation time 31604828 ps
CPU time 0.76 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 204408 kb
Host smart-56d09dcc-c705-4879-adc0-6da40d6a3da2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286749585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2286749585
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3001998950
Short name T104
Test name
Test status
Simulation time 581559623 ps
CPU time 7.79 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 204692 kb
Host smart-bf9c266f-2b45-4d55-9547-af10f52707c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001998950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3001998950
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2336583770
Short name T195
Test name
Test status
Simulation time 366956899 ps
CPU time 2.74 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 213004 kb
Host smart-1c6c2c44-d68f-461b-a8b8-4ace6edec9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336583770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2336583770
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.602122368
Short name T298
Test name
Test status
Simulation time 70068444 ps
CPU time 2.19 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 218640 kb
Host smart-1d224584-d17c-43d5-8425-bcc69f32016e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602122368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.602122368
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1076510303
Short name T209
Test name
Test status
Simulation time 1456058151 ps
CPU time 2.15 seconds
Started Apr 21 12:39:32 PM PDT 24
Finished Apr 21 12:39:35 PM PDT 24
Peak memory 204640 kb
Host smart-1de593dc-c8c7-49f5-a10e-33d9b8342983
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076510303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1076510303
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2806671486
Short name T176
Test name
Test status
Simulation time 49009562 ps
CPU time 0.74 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 204512 kb
Host smart-b0913007-2b66-46e6-ab92-2e53d9aab354
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806671486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2806671486
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3752190447
Short name T218
Test name
Test status
Simulation time 569689169 ps
CPU time 8.09 seconds
Started Apr 21 12:39:31 PM PDT 24
Finished Apr 21 12:39:39 PM PDT 24
Peak memory 204780 kb
Host smart-d66a1da9-043a-4580-89e5-b71b576b802a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752190447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3752190447
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1587942999
Short name T211
Test name
Test status
Simulation time 43667291 ps
CPU time 2.24 seconds
Started Apr 21 12:39:51 PM PDT 24
Finished Apr 21 12:39:54 PM PDT 24
Peak memory 213076 kb
Host smart-c66116cd-0d7d-4a7e-a43c-1735cfa68bff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587942999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1587942999
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2208364948
Short name T301
Test name
Test status
Simulation time 69324208 ps
CPU time 2.33 seconds
Started Apr 21 12:39:45 PM PDT 24
Finished Apr 21 12:39:48 PM PDT 24
Peak memory 217784 kb
Host smart-db8d4b2a-d611-49a3-a54f-b21001016420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208364948 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2208364948
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1502182170
Short name T303
Test name
Test status
Simulation time 76716658 ps
CPU time 1.61 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:51 PM PDT 24
Peak memory 218436 kb
Host smart-978d682a-13ef-492b-a78d-93dbe56e10cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502182170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1502182170
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2507012910
Short name T290
Test name
Test status
Simulation time 467566957 ps
CPU time 1.31 seconds
Started Apr 21 12:39:35 PM PDT 24
Finished Apr 21 12:39:37 PM PDT 24
Peak memory 204688 kb
Host smart-f6896911-696c-4723-be8d-fd26377fa8f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507012910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2507012910
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2763571424
Short name T73
Test name
Test status
Simulation time 45395230 ps
CPU time 0.82 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 204496 kb
Host smart-4b8af5ec-31f1-4e5f-bc1f-23c48be4534f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763571424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2763571424
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.309465356
Short name T264
Test name
Test status
Simulation time 432828078 ps
CPU time 7.6 seconds
Started Apr 21 12:39:39 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 204752 kb
Host smart-da025bb0-d30a-4b39-96ec-3be781b6a1ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309465356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.309465356
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1346436438
Short name T92
Test name
Test status
Simulation time 598757111 ps
CPU time 3.11 seconds
Started Apr 21 12:39:32 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 213020 kb
Host smart-d9b5360c-1f1d-41f3-a8ea-7c80c3ed8eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346436438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1346436438
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1192871195
Short name T251
Test name
Test status
Simulation time 495374001 ps
CPU time 15.5 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:42 PM PDT 24
Peak memory 221028 kb
Host smart-987cd624-4a22-487b-8988-3573fc65d6be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192871195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
192871195
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3767815496
Short name T239
Test name
Test status
Simulation time 145541018 ps
CPU time 2.14 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:39 PM PDT 24
Peak memory 214692 kb
Host smart-e0ab62f4-68a4-4fe3-9e88-b8a543d77d7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767815496 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3767815496
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3649499302
Short name T82
Test name
Test status
Simulation time 103731726 ps
CPU time 1.46 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 221092 kb
Host smart-fdbc660b-ad72-4211-93a3-1799ad558172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649499302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3649499302
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1108309424
Short name T300
Test name
Test status
Simulation time 207431874 ps
CPU time 1.05 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 204592 kb
Host smart-4afd0a8a-e47d-4367-827e-20bb04a0d43a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108309424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1108309424
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.744200106
Short name T230
Test name
Test status
Simulation time 22881506 ps
CPU time 0.71 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:29 PM PDT 24
Peak memory 204512 kb
Host smart-18bef2eb-ec7f-469e-b609-dfa95d4e3c4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744200106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.744200106
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.8842538
Short name T245
Test name
Test status
Simulation time 293158668 ps
CPU time 3.81 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 204828 kb
Host smart-4049c157-0615-4bce-bd1b-5645eca72bda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8842538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_cs
r_outstanding.8842538
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.4199184966
Short name T204
Test name
Test status
Simulation time 13761082431 ps
CPU time 47.3 seconds
Started Apr 21 12:39:47 PM PDT 24
Finished Apr 21 12:40:36 PM PDT 24
Peak memory 226484 kb
Host smart-e4279dc7-357f-4680-b076-07e3af8bcd58
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199184966 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.4199184966
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3903522298
Short name T260
Test name
Test status
Simulation time 393855871 ps
CPU time 2.77 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 213076 kb
Host smart-356b2800-dbde-47b4-8bda-b3478142aafa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903522298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3903522298
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1149837215
Short name T179
Test name
Test status
Simulation time 922207595 ps
CPU time 2.29 seconds
Started Apr 21 12:39:32 PM PDT 24
Finished Apr 21 12:39:35 PM PDT 24
Peak memory 214724 kb
Host smart-ef75c5ed-472d-4b6e-a850-f1cf5722998b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149837215 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1149837215
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3703940611
Short name T86
Test name
Test status
Simulation time 323573639 ps
CPU time 1.58 seconds
Started Apr 21 12:39:37 PM PDT 24
Finished Apr 21 12:39:39 PM PDT 24
Peak memory 212892 kb
Host smart-9f00f579-5147-4cbd-adac-eb92b99e9326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703940611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3703940611
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.863752575
Short name T186
Test name
Test status
Simulation time 439474346 ps
CPU time 1.45 seconds
Started Apr 21 12:39:40 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 204592 kb
Host smart-7b9d06b0-278c-4a8d-bef4-b2953a38987d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863752575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.863752575
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3873565019
Short name T268
Test name
Test status
Simulation time 67405491 ps
CPU time 0.66 seconds
Started Apr 21 12:39:33 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 204408 kb
Host smart-cc3dfdc2-08d9-43dd-a419-a6afbfcdf3b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873565019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3873565019
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3389185971
Short name T115
Test name
Test status
Simulation time 963790588 ps
CPU time 4.36 seconds
Started Apr 21 12:39:45 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204800 kb
Host smart-56030638-bc31-457b-8069-ba1b758aa962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389185971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3389185971
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3829097396
Short name T120
Test name
Test status
Simulation time 466194172 ps
CPU time 5 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 212960 kb
Host smart-adb5ae54-d203-488a-8cf9-6b7caf30ee59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829097396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3829097396
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2236139858
Short name T299
Test name
Test status
Simulation time 2932115148 ps
CPU time 5.24 seconds
Started Apr 21 12:39:33 PM PDT 24
Finished Apr 21 12:39:39 PM PDT 24
Peak memory 218456 kb
Host smart-aa3a3ed3-fd95-464c-84da-eea8ec759db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236139858 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2236139858
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.963747676
Short name T196
Test name
Test status
Simulation time 543153996 ps
CPU time 1.43 seconds
Started Apr 21 12:39:21 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 204656 kb
Host smart-3db9d76f-17a1-45b7-8cad-36d60469dd9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963747676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.963747676
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2471632231
Short name T297
Test name
Test status
Simulation time 72039088 ps
CPU time 0.74 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:51 PM PDT 24
Peak memory 204432 kb
Host smart-58eee4f3-4a12-4447-9d74-d11e06edd649
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471632231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2471632231
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.843723493
Short name T261
Test name
Test status
Simulation time 1053158287 ps
CPU time 7.36 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:33 PM PDT 24
Peak memory 204844 kb
Host smart-e5aaae00-c8d3-4e46-92ff-8bf5ba6504f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843723493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.843723493
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3755431178
Short name T201
Test name
Test status
Simulation time 33652704570 ps
CPU time 21.7 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:59 PM PDT 24
Peak memory 229604 kb
Host smart-7650e271-e6d2-4050-8d8e-f8fc05758f30
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755431178 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.3755431178
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2969095020
Short name T259
Test name
Test status
Simulation time 285155185 ps
CPU time 8.77 seconds
Started Apr 21 12:39:33 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 221076 kb
Host smart-5ff3fb96-a734-414f-af2b-940f91864406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969095020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
969095020
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3427080001
Short name T47
Test name
Test status
Simulation time 188851628 ps
CPU time 3.81 seconds
Started Apr 21 12:39:50 PM PDT 24
Finished Apr 21 12:39:55 PM PDT 24
Peak memory 221120 kb
Host smart-0cd29576-6274-4c35-978e-532806959cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427080001 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3427080001
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2552455780
Short name T257
Test name
Test status
Simulation time 93342788 ps
CPU time 1.43 seconds
Started Apr 21 12:39:47 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 213088 kb
Host smart-50daf208-90d0-4811-8c98-8a88b705b382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552455780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2552455780
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.102393256
Short name T190
Test name
Test status
Simulation time 1230075816 ps
CPU time 2.9 seconds
Started Apr 21 12:39:51 PM PDT 24
Finished Apr 21 12:39:55 PM PDT 24
Peak memory 204588 kb
Host smart-cb9be267-7164-4edc-9745-d210b9adede7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102393256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.102393256
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2466935585
Short name T192
Test name
Test status
Simulation time 92375058 ps
CPU time 0.74 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204492 kb
Host smart-c160321f-8bdb-42c7-bc18-a00f7c564449
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466935585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2466935585
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.196658249
Short name T118
Test name
Test status
Simulation time 821108448 ps
CPU time 7.7 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204796 kb
Host smart-22613803-bb6c-4029-a266-622009fa46cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196658249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.196658249
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4061187164
Short name T78
Test name
Test status
Simulation time 300084675 ps
CPU time 2.83 seconds
Started Apr 21 12:39:32 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 212956 kb
Host smart-a87fa178-ed4e-4806-a19c-50bc3a2fc058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061187164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4061187164
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2415395674
Short name T119
Test name
Test status
Simulation time 1036547825 ps
CPU time 10.48 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:48 PM PDT 24
Peak memory 213192 kb
Host smart-4726322c-187f-4c64-9089-99e646cf103f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415395674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
415395674
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.221635709
Short name T225
Test name
Test status
Simulation time 66637516 ps
CPU time 2.52 seconds
Started Apr 21 12:39:44 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 212872 kb
Host smart-0f42410f-e632-4f75-bab0-aa6ad65937dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221635709 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.221635709
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.199840926
Short name T244
Test name
Test status
Simulation time 147863221 ps
CPU time 2.31 seconds
Started Apr 21 12:39:54 PM PDT 24
Finished Apr 21 12:39:58 PM PDT 24
Peak memory 218276 kb
Host smart-821706f6-65ba-414a-b13c-e65420fe446c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199840926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.199840926
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2478932359
Short name T189
Test name
Test status
Simulation time 265268062 ps
CPU time 0.98 seconds
Started Apr 21 12:39:46 PM PDT 24
Finished Apr 21 12:39:48 PM PDT 24
Peak memory 204596 kb
Host smart-39cdaa4d-ffb3-4004-890c-8e4e3d640dbf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478932359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2478932359
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.735297407
Short name T267
Test name
Test status
Simulation time 101588722 ps
CPU time 0.9 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 204428 kb
Host smart-f90de713-f56b-46c6-a225-4e7a5c0826a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735297407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.735297407
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1053816012
Short name T234
Test name
Test status
Simulation time 520160968 ps
CPU time 4.5 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 204836 kb
Host smart-3c8d309b-2544-4628-9879-1dfb528fa359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053816012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1053816012
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2084785889
Short name T215
Test name
Test status
Simulation time 140996331 ps
CPU time 3.58 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:39 PM PDT 24
Peak memory 213044 kb
Host smart-17b01c04-c2f3-473a-94e8-feeda81c0859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084785889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2084785889
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1708582441
Short name T271
Test name
Test status
Simulation time 653981836 ps
CPU time 2.7 seconds
Started Apr 21 12:39:38 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 220768 kb
Host smart-3f3758ef-7ee2-4b6b-9b95-7933f734bd6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708582441 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1708582441
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2532222028
Short name T101
Test name
Test status
Simulation time 131950885 ps
CPU time 2.17 seconds
Started Apr 21 12:39:40 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 212976 kb
Host smart-adefdb33-7842-4589-ab29-e4d222418948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532222028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2532222028
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2327718048
Short name T237
Test name
Test status
Simulation time 1170497883 ps
CPU time 1.96 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:33 PM PDT 24
Peak memory 204656 kb
Host smart-758790b2-c09b-404c-a1eb-e67555deabba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327718048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2327718048
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3423001169
Short name T205
Test name
Test status
Simulation time 89220456 ps
CPU time 0.93 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 204416 kb
Host smart-eecd69c8-428c-4a60-bf38-bf7e6a3c75cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423001169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3423001169
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3705813133
Short name T117
Test name
Test status
Simulation time 147630225 ps
CPU time 6.3 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:39:35 PM PDT 24
Peak memory 204712 kb
Host smart-58e7e316-8d0d-43b3-af5b-386d086c0984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705813133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3705813133
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3102017352
Short name T124
Test name
Test status
Simulation time 266818065 ps
CPU time 5.53 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 213056 kb
Host smart-06122c20-2766-4831-b880-07a71ea5e0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102017352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3102017352
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3305756512
Short name T76
Test name
Test status
Simulation time 2110222047 ps
CPU time 7.4 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:38 PM PDT 24
Peak memory 212900 kb
Host smart-cb5dc9bd-4763-4280-8a4c-3f34662441f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305756512 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3305756512
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2210600422
Short name T108
Test name
Test status
Simulation time 93900215 ps
CPU time 2.25 seconds
Started Apr 21 12:39:33 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 218348 kb
Host smart-9a3bab8c-b286-4812-9df0-47478d525f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210600422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2210600422
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.151015586
Short name T171
Test name
Test status
Simulation time 1172648074 ps
CPU time 2.71 seconds
Started Apr 21 12:39:37 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 204684 kb
Host smart-a9fdf7be-72da-4009-a696-b32e02c00b20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151015586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.151015586
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1869079243
Short name T248
Test name
Test status
Simulation time 78586439 ps
CPU time 0.81 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 204412 kb
Host smart-fb58bde8-2513-4631-ab13-b18cef350fff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869079243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1869079243
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.567063426
Short name T100
Test name
Test status
Simulation time 574106331 ps
CPU time 6.61 seconds
Started Apr 21 12:39:45 PM PDT 24
Finished Apr 21 12:39:52 PM PDT 24
Peak memory 204808 kb
Host smart-1e7e96d6-a1e9-4f60-b3da-1ca42fe50c12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567063426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.567063426
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2059855200
Short name T269
Test name
Test status
Simulation time 17142249786 ps
CPU time 35.42 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:40:12 PM PDT 24
Peak memory 221320 kb
Host smart-56049af9-4bd9-43da-8b4c-ac9353607d15
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059855200 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.2059855200
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2981554865
Short name T122
Test name
Test status
Simulation time 416485610 ps
CPU time 4.77 seconds
Started Apr 21 12:40:00 PM PDT 24
Finished Apr 21 12:40:05 PM PDT 24
Peak memory 212944 kb
Host smart-f8581735-0d43-456d-83ea-92c151d605e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981554865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2981554865
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3464417774
Short name T125
Test name
Test status
Simulation time 3510525736 ps
CPU time 15.3 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:39:44 PM PDT 24
Peak memory 212996 kb
Host smart-6334a9ce-9c52-41c5-8ca1-ff180ac5d782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464417774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
464417774
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2973400159
Short name T305
Test name
Test status
Simulation time 1831887544 ps
CPU time 3.9 seconds
Started Apr 21 12:39:54 PM PDT 24
Finished Apr 21 12:39:59 PM PDT 24
Peak memory 217540 kb
Host smart-e3b2428b-3371-4543-bf67-bd81e6fc8b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973400159 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2973400159
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3563028421
Short name T238
Test name
Test status
Simulation time 75429880 ps
CPU time 2 seconds
Started Apr 21 12:39:44 PM PDT 24
Finished Apr 21 12:39:46 PM PDT 24
Peak memory 212984 kb
Host smart-2011a2a7-5d50-40e3-9321-e0020b0657ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563028421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3563028421
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3853448700
Short name T198
Test name
Test status
Simulation time 2338341783 ps
CPU time 8.05 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204756 kb
Host smart-b6dc48aa-c5f8-4b37-b86b-aa49e40c0788
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853448700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3853448700
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1353389724
Short name T233
Test name
Test status
Simulation time 25908038 ps
CPU time 0.74 seconds
Started Apr 21 12:39:44 PM PDT 24
Finished Apr 21 12:39:45 PM PDT 24
Peak memory 204444 kb
Host smart-cd4765a1-12a3-4f5c-ae9a-8e392bc7a4da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353389724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1353389724
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1666383079
Short name T102
Test name
Test status
Simulation time 852033518 ps
CPU time 4.04 seconds
Started Apr 21 12:39:35 PM PDT 24
Finished Apr 21 12:39:40 PM PDT 24
Peak memory 204712 kb
Host smart-e89ff495-cd3b-4f29-81eb-e8cbf082c3c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666383079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1666383079
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2649996603
Short name T275
Test name
Test status
Simulation time 898324594 ps
CPU time 8.33 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 212980 kb
Host smart-be578d55-47ff-4969-9d6d-3495de21d607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649996603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
649996603
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1230575994
Short name T112
Test name
Test status
Simulation time 21529212046 ps
CPU time 39.95 seconds
Started Apr 21 12:39:31 PM PDT 24
Finished Apr 21 12:40:12 PM PDT 24
Peak memory 204904 kb
Host smart-5b80cf73-2147-4b00-ad6e-6fb5da1203d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230575994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1230575994
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1478302926
Short name T89
Test name
Test status
Simulation time 228352414 ps
CPU time 2.49 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 213264 kb
Host smart-645a53f5-489e-4478-a181-8210223bcca2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478302926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1478302926
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2961420049
Short name T193
Test name
Test status
Simulation time 3064856207 ps
CPU time 6.85 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:25 PM PDT 24
Peak memory 220928 kb
Host smart-31a47d11-8261-4173-afbc-1ed20c331dbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961420049 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2961420049
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2719114775
Short name T109
Test name
Test status
Simulation time 181842597 ps
CPU time 2.45 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 218016 kb
Host smart-4c4931cc-3fa0-4902-a1d8-1f13cd70600d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719114775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2719114775
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2888936164
Short name T183
Test name
Test status
Simulation time 39603676477 ps
CPU time 55.2 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:40:21 PM PDT 24
Peak memory 204772 kb
Host smart-a9aec6a7-afe2-4a5b-8e8a-07069a9210be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888936164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2888936164
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1248315931
Short name T172
Test name
Test status
Simulation time 48115898399 ps
CPU time 56.39 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:40:24 PM PDT 24
Peak memory 204796 kb
Host smart-976f384e-3721-484f-ad81-dc41ca846ec3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248315931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.1248315931
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3215168280
Short name T95
Test name
Test status
Simulation time 1759100806 ps
CPU time 4.17 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 204704 kb
Host smart-138fde0e-7763-4208-9b7d-a860aff28b8e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215168280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3215168280
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4259083751
Short name T182
Test name
Test status
Simulation time 346431126 ps
CPU time 0.96 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 204668 kb
Host smart-2bec1d93-c4c5-4609-a6f7-26c71e2d2278
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259083751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4
259083751
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3370482797
Short name T283
Test name
Test status
Simulation time 201777538 ps
CPU time 0.8 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 204436 kb
Host smart-380f9727-049c-44dd-bd68-05744d4bbfec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370482797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3370482797
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4230539213
Short name T266
Test name
Test status
Simulation time 2165739549 ps
CPU time 7.4 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 204768 kb
Host smart-c510829d-5951-415f-b26b-ea20d3dcbc5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230539213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4230539213
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.208100261
Short name T284
Test name
Test status
Simulation time 63930709 ps
CPU time 0.74 seconds
Started Apr 21 12:39:38 PM PDT 24
Finished Apr 21 12:39:40 PM PDT 24
Peak memory 204460 kb
Host smart-98cd7093-557a-4d1a-b57a-4a6787672005
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208100261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.208100261
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1103622979
Short name T247
Test name
Test status
Simulation time 26493657 ps
CPU time 0.73 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 204492 kb
Host smart-501ae1d3-877b-454a-a241-a080a75aa715
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103622979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
103622979
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3704205176
Short name T241
Test name
Test status
Simulation time 84991558 ps
CPU time 0.68 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:37 PM PDT 24
Peak memory 204388 kb
Host smart-abe3cdfd-171f-42a4-9e45-8eb204027690
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704205176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3704205176
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3087456173
Short name T289
Test name
Test status
Simulation time 178004434 ps
CPU time 0.67 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:25 PM PDT 24
Peak memory 204460 kb
Host smart-bd65e101-d70a-44df-93fd-b0bda7b924fa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087456173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3087456173
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4072513344
Short name T116
Test name
Test status
Simulation time 121002316 ps
CPU time 3.46 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 204700 kb
Host smart-ba9a0c31-7105-4ad8-be96-f387edc0151c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072513344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.4072513344
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4168367272
Short name T253
Test name
Test status
Simulation time 777266397 ps
CPU time 5.18 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 213100 kb
Host smart-7f2e6586-a7b9-4561-86b3-204ba3098e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168367272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4168367272
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.4261041874
Short name T132
Test name
Test status
Simulation time 16231649413 ps
CPU time 14.85 seconds
Started Apr 21 12:40:12 PM PDT 24
Finished Apr 21 12:40:27 PM PDT 24
Peak memory 215540 kb
Host smart-d6e644c1-17fc-4137-bed6-736859acedb9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261041874 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.4261041874
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2621128403
Short name T113
Test name
Test status
Simulation time 6793473641 ps
CPU time 73.93 seconds
Started Apr 21 12:39:44 PM PDT 24
Finished Apr 21 12:40:59 PM PDT 24
Peak memory 213088 kb
Host smart-dfee9858-0b35-45aa-805d-1baec58b950b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621128403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2621128403
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3289096877
Short name T256
Test name
Test status
Simulation time 7437736537 ps
CPU time 37.41 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:40:06 PM PDT 24
Peak memory 204924 kb
Host smart-d233c154-93bd-4436-89aa-9f3c1f62f0ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289096877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3289096877
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1803238187
Short name T232
Test name
Test status
Simulation time 253528181 ps
CPU time 1.69 seconds
Started Apr 21 12:39:14 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 213032 kb
Host smart-c8483046-6ff7-435b-9e72-4a7a447043a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803238187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1803238187
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3822463857
Short name T77
Test name
Test status
Simulation time 1233429724 ps
CPU time 2.38 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 216360 kb
Host smart-82af8ae2-ee5a-49fd-8865-85bc9090246f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822463857 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3822463857
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.587179918
Short name T111
Test name
Test status
Simulation time 51380056 ps
CPU time 1.49 seconds
Started Apr 21 12:39:21 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 218036 kb
Host smart-8269117e-7d7e-45bf-83e7-686a01307d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587179918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.587179918
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2107410152
Short name T235
Test name
Test status
Simulation time 8774617065 ps
CPU time 27.52 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:53 PM PDT 24
Peak memory 204740 kb
Host smart-c22a7344-1d47-4ebe-b28d-6cebb6866dba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107410152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2107410152
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.719654651
Short name T216
Test name
Test status
Simulation time 40814531243 ps
CPU time 74.92 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:40:43 PM PDT 24
Peak memory 204812 kb
Host smart-ff5ef2da-62d1-42b2-b059-90066570692f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719654651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.719654651
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.561942007
Short name T242
Test name
Test status
Simulation time 472159112 ps
CPU time 2.45 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 204596 kb
Host smart-d1a07265-0fbb-42f0-86fe-5fbbc1641d39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561942007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.561942007
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.753202571
Short name T227
Test name
Test status
Simulation time 95120818 ps
CPU time 0.73 seconds
Started Apr 21 12:39:39 PM PDT 24
Finished Apr 21 12:39:40 PM PDT 24
Peak memory 204416 kb
Host smart-83c5607e-7d20-4c1c-8d66-35836e82ffba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753202571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.753202571
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4071353196
Short name T72
Test name
Test status
Simulation time 4157907192 ps
CPU time 13.46 seconds
Started Apr 21 12:39:42 PM PDT 24
Finished Apr 21 12:39:56 PM PDT 24
Peak memory 204736 kb
Host smart-adf94c8f-31be-4050-a6f5-8d18b0d7ed37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071353196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.4071353196
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4093423808
Short name T306
Test name
Test status
Simulation time 73571303 ps
CPU time 0.73 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 204492 kb
Host smart-f0837010-842a-41ff-a552-c5036f806345
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093423808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4093423808
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.346670789
Short name T272
Test name
Test status
Simulation time 73018457 ps
CPU time 0.7 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:25 PM PDT 24
Peak memory 204428 kb
Host smart-f9149278-3f87-42f7-a032-ef8270828752
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346670789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.346670789
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1891245932
Short name T291
Test name
Test status
Simulation time 47722909 ps
CPU time 0.66 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 204392 kb
Host smart-eb04a3dc-4a2e-4e65-8b2b-d5cfcf25a87e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891245932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1891245932
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.338591785
Short name T213
Test name
Test status
Simulation time 20493155 ps
CPU time 0.68 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204448 kb
Host smart-b381e515-fd59-41ba-aff1-fa6f033626d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338591785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.338591785
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3788753691
Short name T276
Test name
Test status
Simulation time 701091096 ps
CPU time 7.64 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 204784 kb
Host smart-7e9d7467-be81-495a-ad3a-f6727eccdde6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788753691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3788753691
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2135207422
Short name T93
Test name
Test status
Simulation time 457845984 ps
CPU time 4 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:24 PM PDT 24
Peak memory 213072 kb
Host smart-3e5a8702-e5bb-48e8-a9e9-3780555a773d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135207422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2135207422
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2159270515
Short name T127
Test name
Test status
Simulation time 902773297 ps
CPU time 16.86 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:33 PM PDT 24
Peak memory 221160 kb
Host smart-d1dd6bd4-e29f-4a97-9d2b-347a9b18b31f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159270515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2159270515
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.125100608
Short name T224
Test name
Test status
Simulation time 10705654878 ps
CPU time 20.59 seconds
Started Apr 21 12:39:45 PM PDT 24
Finished Apr 21 12:40:06 PM PDT 24
Peak memory 213056 kb
Host smart-3cc5379c-6b8a-4da6-8807-2d38904bbce4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125100608 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.125100608
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2034043133
Short name T279
Test name
Test status
Simulation time 10077700971 ps
CPU time 27.37 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:57 PM PDT 24
Peak memory 204996 kb
Host smart-8145c8c9-a362-481f-9f30-2352dc41d924
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034043133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2034043133
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3635736432
Short name T81
Test name
Test status
Simulation time 59390707 ps
CPU time 1.63 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 212988 kb
Host smart-37fd6859-b492-4608-aa1a-56783cc14a94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635736432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3635736432
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1558707278
Short name T180
Test name
Test status
Simulation time 138791123 ps
CPU time 2.06 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 217708 kb
Host smart-761ff6cc-d071-428b-8eaf-f6c159527b85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558707278 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1558707278
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.338120990
Short name T85
Test name
Test status
Simulation time 380081125 ps
CPU time 2.33 seconds
Started Apr 21 12:39:39 PM PDT 24
Finished Apr 21 12:39:42 PM PDT 24
Peak memory 218536 kb
Host smart-abf0929e-e589-4e1c-be6a-bd7adbd49235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338120990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.338120990
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3823674104
Short name T296
Test name
Test status
Simulation time 14527519610 ps
CPU time 15.07 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:52 PM PDT 24
Peak memory 204684 kb
Host smart-68d25e9a-d732-4821-97ac-9851f55decf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823674104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3823674104
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1949418578
Short name T220
Test name
Test status
Simulation time 42462160562 ps
CPU time 52.34 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:40:18 PM PDT 24
Peak memory 204852 kb
Host smart-0708a489-3005-4f28-861d-479174ceea49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949418578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.1949418578
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2049266301
Short name T97
Test name
Test status
Simulation time 333558200 ps
CPU time 1.21 seconds
Started Apr 21 12:39:35 PM PDT 24
Finished Apr 21 12:39:37 PM PDT 24
Peak memory 204744 kb
Host smart-9d43fa88-7abc-4015-8de5-01ef44d8b413
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049266301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2049266301
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4005528983
Short name T282
Test name
Test status
Simulation time 441996177 ps
CPU time 1.53 seconds
Started Apr 21 12:39:14 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 204532 kb
Host smart-95f40945-937e-472d-9b83-9d4175c1f8de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005528983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
005528983
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3999853497
Short name T207
Test name
Test status
Simulation time 134979204 ps
CPU time 0.82 seconds
Started Apr 21 12:39:39 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 204436 kb
Host smart-b890f149-63f6-4801-a236-432069df1bb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999853497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3999853497
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3794722836
Short name T236
Test name
Test status
Simulation time 383353000 ps
CPU time 1.71 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:26 PM PDT 24
Peak memory 204728 kb
Host smart-d54d9c9a-30d0-4b66-859f-755cf31ecd67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794722836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3794722836
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3959821771
Short name T278
Test name
Test status
Simulation time 210123978 ps
CPU time 0.94 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 204532 kb
Host smart-86228710-3d58-48c7-a4bc-8619ff56e3f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959821771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3959821771
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2131446614
Short name T293
Test name
Test status
Simulation time 43047470 ps
CPU time 0.74 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204440 kb
Host smart-f5b87a42-09cf-4ff8-980a-18ce42430de1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131446614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
131446614
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.961442702
Short name T178
Test name
Test status
Simulation time 20604019 ps
CPU time 0.71 seconds
Started Apr 21 12:39:48 PM PDT 24
Finished Apr 21 12:39:50 PM PDT 24
Peak memory 204428 kb
Host smart-6c2e2a41-47d6-4222-a1d9-24839c1db0e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961442702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.961442702
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3738683253
Short name T202
Test name
Test status
Simulation time 19761433 ps
CPU time 0.69 seconds
Started Apr 21 12:39:43 PM PDT 24
Finished Apr 21 12:39:44 PM PDT 24
Peak memory 204420 kb
Host smart-d51fae68-a408-4da0-ae98-b1e305201775
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738683253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3738683253
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2318683942
Short name T99
Test name
Test status
Simulation time 553681762 ps
CPU time 8.03 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 204720 kb
Host smart-0ac9fd1e-6394-4968-b0f8-61b682a04402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318683942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2318683942
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1027843707
Short name T208
Test name
Test status
Simulation time 23491721387 ps
CPU time 14.41 seconds
Started Apr 21 12:39:22 PM PDT 24
Finished Apr 21 12:39:37 PM PDT 24
Peak memory 215184 kb
Host smart-2de53052-e30f-409b-8a47-41795ee96d2b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027843707 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1027843707
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1076942257
Short name T265
Test name
Test status
Simulation time 198954254 ps
CPU time 2.96 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 213088 kb
Host smart-c8dd0bb5-9b83-4554-9945-e02fe0d764bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076942257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1076942257
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3808793859
Short name T131
Test name
Test status
Simulation time 811047534 ps
CPU time 8.28 seconds
Started Apr 21 12:39:23 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 213052 kb
Host smart-d6bb6b8c-deb3-4773-a914-4af8b01e6605
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808793859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3808793859
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3282647455
Short name T294
Test name
Test status
Simulation time 6364691840 ps
CPU time 4.56 seconds
Started Apr 21 12:39:21 PM PDT 24
Finished Apr 21 12:39:26 PM PDT 24
Peak memory 219104 kb
Host smart-71e58414-266e-4356-9cd0-ce3e59283139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282647455 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3282647455
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2914739658
Short name T70
Test name
Test status
Simulation time 1076325766 ps
CPU time 1.61 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 213012 kb
Host smart-51d16574-75cc-4ac8-8592-008abd6d8045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914739658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2914739658
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2786264037
Short name T184
Test name
Test status
Simulation time 541348191 ps
CPU time 1.54 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 204608 kb
Host smart-df3a13da-36fc-4e0b-b77c-8cbf7c01c255
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786264037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
786264037
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3436760121
Short name T226
Test name
Test status
Simulation time 49747890 ps
CPU time 0.84 seconds
Started Apr 21 12:39:49 PM PDT 24
Finished Apr 21 12:39:56 PM PDT 24
Peak memory 204440 kb
Host smart-56c66441-a94b-450b-ab1b-a6cf0a6aa320
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436760121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
436760121
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1009740123
Short name T114
Test name
Test status
Simulation time 153971097 ps
CPU time 3.43 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 204712 kb
Host smart-ff839eb7-e6ed-4ac4-a1e4-34015f490a41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009740123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1009740123
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3912357201
Short name T199
Test name
Test status
Simulation time 39703250 ps
CPU time 2.12 seconds
Started Apr 21 12:39:44 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 213048 kb
Host smart-0805fe0c-2471-455f-a53b-c2685e00fd47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912357201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3912357201
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3826576802
Short name T212
Test name
Test status
Simulation time 3298318637 ps
CPU time 18.75 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:56 PM PDT 24
Peak memory 221200 kb
Host smart-582c393c-34d5-4918-971e-5ab8fb45b098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826576802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3826576802
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2258121230
Short name T217
Test name
Test status
Simulation time 1646723704 ps
CPU time 4.09 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:24 PM PDT 24
Peak memory 218316 kb
Host smart-879b30e8-9cf4-452b-aa87-5431cfff3bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258121230 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2258121230
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1438442115
Short name T285
Test name
Test status
Simulation time 108782585 ps
CPU time 2.12 seconds
Started Apr 21 12:39:21 PM PDT 24
Finished Apr 21 12:39:24 PM PDT 24
Peak memory 218564 kb
Host smart-f0b046d7-43fe-4e05-89f5-eb60c27224fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438442115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1438442115
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1435046157
Short name T173
Test name
Test status
Simulation time 307894673 ps
CPU time 1.44 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:38 PM PDT 24
Peak memory 204596 kb
Host smart-a1b314c3-fa28-4516-b5d7-ef7ce8848df5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435046157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
435046157
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1816818626
Short name T240
Test name
Test status
Simulation time 56833741 ps
CPU time 0.74 seconds
Started Apr 21 12:39:52 PM PDT 24
Finished Apr 21 12:39:53 PM PDT 24
Peak memory 204440 kb
Host smart-20df8487-d63d-4029-83ec-decc54f3c508
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816818626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
816818626
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1922938525
Short name T88
Test name
Test status
Simulation time 91947619 ps
CPU time 3.74 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 204820 kb
Host smart-f44325c2-4760-433a-a5f3-e7105fac3b69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922938525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1922938525
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.942590310
Short name T243
Test name
Test status
Simulation time 414142782 ps
CPU time 3.21 seconds
Started Apr 21 12:39:31 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 212980 kb
Host smart-0b840937-3626-4c8c-8b5b-21bf8e4d0716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942590310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.942590310
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1141313979
Short name T91
Test name
Test status
Simulation time 1092027460 ps
CPU time 19.04 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:44 PM PDT 24
Peak memory 220996 kb
Host smart-ce901eeb-348d-4334-b2be-e248dbd97c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141313979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1141313979
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3410753609
Short name T197
Test name
Test status
Simulation time 2473859528 ps
CPU time 2.29 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:19 PM PDT 24
Peak memory 215072 kb
Host smart-d9693b99-a1a0-4299-b650-1644633bd244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410753609 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3410753609
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3513677396
Short name T106
Test name
Test status
Simulation time 49758559 ps
CPU time 1.46 seconds
Started Apr 21 12:39:25 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 217672 kb
Host smart-e17bcc13-e4a6-4666-beb9-3cbef0366101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513677396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3513677396
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.470440998
Short name T203
Test name
Test status
Simulation time 2067130369 ps
CPU time 6.94 seconds
Started Apr 21 12:39:34 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 204688 kb
Host smart-74cf2433-956c-4203-9fdc-987d396bb3cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470440998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.470440998
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1892288301
Short name T281
Test name
Test status
Simulation time 112313830 ps
CPU time 0.78 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:29 PM PDT 24
Peak memory 204400 kb
Host smart-cf38bcd2-8883-4ab7-aaf4-4cef4e62d3cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892288301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
892288301
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2399406041
Short name T295
Test name
Test status
Simulation time 145661910 ps
CPU time 6.76 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 204684 kb
Host smart-aeb6c7d9-87ed-4d0b-91b6-dd426144d0d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399406041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2399406041
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.87716550
Short name T287
Test name
Test status
Simulation time 399991731 ps
CPU time 2.85 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 213080 kb
Host smart-b8b82853-11d2-476e-b52d-6776fd644dac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87716550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.87716550
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2523491818
Short name T255
Test name
Test status
Simulation time 3291055805 ps
CPU time 19.39 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 213008 kb
Host smart-48f72c7f-331c-4ec4-a34a-8df7f6d7aded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523491818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2523491818
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.995177160
Short name T249
Test name
Test status
Simulation time 2184687089 ps
CPU time 4.66 seconds
Started Apr 21 12:39:40 PM PDT 24
Finished Apr 21 12:39:46 PM PDT 24
Peak memory 216704 kb
Host smart-82473079-31cc-4cc2-80d3-47801a46df67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995177160 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.995177160
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1100213359
Short name T304
Test name
Test status
Simulation time 137156644 ps
CPU time 2.16 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 212992 kb
Host smart-ac40b4da-c432-45d6-ada7-54d272293282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100213359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1100213359
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3434600584
Short name T223
Test name
Test status
Simulation time 197764162 ps
CPU time 1.18 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 204700 kb
Host smart-d6c0ddf8-fd4c-45f8-9c15-505f8b070113
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434600584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
434600584
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3149429724
Short name T277
Test name
Test status
Simulation time 35779123 ps
CPU time 0.71 seconds
Started Apr 21 12:39:39 PM PDT 24
Finished Apr 21 12:39:41 PM PDT 24
Peak memory 204416 kb
Host smart-8b2eb1bc-7bd1-45ed-9bc2-f8bf6c3438ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149429724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
149429724
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.172163574
Short name T262
Test name
Test status
Simulation time 2400274470 ps
CPU time 8.15 seconds
Started Apr 21 12:39:28 PM PDT 24
Finished Apr 21 12:39:37 PM PDT 24
Peak memory 204948 kb
Host smart-ce9cf802-fd25-489c-982c-82b3baf5f751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172163574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.172163574
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3679939950
Short name T67
Test name
Test status
Simulation time 12059337405 ps
CPU time 14.74 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:35 PM PDT 24
Peak memory 220320 kb
Host smart-9ba9ae20-8bd1-464b-aab7-11494b095853
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679939950 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3679939950
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4275006680
Short name T155
Test name
Test status
Simulation time 34201619 ps
CPU time 2.4 seconds
Started Apr 21 12:39:40 PM PDT 24
Finished Apr 21 12:39:43 PM PDT 24
Peak memory 213016 kb
Host smart-5b0c4260-7052-4256-8440-85dd2bc24fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275006680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4275006680
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3432773352
Short name T129
Test name
Test status
Simulation time 1120857120 ps
CPU time 9.73 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 221036 kb
Host smart-9c2547ba-c7c5-45ab-a27c-e09af6b50e96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432773352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3432773352
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1949139892
Short name T79
Test name
Test status
Simulation time 4459307459 ps
CPU time 3.54 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 216552 kb
Host smart-1aad5d15-a9fa-4bdb-98ed-bf7bfc424205
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949139892 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1949139892
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3046993623
Short name T87
Test name
Test status
Simulation time 198059597 ps
CPU time 2.32 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 218556 kb
Host smart-c8df2949-cddf-40d0-b765-6bb82e840bbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046993623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3046993623
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1231887613
Short name T191
Test name
Test status
Simulation time 1101872705 ps
CPU time 3.99 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 204700 kb
Host smart-4438bc75-13cf-42bd-8ec9-4c1fecdaacc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231887613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
231887613
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3479077564
Short name T175
Test name
Test status
Simulation time 56489573 ps
CPU time 0.72 seconds
Started Apr 21 12:39:27 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 204452 kb
Host smart-9803b4c5-87b6-4014-b888-1e3b4de98cab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479077564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
479077564
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4142295136
Short name T246
Test name
Test status
Simulation time 550207784 ps
CPU time 6.8 seconds
Started Apr 21 12:39:41 PM PDT 24
Finished Apr 21 12:39:49 PM PDT 24
Peak memory 204752 kb
Host smart-f7fba2b4-d578-4fd1-b818-13cef71e843f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142295136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.4142295136
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.47966315
Short name T206
Test name
Test status
Simulation time 158859516 ps
CPU time 3.33 seconds
Started Apr 21 12:39:31 PM PDT 24
Finished Apr 21 12:39:35 PM PDT 24
Peak memory 213116 kb
Host smart-63221ca9-7ef7-4605-b097-66c4870b7994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47966315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.47966315
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.493046307
Short name T90
Test name
Test status
Simulation time 1122997219 ps
CPU time 10.65 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:38 PM PDT 24
Peak memory 221064 kb
Host smart-c41ba337-2808-44bd-aa71-d666ffaff1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493046307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.493046307
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3127979073
Short name T26
Test name
Test status
Simulation time 51476199 ps
CPU time 0.8 seconds
Started Apr 21 12:40:43 PM PDT 24
Finished Apr 21 12:40:44 PM PDT 24
Peak memory 205068 kb
Host smart-f814cda8-d5ae-4d08-9ec9-3f3eddb88254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127979073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3127979073
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3062687463
Short name T10
Test name
Test status
Simulation time 13773939467 ps
CPU time 5.88 seconds
Started Apr 21 12:40:40 PM PDT 24
Finished Apr 21 12:40:46 PM PDT 24
Peak memory 205368 kb
Host smart-72b96b96-5aa8-475f-a7ea-68cbdfed875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062687463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3062687463
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1160039206
Short name T162
Test name
Test status
Simulation time 153719113 ps
CPU time 0.67 seconds
Started Apr 21 12:40:48 PM PDT 24
Finished Apr 21 12:40:49 PM PDT 24
Peak memory 204968 kb
Host smart-412ca9af-dbf7-4464-9046-d11879444221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160039206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1160039206
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1026094016
Short name T166
Test name
Test status
Simulation time 62254770 ps
CPU time 0.92 seconds
Started Apr 21 12:40:49 PM PDT 24
Finished Apr 21 12:40:51 PM PDT 24
Peak memory 204840 kb
Host smart-b2c42783-5ea7-44ae-aaa5-5a392035f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026094016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1026094016
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4141180352
Short name T33
Test name
Test status
Simulation time 139495600 ps
CPU time 0.84 seconds
Started Apr 21 12:40:31 PM PDT 24
Finished Apr 21 12:40:33 PM PDT 24
Peak memory 204908 kb
Host smart-99aa5d5a-90a2-4059-b565-9ef6e97863bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141180352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4141180352
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1680031922
Short name T64
Test name
Test status
Simulation time 333413726 ps
CPU time 1.09 seconds
Started Apr 21 12:40:44 PM PDT 24
Finished Apr 21 12:40:45 PM PDT 24
Peak memory 205136 kb
Host smart-edbb489f-2796-47c0-9c12-2279217f42ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680031922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1680031922
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1892299964
Short name T134
Test name
Test status
Simulation time 214771401 ps
CPU time 0.87 seconds
Started Apr 21 12:40:42 PM PDT 24
Finished Apr 21 12:40:43 PM PDT 24
Peak memory 204984 kb
Host smart-a5dae330-b957-4df5-92c6-c52b5c6c965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892299964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1892299964
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3155999688
Short name T80
Test name
Test status
Simulation time 435814714 ps
CPU time 1.43 seconds
Started Apr 21 12:40:41 PM PDT 24
Finished Apr 21 12:40:43 PM PDT 24
Peak memory 205452 kb
Host smart-4059fdfd-971a-4eee-9f84-2dcd2a580494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155999688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3155999688
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3397413237
Short name T38
Test name
Test status
Simulation time 220774384 ps
CPU time 1.06 seconds
Started Apr 21 12:40:39 PM PDT 24
Finished Apr 21 12:40:41 PM PDT 24
Peak memory 229240 kb
Host smart-74ae9d4c-414a-46e0-858c-03eb188f5e8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397413237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3397413237
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2563138163
Short name T22
Test name
Test status
Simulation time 353093988 ps
CPU time 1.29 seconds
Started Apr 21 12:40:39 PM PDT 24
Finished Apr 21 12:40:41 PM PDT 24
Peak memory 205028 kb
Host smart-9b3cdd5d-46ee-44bb-93bc-a9a0c8ff48cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563138163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2563138163
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4287776132
Short name T170
Test name
Test status
Simulation time 51925140 ps
CPU time 0.71 seconds
Started Apr 21 12:40:42 PM PDT 24
Finished Apr 21 12:40:43 PM PDT 24
Peak memory 205024 kb
Host smart-6c3e2c52-7116-4cc9-a842-b2f7bfd64ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287776132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4287776132
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3791767165
Short name T4
Test name
Test status
Simulation time 4881939111 ps
CPU time 6.96 seconds
Started Apr 21 12:40:33 PM PDT 24
Finished Apr 21 12:40:40 PM PDT 24
Peak memory 205376 kb
Host smart-a8ca1acc-58e5-4244-811e-1e771e863da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791767165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3791767165
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.82360188
Short name T20
Test name
Test status
Simulation time 449698918 ps
CPU time 1.79 seconds
Started Apr 21 12:40:46 PM PDT 24
Finished Apr 21 12:40:49 PM PDT 24
Peak memory 205076 kb
Host smart-853a957c-d241-4875-922f-b21965507a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82360188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.82360188
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3539302763
Short name T8
Test name
Test status
Simulation time 332810800 ps
CPU time 0.97 seconds
Started Apr 21 12:40:45 PM PDT 24
Finished Apr 21 12:40:46 PM PDT 24
Peak memory 204912 kb
Host smart-1fd75a55-7d93-4205-a8d6-f98f2e4cc1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539302763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3539302763
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.616329015
Short name T6
Test name
Test status
Simulation time 1122199491 ps
CPU time 4.66 seconds
Started Apr 21 12:40:45 PM PDT 24
Finished Apr 21 12:40:50 PM PDT 24
Peak memory 205168 kb
Host smart-fa35e9af-ca80-433b-af75-ddf71e0c1829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616329015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.616329015
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3995223356
Short name T16
Test name
Test status
Simulation time 55661945 ps
CPU time 0.7 seconds
Started Apr 21 12:40:40 PM PDT 24
Finished Apr 21 12:40:42 PM PDT 24
Peak memory 205028 kb
Host smart-c378c7b1-2166-4f66-8de1-4fc0fe670346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995223356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3995223356
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1449193126
Short name T35
Test name
Test status
Simulation time 126901186 ps
CPU time 0.79 seconds
Started Apr 21 12:40:55 PM PDT 24
Finished Apr 21 12:40:57 PM PDT 24
Peak memory 204816 kb
Host smart-6bd14633-bd21-489b-b5f6-33ed17a0bbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449193126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1449193126
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.46164589
Short name T42
Test name
Test status
Simulation time 317438514 ps
CPU time 1.8 seconds
Started Apr 21 12:40:44 PM PDT 24
Finished Apr 21 12:40:47 PM PDT 24
Peak memory 205124 kb
Host smart-da059a8a-3892-4e58-9c0e-b12701d20d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46164589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.46164589
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3719787329
Short name T1
Test name
Test status
Simulation time 351279600 ps
CPU time 1.04 seconds
Started Apr 21 12:41:02 PM PDT 24
Finished Apr 21 12:41:04 PM PDT 24
Peak memory 204796 kb
Host smart-c8b013a5-d6bf-41a5-b121-839bb2cf3e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719787329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3719787329
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3721216941
Short name T65
Test name
Test status
Simulation time 269725831 ps
CPU time 0.98 seconds
Started Apr 21 12:40:45 PM PDT 24
Finished Apr 21 12:40:47 PM PDT 24
Peak memory 205092 kb
Host smart-fcd28fc2-2073-4c5a-87ec-de82bf4e8db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721216941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3721216941
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3011561088
Short name T133
Test name
Test status
Simulation time 46501085 ps
CPU time 0.75 seconds
Started Apr 21 12:40:44 PM PDT 24
Finished Apr 21 12:40:46 PM PDT 24
Peak memory 204884 kb
Host smart-2e65d6e0-0c6f-4237-bccc-5204b561891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011561088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3011561088
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1207872736
Short name T2
Test name
Test status
Simulation time 269471292 ps
CPU time 1.14 seconds
Started Apr 21 12:41:02 PM PDT 24
Finished Apr 21 12:41:04 PM PDT 24
Peak memory 205032 kb
Host smart-e7ac058b-047c-4a0d-9141-bccbf50c90e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207872736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1207872736
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2844966214
Short name T17
Test name
Test status
Simulation time 1418494225 ps
CPU time 3.13 seconds
Started Apr 21 12:40:45 PM PDT 24
Finished Apr 21 12:40:48 PM PDT 24
Peak memory 205240 kb
Host smart-03218d16-3dbb-4cbb-b575-cc3827d7eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844966214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2844966214
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2103052261
Short name T19
Test name
Test status
Simulation time 150401000 ps
CPU time 1.19 seconds
Started Apr 21 12:40:56 PM PDT 24
Finished Apr 21 12:40:57 PM PDT 24
Peak memory 205148 kb
Host smart-1a937d73-b677-4fd9-8f02-53578d167569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103052261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2103052261
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1648874467
Short name T25
Test name
Test status
Simulation time 70414484 ps
CPU time 0.93 seconds
Started Apr 21 12:40:46 PM PDT 24
Finished Apr 21 12:40:48 PM PDT 24
Peak memory 205044 kb
Host smart-3e48ba9d-ed4a-4380-a7f4-4a0a9199961a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648874467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1648874467
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2279970819
Short name T13
Test name
Test status
Simulation time 64457146 ps
CPU time 0.83 seconds
Started Apr 21 12:40:44 PM PDT 24
Finished Apr 21 12:40:46 PM PDT 24
Peak memory 213240 kb
Host smart-7da10a83-19f1-4c3a-850f-7fccab473f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279970819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2279970819
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3922960125
Short name T56
Test name
Test status
Simulation time 150828878 ps
CPU time 1.33 seconds
Started Apr 21 12:41:01 PM PDT 24
Finished Apr 21 12:41:02 PM PDT 24
Peak memory 229172 kb
Host smart-b2e8bd7b-d997-4cff-ba54-8f6c7a90d430
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922960125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3922960125
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2781538331
Short name T68
Test name
Test status
Simulation time 877209606 ps
CPU time 1.61 seconds
Started Apr 21 12:40:46 PM PDT 24
Finished Apr 21 12:40:48 PM PDT 24
Peak memory 205104 kb
Host smart-39a2269e-424b-4ef6-a325-9cd99874a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781538331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2781538331
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.104175138
Short name T157
Test name
Test status
Simulation time 30263014 ps
CPU time 0.79 seconds
Started Apr 21 12:41:02 PM PDT 24
Finished Apr 21 12:41:09 PM PDT 24
Peak memory 204944 kb
Host smart-5f07dfb3-3757-4ee3-b734-3230ffe989cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104175138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.104175138
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3781659769
Short name T144
Test name
Test status
Simulation time 64209951 ps
CPU time 0.71 seconds
Started Apr 21 12:41:03 PM PDT 24
Finished Apr 21 12:41:04 PM PDT 24
Peak memory 205036 kb
Host smart-1de0eaf0-5dd6-4e5c-9efa-c641e9887682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781659769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3781659769
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3912931627
Short name T94
Test name
Test status
Simulation time 1038200610 ps
CPU time 1.79 seconds
Started Apr 21 12:41:07 PM PDT 24
Finished Apr 21 12:41:09 PM PDT 24
Peak memory 205228 kb
Host smart-05206bc6-d86d-45c7-b7c8-46a5d86444d2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912931627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3912931627
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1716353959
Short name T140
Test name
Test status
Simulation time 37439540 ps
CPU time 0.78 seconds
Started Apr 21 12:41:17 PM PDT 24
Finished Apr 21 12:41:18 PM PDT 24
Peak memory 204964 kb
Host smart-dc84f7ce-55dc-4a49-828d-5643d206da13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716353959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1716353959
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3344552541
Short name T9
Test name
Test status
Simulation time 4071233568 ps
CPU time 9.5 seconds
Started Apr 21 12:41:08 PM PDT 24
Finished Apr 21 12:41:18 PM PDT 24
Peak memory 205372 kb
Host smart-320f5b6b-23e6-40df-8b29-50392288158f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344552541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3344552541
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2094502069
Short name T40
Test name
Test status
Simulation time 45471363 ps
CPU time 0.68 seconds
Started Apr 21 12:41:03 PM PDT 24
Finished Apr 21 12:41:05 PM PDT 24
Peak memory 204940 kb
Host smart-e0bccde4-c3a7-470e-865d-873bf1467583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094502069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2094502069
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2665121684
Short name T145
Test name
Test status
Simulation time 15928380 ps
CPU time 0.7 seconds
Started Apr 21 12:41:34 PM PDT 24
Finished Apr 21 12:41:35 PM PDT 24
Peak memory 204960 kb
Host smart-e7b8f0d5-59e1-4d34-b555-64f3865429da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665121684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2665121684
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1856408067
Short name T139
Test name
Test status
Simulation time 52209609 ps
CPU time 0.71 seconds
Started Apr 21 12:41:06 PM PDT 24
Finished Apr 21 12:41:07 PM PDT 24
Peak memory 205012 kb
Host smart-aa3c6a9a-570a-4959-8fbf-b372ebfb870c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856408067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1856408067
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1182063827
Short name T36
Test name
Test status
Simulation time 4033830162 ps
CPU time 6.48 seconds
Started Apr 21 12:41:15 PM PDT 24
Finished Apr 21 12:41:22 PM PDT 24
Peak memory 205460 kb
Host smart-c2697dd4-a182-4c9e-a28e-1b8ce114db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182063827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1182063827
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2855607596
Short name T29
Test name
Test status
Simulation time 2474392350 ps
CPU time 4.43 seconds
Started Apr 21 12:41:52 PM PDT 24
Finished Apr 21 12:41:58 PM PDT 24
Peak memory 205476 kb
Host smart-3a3bd398-44dd-4cd1-ac46-0df1640a3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855607596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2855607596
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2484900302
Short name T153
Test name
Test status
Simulation time 42211173 ps
CPU time 0.74 seconds
Started Apr 21 12:41:22 PM PDT 24
Finished Apr 21 12:41:24 PM PDT 24
Peak memory 204968 kb
Host smart-d30821a8-8b23-4b32-a789-0b4d29c12d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484900302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2484900302
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1958619282
Short name T63
Test name
Test status
Simulation time 53116169 ps
CPU time 0.72 seconds
Started Apr 21 12:41:24 PM PDT 24
Finished Apr 21 12:41:26 PM PDT 24
Peak memory 204952 kb
Host smart-feab3934-7cb5-4138-8270-a935781aee1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958619282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1958619282
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3176133546
Short name T61
Test name
Test status
Simulation time 962217823 ps
CPU time 2.55 seconds
Started Apr 21 12:41:08 PM PDT 24
Finished Apr 21 12:41:11 PM PDT 24
Peak memory 205296 kb
Host smart-f19ee290-e690-4101-b5dc-d287364553ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176133546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3176133546
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1188444613
Short name T135
Test name
Test status
Simulation time 18558358 ps
CPU time 0.67 seconds
Started Apr 21 12:41:19 PM PDT 24
Finished Apr 21 12:41:20 PM PDT 24
Peak memory 204944 kb
Host smart-dcff5545-639b-446f-bb01-502dc94a51d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188444613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1188444613
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.71938534
Short name T5
Test name
Test status
Simulation time 45691541 ps
CPU time 0.7 seconds
Started Apr 21 12:41:02 PM PDT 24
Finished Apr 21 12:41:04 PM PDT 24
Peak memory 204948 kb
Host smart-e82ce79a-c855-4c18-b810-d8c71c1d4a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71938534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.71938534
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1933180636
Short name T159
Test name
Test status
Simulation time 73961795 ps
CPU time 0.87 seconds
Started Apr 21 12:40:56 PM PDT 24
Finished Apr 21 12:40:57 PM PDT 24
Peak memory 204864 kb
Host smart-263344e8-7559-479d-8246-d8ddd2e628b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933180636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1933180636
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1004709468
Short name T165
Test name
Test status
Simulation time 37536535 ps
CPU time 0.77 seconds
Started Apr 21 12:41:10 PM PDT 24
Finished Apr 21 12:41:11 PM PDT 24
Peak memory 204960 kb
Host smart-023f11d3-df41-43de-9f7d-a2a744cb73de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004709468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1004709468
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3352619736
Short name T156
Test name
Test status
Simulation time 30571140 ps
CPU time 0.73 seconds
Started Apr 21 12:41:32 PM PDT 24
Finished Apr 21 12:41:33 PM PDT 24
Peak memory 204956 kb
Host smart-1a982b19-91ae-4978-b7c4-bb9b4fde8d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352619736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3352619736
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3126880784
Short name T164
Test name
Test status
Simulation time 50918557 ps
CPU time 0.69 seconds
Started Apr 21 12:41:19 PM PDT 24
Finished Apr 21 12:41:21 PM PDT 24
Peak memory 204976 kb
Host smart-ae8e9624-1f84-4e4d-9870-0eb9187f79c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126880784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3126880784
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.478908912
Short name T49
Test name
Test status
Simulation time 22408275 ps
CPU time 0.76 seconds
Started Apr 21 12:41:07 PM PDT 24
Finished Apr 21 12:41:08 PM PDT 24
Peak memory 204956 kb
Host smart-ea8f2e7e-dd77-4327-992d-d32bc2407487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478908912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.478908912
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3367786028
Short name T54
Test name
Test status
Simulation time 30991686 ps
CPU time 0.71 seconds
Started Apr 21 12:41:24 PM PDT 24
Finished Apr 21 12:41:25 PM PDT 24
Peak memory 204960 kb
Host smart-0b6b99d5-61ed-4b47-a314-ee319c54e161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367786028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3367786028
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2609852748
Short name T57
Test name
Test status
Simulation time 17315666 ps
CPU time 0.7 seconds
Started Apr 21 12:41:12 PM PDT 24
Finished Apr 21 12:41:13 PM PDT 24
Peak memory 205036 kb
Host smart-db6b51e8-4d84-4df7-a073-ce5857bef32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609852748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2609852748
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3565888104
Short name T52
Test name
Test status
Simulation time 188498957 ps
CPU time 0.74 seconds
Started Apr 21 12:41:25 PM PDT 24
Finished Apr 21 12:41:26 PM PDT 24
Peak memory 204976 kb
Host smart-642caee2-a44a-40a5-8658-dbfe243f5105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565888104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3565888104
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.82721742
Short name T53
Test name
Test status
Simulation time 19578596 ps
CPU time 0.74 seconds
Started Apr 21 12:41:25 PM PDT 24
Finished Apr 21 12:41:27 PM PDT 24
Peak memory 204948 kb
Host smart-36ad9499-6d44-4bfc-b068-414cb467cb3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82721742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.82721742
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3433187301
Short name T137
Test name
Test status
Simulation time 22823901 ps
CPU time 0.72 seconds
Started Apr 21 12:41:20 PM PDT 24
Finished Apr 21 12:41:21 PM PDT 24
Peak memory 204984 kb
Host smart-e86c7315-949e-41a5-8d04-3d120e1b15d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433187301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3433187301
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1878671338
Short name T41
Test name
Test status
Simulation time 24345959 ps
CPU time 0.74 seconds
Started Apr 21 12:41:29 PM PDT 24
Finished Apr 21 12:41:30 PM PDT 24
Peak memory 205020 kb
Host smart-9d0adb2d-a045-4d0f-a188-a082abce5de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878671338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1878671338
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3564381708
Short name T150
Test name
Test status
Simulation time 31955022 ps
CPU time 0.8 seconds
Started Apr 21 12:40:50 PM PDT 24
Finished Apr 21 12:40:52 PM PDT 24
Peak memory 204952 kb
Host smart-2e3063da-7d31-4ac1-99bb-5d27eaf737e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564381708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3564381708
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3875480896
Short name T169
Test name
Test status
Simulation time 100244701 ps
CPU time 0.83 seconds
Started Apr 21 12:40:51 PM PDT 24
Finished Apr 21 12:40:52 PM PDT 24
Peak memory 204840 kb
Host smart-6d385346-56ee-4275-977a-ee4f94cd7498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875480896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3875480896
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2347634471
Short name T37
Test name
Test status
Simulation time 189753488 ps
CPU time 1.04 seconds
Started Apr 21 12:41:03 PM PDT 24
Finished Apr 21 12:41:05 PM PDT 24
Peak memory 229424 kb
Host smart-112e8723-3063-4d4f-9b56-5bd49a954d31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347634471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2347634471
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3040338952
Short name T147
Test name
Test status
Simulation time 47185345 ps
CPU time 0.73 seconds
Started Apr 21 12:41:22 PM PDT 24
Finished Apr 21 12:41:28 PM PDT 24
Peak memory 204992 kb
Host smart-f5468c2c-2f7f-4286-9895-6bc1d268eaec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040338952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3040338952
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3864245117
Short name T158
Test name
Test status
Simulation time 18390358 ps
CPU time 0.72 seconds
Started Apr 21 12:41:19 PM PDT 24
Finished Apr 21 12:41:20 PM PDT 24
Peak memory 205008 kb
Host smart-1ec29cf8-c104-4396-8f5c-cdd5f1a88b5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864245117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3864245117
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.675775034
Short name T152
Test name
Test status
Simulation time 67057197 ps
CPU time 0.7 seconds
Started Apr 21 12:41:41 PM PDT 24
Finished Apr 21 12:41:42 PM PDT 24
Peak memory 204952 kb
Host smart-4ae095d3-be1a-462e-adb8-fc2c90c48261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675775034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.675775034
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.435054747
Short name T149
Test name
Test status
Simulation time 56865856 ps
CPU time 0.7 seconds
Started Apr 21 12:41:33 PM PDT 24
Finished Apr 21 12:41:34 PM PDT 24
Peak memory 204944 kb
Host smart-dffa62c2-a633-47ca-8637-4a6dba104ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435054747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.435054747
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.330845736
Short name T163
Test name
Test status
Simulation time 31157863 ps
CPU time 0.68 seconds
Started Apr 21 12:41:12 PM PDT 24
Finished Apr 21 12:41:13 PM PDT 24
Peak memory 204936 kb
Host smart-ef3027e2-be06-4dfd-9c55-1b12a5155c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330845736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.330845736
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3563464568
Short name T160
Test name
Test status
Simulation time 21064590 ps
CPU time 0.74 seconds
Started Apr 21 12:41:08 PM PDT 24
Finished Apr 21 12:41:09 PM PDT 24
Peak memory 204932 kb
Host smart-a72a6ca7-7a89-420e-b7d3-ebd3e68cfee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563464568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3563464568
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1916319140
Short name T136
Test name
Test status
Simulation time 21963076 ps
CPU time 0.73 seconds
Started Apr 21 12:41:23 PM PDT 24
Finished Apr 21 12:41:24 PM PDT 24
Peak memory 205028 kb
Host smart-d77b90a5-2306-4983-9712-9d5422788293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916319140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1916319140
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2546346507
Short name T142
Test name
Test status
Simulation time 41697176 ps
CPU time 0.7 seconds
Started Apr 21 12:41:20 PM PDT 24
Finished Apr 21 12:41:21 PM PDT 24
Peak memory 205240 kb
Host smart-032b84d7-4687-434a-a7d8-562d353cff07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546346507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2546346507
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.337840321
Short name T121
Test name
Test status
Simulation time 41373521 ps
CPU time 0.76 seconds
Started Apr 21 12:41:14 PM PDT 24
Finished Apr 21 12:41:15 PM PDT 24
Peak memory 204956 kb
Host smart-2de6cc4a-378e-4417-bc48-b67ffaab3312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337840321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.337840321
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1072358618
Short name T154
Test name
Test status
Simulation time 32351515 ps
CPU time 0.75 seconds
Started Apr 21 12:41:36 PM PDT 24
Finished Apr 21 12:41:37 PM PDT 24
Peak memory 204964 kb
Host smart-d28fefa1-8271-49d8-a888-b1d912e22062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072358618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1072358618
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1947034946
Short name T58
Test name
Test status
Simulation time 20200250 ps
CPU time 0.78 seconds
Started Apr 21 12:41:06 PM PDT 24
Finished Apr 21 12:41:08 PM PDT 24
Peak memory 204980 kb
Host smart-fc2c8a16-f87c-4754-b4ee-1ad9e6c6bf2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947034946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1947034946
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.658161961
Short name T30
Test name
Test status
Simulation time 5294170836 ps
CPU time 5.22 seconds
Started Apr 21 12:40:46 PM PDT 24
Finished Apr 21 12:40:52 PM PDT 24
Peak memory 215280 kb
Host smart-c6130c07-32de-4e0c-a548-675f209c65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658161961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.658161961
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1266031352
Short name T34
Test name
Test status
Simulation time 50056232 ps
CPU time 0.74 seconds
Started Apr 21 12:40:55 PM PDT 24
Finished Apr 21 12:40:56 PM PDT 24
Peak memory 204824 kb
Host smart-bccfc46e-5944-4972-8c4b-c219a0f3d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266031352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1266031352
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.587328941
Short name T39
Test name
Test status
Simulation time 190030985 ps
CPU time 1.66 seconds
Started Apr 21 12:41:02 PM PDT 24
Finished Apr 21 12:41:05 PM PDT 24
Peak memory 229188 kb
Host smart-f6f9e0d7-b9c2-47bc-a3a5-f88539c0667d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587328941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.587328941
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.4253742749
Short name T148
Test name
Test status
Simulation time 44656240 ps
CPU time 0.7 seconds
Started Apr 21 12:41:32 PM PDT 24
Finished Apr 21 12:41:34 PM PDT 24
Peak memory 205056 kb
Host smart-ad637b85-b23e-403c-87b0-e5e7ae8ae37d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253742749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4253742749
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2741889051
Short name T138
Test name
Test status
Simulation time 55771565 ps
CPU time 0.72 seconds
Started Apr 21 12:41:27 PM PDT 24
Finished Apr 21 12:41:28 PM PDT 24
Peak memory 205040 kb
Host smart-6f32bd8a-b2d3-4b80-b46c-490add345cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741889051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2741889051
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.329755747
Short name T44
Test name
Test status
Simulation time 57764887 ps
CPU time 0.7 seconds
Started Apr 21 12:41:05 PM PDT 24
Finished Apr 21 12:41:06 PM PDT 24
Peak memory 205028 kb
Host smart-d30d580e-d45c-4e05-8e66-5c0f55b3d636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329755747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.329755747
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1536139816
Short name T146
Test name
Test status
Simulation time 24671617 ps
CPU time 0.74 seconds
Started Apr 21 12:41:33 PM PDT 24
Finished Apr 21 12:41:34 PM PDT 24
Peak memory 204960 kb
Host smart-096f43f0-bc13-40fb-aadc-fb59d9e890b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536139816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1536139816
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3182643117
Short name T151
Test name
Test status
Simulation time 27684568 ps
CPU time 0.7 seconds
Started Apr 21 12:41:18 PM PDT 24
Finished Apr 21 12:41:19 PM PDT 24
Peak memory 204956 kb
Host smart-df43f94f-575a-4f7b-b9da-0962bc6def9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182643117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3182643117
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3315036669
Short name T168
Test name
Test status
Simulation time 102520785 ps
CPU time 0.73 seconds
Started Apr 21 12:41:28 PM PDT 24
Finished Apr 21 12:41:30 PM PDT 24
Peak memory 204952 kb
Host smart-0246ca36-de40-4312-a1ee-a610f0bc58f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315036669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3315036669
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.822271548
Short name T141
Test name
Test status
Simulation time 22320781 ps
CPU time 0.71 seconds
Started Apr 21 12:41:18 PM PDT 24
Finished Apr 21 12:41:19 PM PDT 24
Peak memory 204976 kb
Host smart-936b99db-4f1c-480b-8628-f6d070813db6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822271548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.822271548
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1366797265
Short name T143
Test name
Test status
Simulation time 57913063 ps
CPU time 0.7 seconds
Started Apr 21 12:41:10 PM PDT 24
Finished Apr 21 12:41:11 PM PDT 24
Peak memory 204960 kb
Host smart-8026b8b5-42a2-4fa4-98c6-d67830ecd427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366797265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1366797265
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2145154278
Short name T43
Test name
Test status
Simulation time 69366350 ps
CPU time 0.7 seconds
Started Apr 21 12:41:14 PM PDT 24
Finished Apr 21 12:41:15 PM PDT 24
Peak memory 205032 kb
Host smart-dfb67508-d584-45ac-8583-2f8ddb8fc5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145154278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2145154278
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1342683813
Short name T59
Test name
Test status
Simulation time 26659395 ps
CPU time 0.73 seconds
Started Apr 21 12:40:42 PM PDT 24
Finished Apr 21 12:40:43 PM PDT 24
Peak memory 204940 kb
Host smart-932c3d99-2274-47d2-8178-2bffe673d0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342683813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1342683813
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1525052355
Short name T51
Test name
Test status
Simulation time 26408227 ps
CPU time 0.74 seconds
Started Apr 21 12:40:49 PM PDT 24
Finished Apr 21 12:40:50 PM PDT 24
Peak memory 205008 kb
Host smart-221371bd-7408-41fb-a1d1-27c1e047f0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525052355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1525052355
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.4011605870
Short name T161
Test name
Test status
Simulation time 45096633 ps
CPU time 0.7 seconds
Started Apr 21 12:41:03 PM PDT 24
Finished Apr 21 12:41:04 PM PDT 24
Peak memory 204932 kb
Host smart-1f053827-b9a6-4911-8a21-e9a56c57d640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011605870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4011605870
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.176836237
Short name T167
Test name
Test status
Simulation time 53511247 ps
CPU time 0.7 seconds
Started Apr 21 12:41:00 PM PDT 24
Finished Apr 21 12:41:01 PM PDT 24
Peak memory 204984 kb
Host smart-65cb39df-c17b-4403-904a-988effe09e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176836237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.176836237
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.335790824
Short name T31
Test name
Test status
Simulation time 567394154 ps
CPU time 2.07 seconds
Started Apr 21 12:40:58 PM PDT 24
Finished Apr 21 12:41:01 PM PDT 24
Peak memory 205340 kb
Host smart-c13eb69e-6a10-4471-9173-3ef793a36977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335790824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.335790824
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1155862093
Short name T50
Test name
Test status
Simulation time 52670547 ps
CPU time 0.7 seconds
Started Apr 21 12:41:02 PM PDT 24
Finished Apr 21 12:41:03 PM PDT 24
Peak memory 205008 kb
Host smart-a0a8e42e-65f5-469d-a749-cc68b4b59c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155862093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1155862093
Directory /workspace/9.rv_dm_alert_test/latest
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