Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	213822	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	540797	1		T2	2		T6	8		T7	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	495419	1		T6	10		T7	8		T20	10
values[0x0]	127927	1		T2	2		T4	4		T7	1
values[0x1]	131273	1		T4	3		T6	1		T60	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	163171	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	591448	1		T2	2		T6	9		T7	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3024	1		T27	1		T75	2		T43	1
valid_sources[0x01]	2764	1		T17	3		T69	1		T75	3
valid_sources[0x02]	2790	1		T42	2		T69	3		T43	1
valid_sources[0x03]	2858	1		T4	1		T41	5		T42	11
valid_sources[0x04]	3184	1		T17	1		T28	1		T75	4
valid_sources[0x05]	2679	1		T17	2		T43	2		T65	3
valid_sources[0x06]	2972	1		T42	1		T69	3		T75	1
valid_sources[0x07]	3088	1		T44	7		T69	1		T75	1
valid_sources[0x08]	3297	1		T69	1		T75	1		T43	2
valid_sources[0x09]	3048	1		T23	5		T44	1		T42	2
valid_sources[0x0a]	3191	1		T69	1		T43	3		T76	275
valid_sources[0x0b]	2910	1		T42	5		T69	6		T43	1
valid_sources[0x0c]	2676	1		T42	6		T75	3		T43	1
valid_sources[0x0d]	3157	1		T23	2		T27	1		T16	1
valid_sources[0x0e]	2664	1		T28	1		T44	2		T42	4
valid_sources[0x0f]	2627	1		T44	2		T42	2		T69	1
valid_sources[0x10]	2831	1		T42	9		T75	2		T43	4
valid_sources[0x11]	2725	1		T75	1		T43	4		T81	11
valid_sources[0x12]	2792	1		T42	1		T75	4		T43	3
valid_sources[0x13]	2643	1		T42	1		T43	1		T81	6
valid_sources[0x14]	3092	1		T69	4		T43	5		T81	1
valid_sources[0x15]	2674	1		T69	3		T75	5		T43	2
valid_sources[0x16]	2860	1		T17	1		T69	2		T75	4
valid_sources[0x17]	2912	1		T41	210		T69	1		T75	4
valid_sources[0x18]	2831	1		T17	3		T69	2		T43	7
valid_sources[0x19]	2894	1		T43	1		T81	3		T77	17
valid_sources[0x1a]	2993	1		T44	1		T69	1		T77	9
valid_sources[0x1b]	2821	1		T17	4		T44	1		T42	1
valid_sources[0x1c]	4337	1		T28	1		T41	172		T42	1
valid_sources[0x1d]	2662	1		T69	1		T75	1		T43	2
valid_sources[0x1e]	2734	1		T42	2		T43	4		T77	7
valid_sources[0x1f]	2739	1		T23	3		T42	3		T69	5
valid_sources[0x20]	3078	1		T43	4		T81	3		T76	18
valid_sources[0x21]	3448	1		T41	115		T44	1		T81	2
valid_sources[0x22]	2767	1		T42	7		T69	3		T75	1
valid_sources[0x23]	3631	1		T41	824		T42	4		T69	1
valid_sources[0x24]	2896	1		T42	3		T69	2		T75	4
valid_sources[0x25]	2629	1		T42	2		T69	4		T75	1
valid_sources[0x26]	2912	1		T43	1		T81	6		T78	12
valid_sources[0x27]	2955	1		T26	3		T42	8		T43	3
valid_sources[0x28]	2931	1		T27	1		T42	1		T75	1
valid_sources[0x29]	2739	1		T69	3		T75	4		T43	7
valid_sources[0x2a]	2833	1		T69	2		T75	6		T43	3
valid_sources[0x2b]	3005	1		T75	2		T43	1		T81	1
valid_sources[0x2c]	3049	1		T17	2		T42	9		T43	1
valid_sources[0x2d]	2650	1		T17	1		T42	1		T43	4
valid_sources[0x2e]	3064	1		T75	1		T43	1		T81	21
valid_sources[0x2f]	2773	1		T42	2		T43	3		T81	1
valid_sources[0x30]	2998	1		T42	1		T69	1		T43	5
valid_sources[0x31]	3133	1		T75	1		T43	1		T77	3
valid_sources[0x32]	3142	1		T16	1		T42	2		T69	1
valid_sources[0x33]	2994	1		T41	33		T42	3		T69	2
valid_sources[0x34]	2774	1		T42	4		T69	2		T43	2
valid_sources[0x35]	2892	1		T42	1		T69	1		T75	1
valid_sources[0x36]	3347	1		T60	4		T20	1		T23	1
valid_sources[0x37]	3022	1		T17	5		T43	2		T81	2
valid_sources[0x38]	3027	1		T42	12		T69	5		T43	1
valid_sources[0x39]	3098	1		T42	2		T43	7		T81	1
valid_sources[0x3a]	2745	1		T42	1		T75	1		T43	1
valid_sources[0x3b]	2707	1		T22	1		T69	5		T75	2
valid_sources[0x3c]	2713	1		T42	2		T69	1		T75	1
valid_sources[0x3d]	3349	1		T42	6		T69	2		T77	6
valid_sources[0x3e]	2707	1		T42	4		T69	2		T43	3
valid_sources[0x3f]	2712	1		T20	1		T131	1		T69	4
valid_sources[0x40]	2610	1		T69	5		T81	2		T77	8
valid_sources[0x41]	3099	1		T20	1		T69	2		T75	2
valid_sources[0x42]	3003	1		T23	1		T42	5		T69	4
valid_sources[0x43]	2982	1		T22	2		T44	2		T42	2
valid_sources[0x44]	2769	1		T17	1		T75	4		T43	5
valid_sources[0x45]	2679	1		T20	2		T17	3		T69	1
valid_sources[0x46]	2816	1		T42	3		T75	1		T43	2
valid_sources[0x47]	2800	1		T131	1		T16	1		T42	1
valid_sources[0x48]	3070	1		T15	1		T69	4		T75	1
valid_sources[0x49]	2714	1		T69	4		T81	4		T77	6
valid_sources[0x4a]	2980	1		T42	2		T69	2		T43	1
valid_sources[0x4b]	3176	1		T20	1		T44	1		T42	11
valid_sources[0x4c]	3275	1		T41	134		T75	2		T43	4
valid_sources[0x4d]	2769	1		T75	2		T43	2		T76	27
valid_sources[0x4e]	2807	1		T16	3		T69	1		T81	4
valid_sources[0x4f]	2843	1		T44	5		T42	1		T69	1
valid_sources[0x50]	2946	1		T42	2		T69	1		T75	2
valid_sources[0x51]	2795	1		T14	5		T69	2		T43	3
valid_sources[0x52]	2771	1		T75	4		T43	11		T81	1
valid_sources[0x53]	3285	1		T41	307		T69	3		T43	8
valid_sources[0x54]	3191	1		T75	4		T43	5		T81	13
valid_sources[0x55]	2751	1		T17	4		T44	4		T42	15
valid_sources[0x56]	2935	1		T69	1		T75	2		T43	3
valid_sources[0x57]	2660	1		T69	1		T77	23		T78	1
valid_sources[0x58]	3530	1		T41	274		T69	1		T75	1
valid_sources[0x59]	2898	1		T2	1		T69	4		T75	3
valid_sources[0x5a]	3135	1		T42	4		T69	1		T75	2
valid_sources[0x5b]	2827	1		T26	2		T75	1		T43	5
valid_sources[0x5c]	3405	1		T42	3		T69	2		T75	3
valid_sources[0x5d]	2998	1		T23	1		T69	1		T75	1
valid_sources[0x5e]	2990	1		T14	2		T41	275		T42	1
valid_sources[0x5f]	2821	1		T17	1		T27	1		T75	1
valid_sources[0x60]	2964	1		T20	3		T69	1		T75	2
valid_sources[0x61]	2947	1		T17	2		T69	3		T75	5
valid_sources[0x62]	2733	1		T42	9		T69	1		T75	3
valid_sources[0x63]	2981	1		T11	3		T42	1		T69	1
valid_sources[0x64]	2924	1		T23	4		T41	13		T75	4
valid_sources[0x65]	3407	1		T42	2		T43	2		T81	28
valid_sources[0x66]	2662	1		T43	1		T77	4		T82	38
valid_sources[0x67]	2711	1		T23	3		T43	1		T81	4
valid_sources[0x68]	2705	1		T44	2		T69	1		T43	3
valid_sources[0x69]	2942	1		T44	2		T42	9		T69	1
valid_sources[0x6a]	2787	1		T14	1		T81	6		T78	4
valid_sources[0x6b]	2763	1		T28	1		T75	1		T43	2
valid_sources[0x6c]	2843	1		T17	2		T28	1		T42	2
valid_sources[0x6d]	2820	1		T69	1		T75	1		T43	4
valid_sources[0x6e]	2735	1		T69	1		T75	6		T77	31
valid_sources[0x6f]	2935	1		T23	2		T42	3		T43	4
valid_sources[0x70]	2766	1		T17	3		T44	1		T75	3
valid_sources[0x71]	3017	1		T44	1		T69	1		T43	1
valid_sources[0x72]	2786	1		T17	1		T69	1		T75	3
valid_sources[0x73]	2917	1		T44	8		T69	1		T75	1
valid_sources[0x74]	2798	1		T14	7		T23	1		T42	6
valid_sources[0x75]	2678	1		T42	4		T69	2		T75	2
valid_sources[0x76]	2707	1		T22	1		T27	1		T44	1
valid_sources[0x77]	2829	1		T43	1		T81	13		T77	11
valid_sources[0x78]	2645	1		T17	3		T81	3		T77	8
valid_sources[0x79]	3099	1		T23	1		T12	40		T69	3
valid_sources[0x7a]	2993	1		T22	1		T16	1		T42	2
valid_sources[0x7b]	2781	1		T69	1		T75	1		T43	3
valid_sources[0x7c]	2996	1		T17	1		T44	1		T69	2
valid_sources[0x7d]	2896	1		T69	1		T43	6		T81	8
valid_sources[0x7e]	2743	1		T69	1		T75	2		T43	2
valid_sources[0x7f]	2680	1		T23	1		T69	2		T75	3
valid_sources[0x80]	3178	1		T41	156		T42	1		T81	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

288576

1

T6

8

T7

4

T20

6

values[0x0]

all_enables

biggest_size

126410

1

T2

2

T7

1

T60

1

values[0x1]

all_enables

biggest_size

125811

1

T21

1

T20

5

T10

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4917	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19655	1		T1	1		T29	2		T40	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9766	1		T41	36		T44	19		T42	176
values[0x0]	7238	1		T1	4		T29	5		T40	2
values[0x1]	7568	1		T1	4		T29	4		T40	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3745	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20827	1		T1	1		T29	2		T40	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	146	1		T132	1		T44	1		T69	44
valid_sources[0x01]	77	1		T44	1		T42	3		T76	2
valid_sources[0x02]	72	1		T42	4		T65	14		T79	1
valid_sources[0x03]	71	1		T42	6		T65	4		T78	2
valid_sources[0x04]	37	1		T42	3		T77	1		T78	2
valid_sources[0x05]	164	1		T44	1		T77	1		T65	5
valid_sources[0x06]	175	1		T57	1		T133	18		T42	2
valid_sources[0x07]	53	1		T42	4		T77	1		T79	4
valid_sources[0x08]	46	1		T134	1		T135	2		T42	6
valid_sources[0x09]	193	1		T136	4		T79	3		T80	1
valid_sources[0x0a]	109	1		T42	1		T78	1		T79	1
valid_sources[0x0b]	83	1		T42	3		T81	1		T83	2
valid_sources[0x0c]	139	1		T52	6		T42	2		T65	5
valid_sources[0x0d]	73	1		T137	3		T42	4		T43	1
valid_sources[0x0e]	163	1		T135	1		T42	4		T78	1
valid_sources[0x0f]	132	1		T53	3		T42	3		T78	2
valid_sources[0x10]	72	1		T44	1		T42	1		T79	4
valid_sources[0x11]	74	1		T59	6		T135	1		T42	1
valid_sources[0x12]	63	1		T42	1		T78	1		T79	2
valid_sources[0x13]	87	1		T42	4		T78	1		T79	4
valid_sources[0x14]	53	1		T138	1		T42	3		T79	2
valid_sources[0x15]	75	1		T139	15		T140	1		T141	1
valid_sources[0x16]	76	1		T42	2		T113	6		T115	16
valid_sources[0x17]	93	1		T47	4		T42	3		T65	12
valid_sources[0x18]	56	1		T41	6		T44	1		T42	2
valid_sources[0x19]	36	1		T42	2		T77	1		T79	3
valid_sources[0x1a]	64	1		T142	1		T44	1		T42	9
valid_sources[0x1b]	84	1		T42	2		T79	1		T80	1
valid_sources[0x1c]	156	1		T58	3		T138	3		T143	3
valid_sources[0x1d]	50	1		T42	3		T77	1		T78	2
valid_sources[0x1e]	65	1		T42	1		T79	2		T91	1
valid_sources[0x1f]	68	1		T40	1		T140	2		T42	3
valid_sources[0x20]	63	1		T42	2		T79	5		T114	2
valid_sources[0x21]	84	1		T77	1		T79	6		T144	1
valid_sources[0x22]	146	1		T44	1		T42	5		T77	1
valid_sources[0x23]	97	1		T42	1		T79	1		T114	4
valid_sources[0x24]	66	1		T42	3		T65	2		T79	3
valid_sources[0x25]	102	1		T142	3		T145	3		T44	3
valid_sources[0x26]	98	1		T146	1		T42	2		T78	1
valid_sources[0x27]	120	1		T42	1		T78	4		T79	2
valid_sources[0x28]	71	1		T44	2		T42	3		T78	1
valid_sources[0x29]	60	1		T42	4		T78	1		T147	2
valid_sources[0x2a]	102	1		T57	1		T148	1		T42	6
valid_sources[0x2b]	65	1		T149	8		T42	1		T77	1
valid_sources[0x2c]	64	1		T42	2		T79	7		T114	3
valid_sources[0x2d]	72	1		T134	1		T42	5		T113	2
valid_sources[0x2e]	281	1		T41	3		T42	3		T78	1
valid_sources[0x2f]	59	1		T40	1		T48	3		T42	1
valid_sources[0x30]	64	1		T58	1		T42	1		T79	1
valid_sources[0x31]	79	1		T44	1		T42	4		T77	2
valid_sources[0x32]	72	1		T138	1		T79	1		T80	1
valid_sources[0x33]	101	1		T42	2		T69	13		T79	4
valid_sources[0x34]	112	1		T141	1		T42	1		T79	1
valid_sources[0x35]	79	1		T29	9		T42	2		T79	3
valid_sources[0x36]	70	1		T42	1		T77	1		T79	1
valid_sources[0x37]	126	1		T42	5		T75	44		T79	2
valid_sources[0x38]	93	1		T148	1		T146	1		T77	3
valid_sources[0x39]	233	1		T42	2		T76	2		T79	1
valid_sources[0x3a]	59	1		T42	3		T84	4		T86	4
valid_sources[0x3b]	80	1		T42	3		T78	1		T79	1
valid_sources[0x3c]	57	1		T42	5		T77	2		T65	6
valid_sources[0x3d]	84	1		T42	3		T77	1		T65	2
valid_sources[0x3e]	97	1		T40	1		T42	3		T65	5
valid_sources[0x3f]	97	1		T42	2		T78	1		T79	3
valid_sources[0x40]	117	1		T138	1		T41	3		T44	1
valid_sources[0x41]	63	1		T42	1		T79	2		T91	1
valid_sources[0x42]	68	1		T150	1		T42	4		T79	6
valid_sources[0x43]	55	1		T146	1		T42	1		T78	2
valid_sources[0x44]	98	1		T42	2		T81	8		T78	1
valid_sources[0x45]	193	1		T42	4		T69	105		T65	24
valid_sources[0x46]	67	1		T57	1		T134	1		T41	3
valid_sources[0x47]	105	1		T50	22		T42	2		T76	4
valid_sources[0x48]	98	1		T140	1		T141	2		T42	6
valid_sources[0x49]	39	1		T5	3		T57	1		T78	1
valid_sources[0x4a]	101	1		T140	1		T44	1		T42	3
valid_sources[0x4b]	142	1		T151	7		T42	2		T79	3
valid_sources[0x4c]	81	1		T42	5		T79	1		T80	1
valid_sources[0x4d]	102	1		T140	1		T41	1		T42	4
valid_sources[0x4e]	128	1		T148	1		T42	2		T79	1
valid_sources[0x4f]	82	1		T134	1		T44	1		T42	2
valid_sources[0x50]	62	1		T42	3		T78	1		T85	2
valid_sources[0x51]	56	1		T70	2		T152	2		T42	2
valid_sources[0x52]	72	1		T134	1		T42	1		T69	16
valid_sources[0x53]	160	1		T42	3		T78	1		T79	3
valid_sources[0x54]	92	1		T42	1		T43	1		T65	2
valid_sources[0x55]	80	1		T46	1		T134	1		T42	3
valid_sources[0x56]	75	1		T1	2		T42	1		T81	1
valid_sources[0x57]	83	1		T148	1		T42	1		T65	1
valid_sources[0x58]	102	1		T57	1		T42	4		T79	1
valid_sources[0x59]	53	1		T42	3		T43	3		T77	1
valid_sources[0x5a]	213	1		T141	1		T42	2		T69	53
valid_sources[0x5b]	197	1		T135	1		T42	3		T77	1
valid_sources[0x5c]	160	1		T44	1		T42	5		T77	1
valid_sources[0x5d]	73	1		T42	1		T79	3		T80	1
valid_sources[0x5e]	81	1		T74	1		T42	2		T65	4
valid_sources[0x5f]	58	1		T42	2		T77	1		T78	1
valid_sources[0x60]	73	1		T42	1		T77	2		T79	3
valid_sources[0x61]	132	1		T41	5		T42	3		T75	60
valid_sources[0x62]	259	1		T138	1		T51	3		T70	1
valid_sources[0x63]	75	1		T143	3		T44	1		T77	1
valid_sources[0x64]	66	1		T47	2		T132	1		T42	2
valid_sources[0x65]	79	1		T44	1		T42	2		T79	3
valid_sources[0x66]	82	1		T57	1		T42	4		T79	3
valid_sources[0x67]	62	1		T148	1		T79	1		T80	1
valid_sources[0x68]	64	1		T57	1		T42	2		T79	2
valid_sources[0x69]	108	1		T42	1		T79	4		T114	1
valid_sources[0x6a]	76	1		T42	2		T85	1		T125	1
valid_sources[0x6b]	78	1		T42	5		T78	3		T79	3
valid_sources[0x6c]	84	1		T44	1		T42	1		T114	1
valid_sources[0x6d]	150	1		T48	3		T51	5		T153	7
valid_sources[0x6e]	57	1		T5	1		T42	1		T77	1
valid_sources[0x6f]	62	1		T19	7		T42	2		T79	3
valid_sources[0x70]	109	1		T154	2		T78	1		T79	3
valid_sources[0x71]	159	1		T42	2		T78	1		T79	4
valid_sources[0x72]	44	1		T148	1		T42	4		T78	1
valid_sources[0x73]	106	1		T44	1		T42	1		T79	3
valid_sources[0x74]	50	1		T1	1		T57	1		T140	2
valid_sources[0x75]	76	1		T46	1		T44	2		T42	1
valid_sources[0x76]	169	1		T132	1		T42	3		T79	5
valid_sources[0x77]	132	1		T138	1		T42	1		T79	2
valid_sources[0x78]	53	1		T42	2		T77	3		T79	1
valid_sources[0x79]	119	1		T42	4		T43	3		T79	2
valid_sources[0x7a]	58	1		T42	2		T80	1		T91	1
valid_sources[0x7b]	84	1		T155	13		T146	1		T42	1
valid_sources[0x7c]	70	1		T44	1		T42	2		T78	1
valid_sources[0x7d]	103	1		T44	1		T77	1		T65	3
valid_sources[0x7e]	171	1		T5	1		T44	1		T42	6
valid_sources[0x7f]	84	1		T42	4		T80	1		T91	2
valid_sources[0x80]	78	1		T49	1		T44	1		T42	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6704

1

T41

14

T44

15

T42

173

values[0x0]

all_enables

biggest_size

6503

1

T1

1

T29

2

T5

2

values[0x1]

all_enables

biggest_size

6448

1

T40

4

T5

1

T45

1