SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 772821 | 1 | T2 | 2 | T4 | 7 | T6 | 11 | |||
auto[1] | 18959 | 1 | T17 | 80 | T18 | 80 | T41 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 791624 | 1 | T2 | 2 | T4 | 7 | T6 | 11 | |||
values[1] | 12 | 1 | T76 | 2 | T121 | 3 | T122 | 1 | |||
values[2] | 7 | 1 | T121 | 2 | T122 | 2 | T123 | 1 | |||
values[3] | 80 | 1 | T41 | 4 | T76 | 3 | T77 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 791620 | 1 | T2 | 2 | T4 | 7 | T6 | 11 | |||
values[1] | 14 | 1 | T91 | 1 | T121 | 3 | T122 | 1 | |||
values[2] | 3 | 1 | T41 | 1 | T77 | 1 | T124 | 1 | |||
values[3] | 88 | 1 | T41 | 3 | T76 | 4 | T77 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 791540 | 1 | T2 | 2 | T4 | 7 | T6 | 11 | |||
auto[TlIntgErrCmd] | 80 | 1 | T41 | 2 | T76 | 1 | T77 | 3 | |||
auto[TlIntgErrData] | 84 | 1 | T41 | 4 | T76 | 4 | T77 | 4 | |||
auto[TlIntgErrBoth] | 76 | 1 | T41 | 4 | T76 | 5 | T77 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 40079 | 0 | T1 | 8 | T29 | 9 | T40 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39913 | 1 | T1 | 8 | T29 | 9 | T40 | 8 | |||
values[1] | 18 | 1 | T41 | 1 | T91 | 1 | T121 | 1 | |||
values[2] | 4 | 1 | T125 | 1 | T126 | 2 | T127 | 1 | |||
values[3] | 83 | 1 | T41 | 4 | T76 | 3 | T77 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39917 | 1 | T1 | 8 | T29 | 9 | T40 | 8 | |||
values[1] | 7 | 1 | T41 | 1 | T77 | 1 | T122 | 2 | |||
values[2] | 4 | 1 | T125 | 1 | T122 | 1 | T123 | 1 | |||
values[3] | 81 | 1 | T76 | 4 | T77 | 7 | T91 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 39839 | 1 | T1 | 8 | T29 | 9 | T40 | 8 | |||
auto[TlIntgErrCmd] | 78 | 1 | T41 | 2 | T76 | 4 | T77 | 1 | |||
auto[TlIntgErrData] | 74 | 1 | T41 | 3 | T76 | 2 | T77 | 5 | |||
auto[TlIntgErrBoth] | 88 | 1 | T41 | 5 | T76 | 4 | T77 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |