Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
249321 |
1 |
|
T4 |
7 |
|
T6 |
3 |
|
T7 |
4 |
full_word |
542459 |
1 |
|
T2 |
2 |
|
T6 |
8 |
|
T7 |
5 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
791540 |
1 |
|
T2 |
2 |
|
T4 |
7 |
|
T6 |
11 |
auto[TlIntgErrCmd] |
80 |
1 |
|
T41 |
2 |
|
T76 |
1 |
|
T77 |
3 |
auto[TlIntgErrData] |
84 |
1 |
|
T41 |
4 |
|
T76 |
4 |
|
T77 |
4 |
auto[TlIntgErrBoth] |
76 |
1 |
|
T41 |
4 |
|
T76 |
5 |
|
T77 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
497469 |
1 |
|
T6 |
10 |
|
T7 |
8 |
|
T20 |
10 |
auto[1] |
294311 |
1 |
|
T2 |
2 |
|
T4 |
7 |
|
T6 |
1 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
208586 |
1 |
|
T6 |
2 |
|
T7 |
4 |
|
T20 |
4 |
auto[TlIntgErrNone] |
partial |
auto[1] |
40523 |
1 |
|
T4 |
7 |
|
T6 |
1 |
|
T60 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
288766 |
1 |
|
T6 |
8 |
|
T7 |
4 |
|
T20 |
6 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
253665 |
1 |
|
T2 |
2 |
|
T7 |
1 |
|
T60 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
33 |
1 |
|
T41 |
2 |
|
T77 |
2 |
|
T91 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
36 |
1 |
|
T76 |
1 |
|
T77 |
1 |
|
T91 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
5 |
1 |
|
T121 |
1 |
|
T122 |
1 |
|
T128 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
T129 |
1 |
|
T125 |
1 |
|
T122 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
39 |
1 |
|
T41 |
1 |
|
T76 |
2 |
|
T77 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
41 |
1 |
|
T41 |
2 |
|
T76 |
2 |
|
T77 |
2 |
auto[TlIntgErrData] |
full_word |
auto[0] |
1 |
1 |
|
T125 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrData] |
full_word |
auto[1] |
3 |
1 |
|
T41 |
1 |
|
T126 |
1 |
|
T127 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
32 |
1 |
|
T41 |
2 |
|
T76 |
1 |
|
T129 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
31 |
1 |
|
T41 |
1 |
|
T76 |
3 |
|
T77 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
7 |
1 |
|
T77 |
1 |
|
T121 |
3 |
|
T130 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
6 |
1 |
|
T41 |
1 |
|
T76 |
1 |
|
T77 |
1 |