Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25559665	13716	0	0
late_debug_enable_rd_A	25559665	2064	0	0
late_debug_enable_regwen_rd_A	25559665	1826	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25559665	13716	0	0
T41	54411	2	0	0
T42	124289	285	0	0
T43	8706	57	0	0
T44	6835	231	0	0
T65	261375	53	0	0
T69	13596	807	0	0
T75	11300	536	0	0
T76	45572	4	0	0
T77	50611	3	0	0
T78	100225	32	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25559665	2064	0	0
T43	8706	7	0	0
T78	100225	31	0	0
T80	202636	62	0	0
T81	10460	5	0	0
T88	20628	27	0	0
T113	719325	77	0	0
T114	16920	172	0	0
T115	561131	52	0	0
T116	114943	31	0	0
T117	424161	113	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25559665	1826	0	0
T43	8706	29	0	0
T78	100225	24	0	0
T80	202636	47	0	0
T81	10460	12	0	0
T88	20628	5	0	0
T113	719325	82	0	0
T114	16920	82	0	0
T115	561131	54	0	0
T116	114943	20	0	0
T117	424161	99	0	0