Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36
1	1	Covered	T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	15880940	15880130	0	0
selKnown1	14289693	14288883	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	15880940	15880130	0	0
T1	356	354	0	0
T2	1500	1498	0	0
T3	1264	1262	0	0
T4	5744	5742	0	0
T5	376	374	0	0
T6	1382	1380	0	0
T7	1	0	0	0
T10	0	8	0	0
T19	356	354	0	0
T25	2	0	0	0
T29	316	314	0	0
T30	9	8	0	0
T32	0	122	0	0
T34	0	16	0	0
T36	0	21	0	0
T37	22	20	0	0
T38	22	20	0	0
T39	0	40	0	0
T40	314	312	0	0
T46	1	0	0	0
T47	2	0	0	0
T53	2	0	0	0
T54	310	308	0	0
T55	0	40	0	0
T56	0	20	0	0
T57	2	0	0	0
T58	2	0	0	0
T59	2	0	0	0
T61	0	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	14289693	14288883	0	0
T1	1288	1286	0	0
T2	4510	4508	0	0
T3	3162	3160	0	0
T4	8535	8533	0	0
T5	2784	2782	0	0
T6	1599	1597	0	0
T7	2	0	0	0
T10	0	8	0	0
T19	1478	1476	0	0
T25	2	0	0	0
T29	1983	1981	0	0
T32	0	122	0	0
T34	0	16	0	0
T36	0	4	0	0
T37	22	20	0	0
T38	22	20	0	0
T39	0	40	0	0
T40	1162	1160	0	0
T47	2	0	0	0
T53	2	0	0	0
T54	1816	1814	0	0
T55	0	40	0	0
T56	0	20	0	0
T57	2	0	0	0
T58	2	0	0	0
T59	2	0	0	0
T60	2	0	0	0
T61	0	8	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36
1	1	Covered	T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	3943929	3943831	0	0
selKnown1	2352799	2352701	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	3943929	3943831	0	0
T1	178	177	0	0
T2	750	749	0	0
T3	632	631	0	0
T4	2872	2871	0	0
T5	188	187	0	0
T6	691	690	0	0
T19	178	177	0	0
T29	158	157	0	0
T40	157	156	0	0
T54	155	154	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	2352799	2352701	0	0
T1	1110	1109	0	0
T2	3760	3759	0	0
T3	2530	2529	0	0
T4	5663	5662	0	0
T5	2596	2595	0	0
T6	908	907	0	0
T19	1300	1299	0	0
T29	1825	1824	0	0
T40	1005	1004	0	0
T54	1661	1660	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36
1	1	Covered	T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	255	157	0	0
selKnown1	247	149	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	255	157	0	0
T7	1	0	0	0
T10	0	4	0	0
T25	1	0	0	0
T32	0	61	0	0
T34	0	8	0	0
T36	0	10	0	0
T37	11	10	0	0
T38	11	10	0	0
T39	0	20	0	0
T47	1	0	0	0
T53	1	0	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	1	0	0	0
T58	1	0	0	0
T59	1	0	0	0
T60	1	0	0	0
T61	0	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	247	149	0	0
T7	1	0	0	0
T10	0	4	0	0
T25	1	0	0	0
T32	0	61	0	0
T34	0	8	0	0
T36	0	2	0	0
T37	11	10	0	0
T38	11	10	0	0
T39	0	20	0	0
T47	1	0	0	0
T53	1	0	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	1	0	0	0
T58	1	0	0	0
T59	1	0	0	0
T60	1	0	0	0
T61	0	4	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36
1	1	Covered	T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	11935276	11934969	0	0
selKnown1	11935276	11934969	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	11935276	11934969	0	0
T1	178	177	0	0
T2	750	749	0	0
T3	632	631	0	0
T4	2872	2871	0	0
T5	188	187	0	0
T6	691	690	0	0
T19	178	177	0	0
T29	158	157	0	0
T40	157	156	0	0
T54	155	154	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	11935276	11934969	0	0
T1	178	177	0	0
T2	750	749	0	0
T3	632	631	0	0
T4	2872	2871	0	0
T5	188	187	0	0
T6	691	690	0	0
T19	178	177	0	0
T29	158	157	0	0
T40	157	156	0	0
T54	155	154	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36
1	1	Covered	T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1480	1173	0	0
selKnown1	1371	1064	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1173	0	0
T10	0	4	0	0
T25	1	0	0	0
T30	9	8	0	0
T32	0	61	0	0
T34	0	8	0	0
T36	0	11	0	0
T37	11	10	0	0
T38	11	10	0	0
T39	0	20	0	0
T46	1	0	0	0
T47	1	0	0	0
T53	1	0	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	1	0	0	0
T58	1	0	0	0
T59	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1371	1064	0	0
T7	1	0	0	0
T10	0	4	0	0
T25	1	0	0	0
T32	0	61	0	0
T34	0	8	0	0
T36	0	2	0	0
T37	11	10	0	0
T38	11	10	0	0
T39	0	20	0	0
T47	1	0	0	0
T53	1	0	0	0
T55	0	20	0	0
T56	0	10	0	0
T57	1	0	0	0
T58	1	0	0	0
T59	1	0	0	0
T60	1	0	0	0
T61	0	4	0	0