41bc3e0c7f
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 2.190s | 474.754us | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.060s | 156.068us | 4 | 5 | 80.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.880s | 156.831us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 4.520s | 1.047ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.820s | 62.033us | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 3.510s | 773.526us | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 8.270s | 2.435ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.539m | 27.714ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 28.360s | 22.850ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 4.320s | 1.845ms | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 9.780s | 3.170ms | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 1.090s | 548.607us | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.010s | 362.280us | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.880s | 56.655us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.340s | 948.685us | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.800s | 38.783us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 0.690s | 97.623us | 0 | 2 | 0.00 |
V1 | progbuf_busy | rv_dm_progbuf_busy | 1.490s | 198.599us | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.810s | 27.118us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.870s | 54.562us | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 1.090s | 548.607us | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 0.810s | 99.221us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.520s | 950.896us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.440s | 633.322us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.207m | 15.176ms | 4 | 5 | 80.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.282m | 31.065ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 13.460s | 6.142ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.282m | 31.065ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.440s | 633.322us | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 0.730s | 28.758us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 0.680s | 18.210us | 5 | 5 | 100.00 |
V1 | TOTAL | 157 | 161 | 97.52 | |||
V2 | idcode | rv_dm_smoke | 2.190s | 474.754us | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.880s | 941.496us | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.160m | 50.000ms | 0 | 2 | 0.00 |
V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.960s | 379.907us | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 7.120s | 2.246ms | 3 | 20 | 15.00 |
rv_dm_delayed_resp_sba_tl_access | 1.740s | 320.276us | 0 | 20 | 0.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 1.400s | 215.954us | 0 | 20 | 0.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 54.220s | 44.754ms | 2 | 20 | 10.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.740s | 81.216us | 0 | 2 | 0.00 |
V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
V2 | ndmreset_req | rv_dm_ndmreset_req | 1.880s | 334.716us | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 1.280s | 213.039us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 2.880s | 2.286ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 43.500s | 12.947ms | 16 | 40 | 40.00 | ||
V2 | stress_all | rv_dm_stress_all | 17.370s | 5.129ms | 2 | 50 | 4.00 |
V2 | alert_test | rv_dm_alert_test | 0.820s | 40.615us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.970s | 448.728us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.970s | 448.728us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.282m | 31.065ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.520s | 950.896us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.440s | 633.322us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.450s | 3.317ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.282m | 31.065ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.520s | 950.896us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.440s | 633.322us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.450s | 3.317ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 125 | 276 | 45.29 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 1.980s | 300.516us | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 20.260s | 3.468ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.408m | 24.475ms | 0 | 50 | 0.00 |
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 307 | 512 | 59.96 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 28 | 28 | 25 | 89.29 |
V2 | 18 | 16 | 8 | 44.44 |
V2S | 10 | 2 | 2 | 20.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
79.72 | 93.86 | 81.18 | 87.69 | 73.08 | 82.50 | 98.52 | 41.19 |
UVM_ERROR (rv_dm_scoreboard.sv:250) [scoreboard] Check failed sba_item.rdata[*] == data (* [*] vs * [*])
has 41 failures:
0.rv_dm_sba_tl_access.86314403292808502203150891436575478715754223908310213543101129532447459441929
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 56098746 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2291657348 [0x8897ea84])
SBA item:
item: (sba_access_item@6487) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h36f9ea8c wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6397) { a_addr: 'h36f9ea8c a_data: 'hbc71de1b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2755f d_param: 'h0 d_source: 'h0 d_data: 'h8897ea84 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd1a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_sba_tl_access.101542150522113398926631048877323611924534192342519414829195126690895889446066
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 321968711 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 224 [0xe0])
SBA item:
item: (sba_access_item@9289) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'hd9d6352 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@9233) { a_addr: 'hd9d6350 a_data: 'h8f6d0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h242e7 d_param: 'h0 d_source: 'h0 d_data: 'he0c48b d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd75 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 13 more failures.
0.rv_dm_delayed_resp_sba_tl_access.2493650018261462897092644353638247351684038829169017666639540415056195039796
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 79685871 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2948363581 [0xafbc753d])
SBA item:
item: (sba_access_item@5981) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'h86b1882c wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5943) { a_addr: 'h86b1882c a_data: 'h8f90fd93 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h259e7 d_param: 'h0 d_source: 'h0 d_data: 'hafbc753d d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd11 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_delayed_resp_sba_tl_access.50670001572708418958628918151137787882028608399743200862683333088308400287221
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 320276059 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1908933028 [0x71c801a4])
SBA item:
item: (sba_access_item@7249) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h3e13f760 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7193) { a_addr: 'h3e13f760 a_data: 'h5b33b8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h24ac7 d_param: 'h0 d_source: 'h0 d_data: 'h71c801a4 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd6a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 15 more failures.
0.rv_dm_autoincr_sba_tl_access.74332936486658946243491902715942899017377496550457038849754940604289584086473
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 18275124 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 10930257 [0xa6c851])
SBA item:
item: (sba_access_item@5755) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'hbdf3e629 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5661) { a_addr: 'hbdf3e628 a_data: 'h222c2300 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h25551 d_param: 'h0 d_source: 'h0 d_data: 'ha6c851fb d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd69 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_autoincr_sba_tl_access.34200730160381152202100035879207061338308842688632788221868367106510110765130
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 21150593 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2129116654 [0x7ee7bdee])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5343) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'h7ee7bdee d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd67 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 2 more failures.
3.rv_dm_bad_sba_tl_access.95533771964936850184027324511676144919871773852272744665917713072208341312957
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 41373675 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 35410 [0x8a52])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'had3fe37e wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrBadAddr timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5343) { a_addr: 'had3fe37c a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h24e2a d_param: 'h0 d_source: 'h0 d_data: 'h8a52682c d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'hea0 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
12.rv_dm_bad_sba_tl_access.86725405511854351970813609597703473836971581681318917472879359520582842638351
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 131336841 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 4201635766 [0xfa6fdfb6])
SBA item:
item: (sba_access_item@5465) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5413) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'hfa6fdfb6 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h1 d_user: 'hee7 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 3 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*])
has 25 failures:
0.rv_dm_stress_all.53755725338166354873199185938614309662595168457060782517734316994351732827901
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 74608180 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 74608180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all.73678489450083725607434892614566078501843513887409442512177062325229688297901
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1943826562 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 1943826562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
3.rv_dm_stress_all_with_rand_reset.72243937933261530651321480161770406008243466234439193575539388326107458568336
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55875105 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 55875105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_stress_all_with_rand_reset.107034070581979686288554762531617686616863785749453427145064569618685069991549
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 91121107 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 91121107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:91) m_jtag_dmi_monitor [m_jtag_dmi_monitor] JTAG operation * != DmiOpNone in quiet period
has 15 failures:
Test rv_dm_halt_resume_whereto has 2 failures.
0.rv_dm_halt_resume_whereto.90999570725170906598380883414173485658080241597513650325526894107668377818010
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 69106758 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 69106758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_halt_resume_whereto.100396216851564219386642264606732985979743438937586980482480578689750335054478
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 97622626 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 97622626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 4 failures.
1.rv_dm_stress_all_with_rand_reset.25251937114746629631038465869912146013882097332184363682692400379656253414626
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 49606355 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 49606355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.21950951387386562576834628913259621740743278762149659874588010065744852794465
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 65061971 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 65061971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test rv_dm_stress_all has 9 failures.
4.rv_dm_stress_all.43344645899881172566100286344948360124338482194985211779343748084105414557821
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1348765504 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 1348765504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all.22889225311506516121818684083578345685240138027931774618652803766328810862889
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 9601384081 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 9601384081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==
gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 11 failures:
0.rv_dm_bad_sba_tl_access.108000214953890609481310357117380240210326865639781316071331972145768760918701
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 215954201 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 4 [0x4])
UVM_INFO @ 215954201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_bad_sba_tl_access.113395523377725834596252597263737188758819799507432821856927901571482160982907
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 32166443 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 32166443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
4.rv_dm_autoincr_sba_tl_access.44849098885555954626936707273992137055473260473406434732598025721120337501087
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 45286869 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 45286869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_autoincr_sba_tl_access.80907659045095322675150398966898215359992545716289657683746530725497105326824
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 176506488 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 176506488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*])
has 8 failures:
0.rv_dm_tap_fsm_rand_reset.114438571475874485681834988973868452050318116053092466150133872757579870185300
Line 309, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 7916642363 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7916642363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_tap_fsm_rand_reset.93229892301683982224407604358802400745163795006780119296994006001902319628979
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 585815379 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 585815379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
has 8 failures:
Test rv_dm_jtag_dmi_debug_disabled has 2 failures.
0.rv_dm_jtag_dmi_debug_disabled.64906529812924068277847893665138623888564995719777687889186075839126282469261
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 23802141 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (671863882 [0x280bd44a] vs 472165562 [0x1c24acba])
UVM_INFO @ 23802141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_debug_disabled.59452513969899728983784680431713516697291907537278465548527982387963425916145
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 81215763 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3949609494 [0xeb6a4216])
UVM_INFO @ 81215763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
5.rv_dm_stress_all_with_rand_reset.23963026596543940856665312013146708355661610036561401517336019690120945110003
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 917357599 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 185695490 [0xb117d02])
UVM_INFO @ 917357599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all_with_rand_reset.11115105420527633075767984320667960038328616743199403388994912607549640773444
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 58615097 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 2255495600 [0x867021b0])
UVM_INFO @ 58615097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 4 failures.
17.rv_dm_stress_all.4367969858912011504774653560294418861190172528272246530044239335510748919583
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2481580173 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (671863882 [0x280bd44a] vs 593018296 [0x2358bdb8])
UVM_INFO @ 2481580173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all.63499548594674999185387242943700953210547166729331741588816096107442186327788
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 32137454 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (671863882 [0x280bd44a] vs 294624168 [0x118f9ba8])
UVM_INFO @ 32137454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*])
has 7 failures:
1.rv_dm_tap_fsm_rand_reset.98930017629860428554683805140963516406026924676325104247885262930397659318056
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1031579510 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1031579510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_tap_fsm_rand_reset.110364031546984669975892314742418075971350470362414104745482761842274616761455
Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4292149044 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4292149044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 6 failures:
7.rv_dm_stress_all_with_rand_reset.73284988330262540315109014623906803130549687525617343521904922723050714511076
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33863516 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33863516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.rv_dm_stress_all_with_rand_reset.50128476807816647412082272038586233100763954395591459990451995904298800810281
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28393719 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28393719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
20.rv_dm_stress_all.21134877298406213949753453294139469823922053220589611718408122587888899577896
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 53682478 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 53682478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.rv_dm_stress_all.55550656696036678050854086861969746719495129406472066429935051432207194888107
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10400474 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10400474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 5 failures:
Test rv_dm_jtag_dtm_idle_hint has 2 failures.
0.rv_dm_jtag_dtm_idle_hint.38188653077646540446468061939163258651844573016427179644165461608153121341674
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dtm_idle_hint.8191329006207062090790137688226625481186209384220451141109400594603676355179
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_csr_bit_bash has 1 failures.
3.rv_dm_csr_bit_bash.1607642084096089990922047711893041157523531392260820242711756744650082556283
Line 316, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 2 failures.
11.rv_dm_autoincr_sba_tl_access.30058594692913668196054410857506297722314206380113925145333124311777959792583
Line 413, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_autoincr_sba_tl_access.30656332364233105644903055993837578307663613899462221980506040334634385713106
Line 404, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:280) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (* [*] vs * [*])
has 5 failures:
1.rv_dm_bad_sba_tl_access.10931200546572131415548756833039295263077203738800791830638098055270860946100
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 92861171 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 92861171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_bad_sba_tl_access.13550575362693054898457914818348121906942335029378698761949043451210504050236
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 32721787 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 32721787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
8.rv_dm_autoincr_sba_tl_access.39765678511747553707797504934810741940198111473850621048636233339460641309862
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 88748512 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 88748512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_autoincr_sba_tl_access.14543978194487942116214297823666590427594267387411774868449136960946084491457
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 94891949 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 94891949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:282) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (* [*] vs * [*])
has 5 failures:
2.rv_dm_bad_sba_tl_access.83485951629609902281118916328405784413070450248404302579921825554163079037415
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 50645633 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 50645633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_bad_sba_tl_access.57067751221496091227184149508291511371862836416938788898066444242245915613736
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 292315805 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 292315805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
2.rv_dm_autoincr_sba_tl_access.38888844858759321610963179314950514605530436921082120606461023711118066720500
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 226740053 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 226740053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_dm_autoincr_sba_tl_access.76548262364995327363566023593800181969396349919171911318549642508146458133226
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 437423221 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 437423221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 5 failures:
13.rv_dm_stress_all_with_rand_reset.63664564352619762491804180883142437468023975474225169434423041046903119780663
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25802407 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25802407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_dm_stress_all_with_rand_reset.48960823089993117838790142169226650890823929066131253410512819416932253010190
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55258461 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 55258461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
36.rv_dm_stress_all.85432866137532597828142382457106433461503165463496673947469498986640563994262
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 21871211 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21871211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:26) [rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, data) (* [*] vs * [*])
has 5 failures:
15.rv_dm_stress_all_with_rand_reset.15744522458276066189839437603343738343765657980186921120098872046222199765690
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16768154 ps: (rv_dm_hart_unavail_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 16768154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all_with_rand_reset.30769637023398746218842336531115566475593186270078598806886566797698771482799
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19336437 ps: (rv_dm_hart_unavail_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 19336437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
16.rv_dm_stress_all.12345450735830087723131394284394013223677058072997104639236985726742374155259
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 9833721 ps: (rv_dm_hart_unavail_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9833721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 5 failures:
25.rv_dm_stress_all.37716963121732897480642374215071653301132998191389996882288005271714642752173
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10401533 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10401533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.rv_dm_stress_all.66255449371021931034697385184891744896305320534482170799878531791058688922693
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7924434 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7924434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
42.rv_dm_stress_all_with_rand_reset.54390503348939491669109536872402058144640735470479523053377260672455046170265
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45753507 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45753507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.rv_dm_stress_all_with_rand_reset.84528364363054243954293158397413301338012085582561545270514294176585032574243
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35211387 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 35211387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 4 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
0.rv_dm_stress_all_with_rand_reset.40788136314505214437078354119198563737319592279174326289509229579059603457243
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47869624 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 47869624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rv_dm_stress_all_with_rand_reset.90975516555439723673728911434355262728531095216566705860796539830159254637410
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23881077 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23881077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 2 failures.
31.rv_dm_stress_all.75856286478544783832955324123741444535798016199283923529745712300609051418467
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 18899384 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18899384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_dm_stress_all.24473411300319578153762459735896250941141769986987973636758729163064807776360
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 11384612 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11384612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_*
has 4 failures:
12.rv_dm_stress_all_with_rand_reset.72179301135940843753285805995248580568854999530165084975759198552202437511404
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5646923007 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1484041474 [0x5874ad02]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 5646923007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all_with_rand_reset.13323932600566104547803419887115900340284042420758840503924986804580524483952
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 266514365 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 3057452112 [0xb63d0450]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 266514365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*])
has 3 failures:
5.rv_dm_tap_fsm_rand_reset.26153176471765857021677897865144534662179258706609712811148157073688085154956
Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 6745112285 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6745112285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_tap_fsm_rand_reset.102795583305432732061836631275625423233463712361787135453061672817152500957890
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1702724405 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1702724405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 3 failures:
6.rv_dm_stress_all_with_rand_reset.59370327896797428311897345694174781426118947216813694074238295817366849636776
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 439110904 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 439110904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_dm_stress_all_with_rand_reset.83799564276468999777774404883812988828867268258424869255975348733368177519838
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 679823572 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 679823572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:260) [scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (* [*] vs * [*])
has 3 failures:
Test rv_dm_autoincr_sba_tl_access has 2 failures.
7.rv_dm_autoincr_sba_tl_access.77112685479334234603595593477159714448924302429376753829570962036890445888758
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 30973003 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (0 [0x0] vs 1 [0x1])
SBA item:
item: (sba_access_item@5665) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h1f328358 wdata: { [0]: 'h18449434 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5627) { a_addr: 'h1f328358 a_data: 'h18449434 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h27e26 d_param: 'h0 d_source: 'h0 d_data: 'h58457078 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1cc4 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
12.rv_dm_autoincr_sba_tl_access.33349842785496644932565103604871459766584118121042772014746023851095653418758
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 61753826 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (0 [0x0] vs 1 [0x1])
SBA item:
item: (sba_access_item@5665) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h892fa53c wdata: { [0]: 'h12280c71 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5609) { a_addr: 'h892fa53c a_data: 'h12280c71 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h254a3 d_param: 'h0 d_source: 'h0 d_data: 'he7a284a1 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1ce2 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
12.rv_dm_delayed_resp_sba_tl_access.53659250977030683893491392763890444149422058373693222003723324495939702597
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 76370914 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@5821) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hd347584e wdata: { [0]: 'hee05de72 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5683) { a_addr: 'hd347584c a_data: 'h5a1c0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h243c2 d_param: 'h0 d_source: 'h0 d_data: 'h31d34eed d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd5d a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (jtag_dmi_monitor.sv:67) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * }
has 3 failures:
Test rv_dm_stress_all has 2 failures.
14.rv_dm_stress_all.40054538190597441102197089774156014460775374140197811685769207545445749747849
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1598277 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1598277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all.71903271990350408777811907066029071457019944331366858284642547772779091861295
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1446977 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1446977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
26.rv_dm_stress_all_with_rand_reset.58655161964281062393848548511638506692202497865557141640107340185372022818693
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2056318 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2056318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*])
has 3 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
14.rv_dm_stress_all_with_rand_reset.95287868218574672929436903584080886687628159923859867236267135856255558821163
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 142547040 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (671863882 [0x280bd44a] vs 0 [0x0])
UVM_INFO @ 142547040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_dm_stress_all_with_rand_reset.68721117524671863741378466925679027554680095507031791051548920956783011041021
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 73415601 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (671863882 [0x280bd44a] vs 0 [0x0])
UVM_INFO @ 73415601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
41.rv_dm_stress_all.38898624615842064792606535130433048097297736507805331155725027825094914058333
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3082957906 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 3082957906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*])
has 2 failures:
2.rv_dm_stress_all.110135312274240067339828857979287561788664511409637601055905022460161485650538
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 21307485 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21307485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_stress_all.66048795927983227675668780802584278492640923775806293131068962811920767653608
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 37452675 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 37452675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*])
has 2 failures:
6.rv_dm_tap_fsm_rand_reset.103870992225006449329456736329802758681138283328854105688246936326699681620231
Line 371, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 7991602630 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7991602630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_tap_fsm_rand_reset.51104935010985824633995961748792080509261331740535037300740313816308974336284
Line 295, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4453472812 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4453472812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*])
has 2 failures:
9.rv_dm_stress_all_with_rand_reset.54235293089124748749137981286722660178352011553283069426433190433536206220628
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27499691 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (1 [0x1] vs 671863882 [0x280bd44a])
UVM_INFO @ 27499691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_stress_all_with_rand_reset.29015678829626975183545162952250286250411131732478089759545702228383385485998
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40924901 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (28 [0x1c] vs 671863882 [0x280bd44a])
UVM_INFO @ 40924901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:275) [scoreboard] Check failed byte_mask == sba_tl_item.a_mask (* [*] vs * [*])
has 2 failures:
10.rv_dm_autoincr_sba_tl_access.110312217788601380225652855373284313270217458199771337605323448092735597546930
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 38735571 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@6189) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'he06d5128 wdata: { [0]: 'hdccd53ad } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrBadAddr timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6133) { a_addr: 'he06d5128 a_data: 'hdccd53ad a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h27d69 d_param: 'h0 d_source: 'h0 d_data: 'h700c359e d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h1 d_user: 'h1f67 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
17.rv_dm_autoincr_sba_tl_access.50607479831561979019293756748393845454211186510110514229989748540810549346112
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 252113661 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@6445) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h8730e84c wdata: { [0]: 'h6c0c5156 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrOther timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6385) { a_addr: 'h8730e84c a_data: 'h6c0c5156 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h26dae d_param: 'h0 d_source: 'h0 d_data: 'he905297 d_size: 'h2 d_opcode: 'h2 d_error: 'h1 d_sink: 'h1 d_user: 'h73d a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*)
has 2 failures:
13.rv_dm_tap_fsm_rand_reset.6897490510325677486986089186191729386287674916105419186404903846934036407802
Line 293, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 22304619284 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 22304619284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_dm_tap_fsm_rand_reset.55521306460735027283125065206377844604625127044516278919107228961544654771267
Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 8990504094 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 8990504094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:136) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
has 2 failures:
Test rv_dm_stress_all has 1 failures.
15.rv_dm_stress_all.14719651543403836733285569813465869857025839385386293980431215411398724904578
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6460501 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 6460501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
36.rv_dm_stress_all_with_rand_reset.102490182949529921009997778574245868629781325330443475054815108618244665195812
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21724559 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 21724559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:38) [rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == get_field_val(jtag_dmi_ral.dmcontrol.ndmreset, rdata) (* [*] vs * [*])
has 2 failures:
26.rv_dm_stress_all.67663384017193246951563385428188873342107555115421657794610712245397642466146
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 56921478 ps: (rv_dm_ndmreset_req_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == get_field_val(jtag_dmi_ral.dmcontrol.ndmreset, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 56921478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_stress_all.59311121985204486277053539965533609571440640551583154519871741223567929729741
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 223393873 ps: (rv_dm_ndmreset_req_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == get_field_val(jtag_dmi_ral.dmcontrol.ndmreset, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 223393873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 2 failures:
36.rv_dm_tap_fsm_rand_reset.27861819028423452448376936194902656840393160904426442596624698471935547808354
Line 338, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 9509902704 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 9509902704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.rv_dm_tap_fsm_rand_reset.10510467805715955751210513072489328216962085104801547496316600277349136700179
Line 361, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 10754030276 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 10754030276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_monitor.sv:197) [monitor] Check failed (pending_a_req.exists(cfg.vif.mon_cb.d2h.d_source)) Cannot find request matching d_source *
has 1 failures:
2.rv_dm_jtag_dtm_csr_hw_reset.74877418196803950249578697552610335427576907702621010607790848173498677211971
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
UVM_FATAL @ 156068011 ps: (tl_monitor.sv:197) [uvm_test_top.env.m_tl_sba_agent.monitor] Check failed (pending_a_req.exists(cfg.vif.mon_cb.d2h.d_source)) Cannot find request matching d_source 0x0
UVM_INFO @ 156068011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*])
has 1 failures:
2.rv_dm_stress_all_with_rand_reset.62907976326326937775018424889845843676058434387983210120177547165092278827059
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 529103688 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (8 [0x8] vs 25690134 [0x1880016])
UVM_INFO @ 529103688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:173) [m_sba_access_monitor] Check failed (dmi_item.rdata inside {exp_addr, exp_addr + (* << size)})
has 1 failures:
3.rv_dm_autoincr_sba_tl_access.52201360431722629632366954521095983035116095672658324505765402508895067983779
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 68287038 ps: (sba_access_monitor.sv:173) [uvm_test_top.env.m_sba_access_monitor] Check failed (dmi_item.rdata inside {exp_addr, exp_addr + (1 << size)})
UVM_INFO @ 68287038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:178) [m_sba_access_monitor] Check failed dmi_item.rdata == exp_addr (* [*] vs * [*])
has 1 failures:
5.rv_dm_autoincr_sba_tl_access.32789629750725373879105662320140556504496052854973304273272335757541796681344
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 262016063 ps: (sba_access_monitor.sv:178) [uvm_test_top.env.m_sba_access_monitor] Check failed dmi_item.rdata == exp_addr (0 [0x0] vs 267980744 [0xff90fc8])
UVM_INFO @ 262016063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*)
has 1 failures:
5.rv_dm_stress_all.103176886891095656256421827574682358673353459821472929733294001475184751151249
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 4864330059 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x7397c100)
UVM_INFO @ 4864330059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@7301) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
7.rv_dm_sba_tl_access.74852158576440139865739320591226414725579540886200954692116760833144985041863
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 302599198 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@7301) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h4bc8f889 wdata: { [0]: 'h8a7ada30 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 302599198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5741) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
8.rv_dm_delayed_resp_sba_tl_access.50470659415095199361085924511264936830450887034762481157625510641731867056032
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 22859993 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5741) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h88bdc24f wdata: { [0]: 'h1ef8764c } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 22859993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*])
has 1 failures:
8.rv_dm_stress_all.84279846993675288356276807778062899719908687057611549824354495500730426079251
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 133625250 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 133625250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:50) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, data) (* [*] vs * [*])
has 1 failures:
9.rv_dm_stress_all.79404226067871493998175451890846412775529944228338598308720566206114165869491
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 30017165 ps: (rv_dm_smoke_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 30017165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@7957) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
14.rv_dm_sba_tl_access.109146406201777296881252031245855587756023230798085054415502796608818658966613
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 67816396 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@7957) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h94381e92 wdata: { [0]: 'h3fa1bda2 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 67816396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 1 failures:
18.rv_dm_stress_all.18501015041018259553466642052048162539322098149504613650132834085002617226623
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
Job ID: smart:95039396-3af9-4875-9fbd-a674ffc3ed7a
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen
has 1 failures:
18.rv_dm_stress_all_with_rand_reset.38206400314920754117826278215522857522835080382889984845965539564737691014607
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 24498032 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 24498032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5921) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
19.rv_dm_delayed_resp_sba_tl_access.73977191121244660299497737617083907943897439903348675870656480848467527124857
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 34602852 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5921) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'he8eb4c27 wdata: { [0]: 'hd6c8620 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 34602852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable
has 1 failures:
33.rv_dm_stress_all_with_rand_reset.63846786417606990771595384446009905256225175468192589498569001616231979240189
Line 289, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 24475420429 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 24475420429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 1 failures:
35.rv_dm_stress_all.62318952596558694276870370203184698339278587400981463728026995171428057139610
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10057041047 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 10057041047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---