RV_DM Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.190s 474.754us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.060s 156.068us 4 5 80.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.880s 156.831us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 4.520s 1.047ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.820s 62.033us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 3.510s 773.526us 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 8.270s 2.435ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.539m 27.714ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 28.360s 22.850ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 4.320s 1.845ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 9.780s 3.170ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.090s 548.607us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.010s 362.280us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.880s 56.655us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.340s 948.685us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.800s 38.783us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.690s 97.623us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 1.490s 198.599us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.810s 27.118us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.870s 54.562us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.090s 548.607us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.810s 99.221us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.520s 950.896us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.440s 633.322us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.207m 15.176ms 4 5 80.00
V1 csr_aliasing rv_dm_csr_aliasing 1.282m 31.065ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 13.460s 6.142ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.282m 31.065ms 5 5 100.00
rv_dm_csr_rw 2.440s 633.322us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.730s 28.758us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.680s 18.210us 5 5 100.00
V1 TOTAL 157 161 97.52
V2 idcode rv_dm_smoke 2.190s 474.754us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.880s 941.496us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.160m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.960s 379.907us 2 2 100.00
V2 sba rv_dm_sba_tl_access 7.120s 2.246ms 3 20 15.00
rv_dm_delayed_resp_sba_tl_access 1.740s 320.276us 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 1.400s 215.954us 0 20 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 54.220s 44.754ms 2 20 10.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.740s 81.216us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 1.880s 334.716us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.280s 213.039us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 2.880s 2.286ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 43.500s 12.947ms 16 40 40.00
V2 stress_all rv_dm_stress_all 17.370s 5.129ms 2 50 4.00
V2 alert_test rv_dm_alert_test 0.820s 40.615us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.970s 448.728us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.970s 448.728us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.282m 31.065ms 5 5 100.00
rv_dm_csr_hw_reset 2.520s 950.896us 5 5 100.00
rv_dm_csr_rw 2.440s 633.322us 20 20 100.00
rv_dm_same_csr_outstanding 8.450s 3.317ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.282m 31.065ms 5 5 100.00
rv_dm_csr_hw_reset 2.520s 950.896us 5 5 100.00
rv_dm_csr_rw 2.440s 633.322us 20 20 100.00
rv_dm_same_csr_outstanding 8.450s 3.317ms 20 20 100.00
V2 TOTAL 125 276 45.29
V2S tl_intg_err rv_dm_sec_cm 1.980s 300.516us 5 5 100.00
rv_dm_tl_intg_err 20.260s 3.468ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.408m 24.475ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 307 512 59.96

Testplan Progress

Items Total Written Passing Progress
V1 28 28 25 89.29
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.72 93.86 81.18 87.69 73.08 82.50 98.52 41.19

Failure Buckets

Past Results