Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	183788	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	529557	1		T1	7		T3	5		T7	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	446129	1		T1	10		T5	8		T27	8
values[0x0]	131179	1		T3	6		T7	11		T8	3
values[0x1]	136037	1		T1	1		T3	10		T7	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	140490	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	572855	1		T1	8		T3	8		T7	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3007	1		T7	2		T28	3		T44	12
valid_sources[0x01]	2570	1		T6	1		T79	2		T44	15
valid_sources[0x02]	2610	1		T9	2		T44	10		T42	5
valid_sources[0x03]	2818	1		T44	13		T42	12		T40	31
valid_sources[0x04]	2557	1		T23	11		T14	2		T44	12
valid_sources[0x05]	3852	1		T44	23		T42	4		T40	51
valid_sources[0x06]	2843	1		T44	10		T42	30		T40	23
valid_sources[0x07]	2766	1		T6	1		T14	1		T44	6
valid_sources[0x08]	2965	1		T14	4		T44	7		T40	20
valid_sources[0x09]	2434	1		T9	1		T44	7		T40	48
valid_sources[0x0a]	3512	1		T44	11		T42	30		T40	41
valid_sources[0x0b]	2749	1		T44	13		T40	49		T43	8
valid_sources[0x0c]	2434	1		T44	6		T42	10		T40	56
valid_sources[0x0d]	2564	1		T9	2		T13	1		T44	6
valid_sources[0x0e]	2463	1		T19	2		T9	3		T14	5
valid_sources[0x0f]	3149	1		T23	3		T44	12		T42	10
valid_sources[0x10]	3096	1		T14	8		T44	6		T42	11
valid_sources[0x11]	2611	1		T1	11		T79	2		T96	16
valid_sources[0x12]	2817	1		T13	2		T44	16		T42	1
valid_sources[0x13]	2420	1		T19	3		T44	4		T39	1
valid_sources[0x14]	2758	1		T9	1		T14	5		T44	11
valid_sources[0x15]	2813	1		T6	1		T9	2		T44	8
valid_sources[0x16]	3281	1		T9	1		T14	1		T44	9
valid_sources[0x17]	3216	1		T28	2		T44	9		T42	23
valid_sources[0x18]	2665	1		T44	11		T40	51		T43	18
valid_sources[0x19]	2558	1		T16	1		T79	2		T44	11
valid_sources[0x1a]	2955	1		T44	12		T42	35		T40	42
valid_sources[0x1b]	3545	1		T23	9		T44	14		T42	19
valid_sources[0x1c]	2827	1		T44	11		T42	7		T40	28
valid_sources[0x1d]	2802	1		T14	3		T44	14		T42	14
valid_sources[0x1e]	2226	1		T9	1		T44	12		T42	8
valid_sources[0x1f]	2704	1		T23	10		T44	23		T40	51
valid_sources[0x20]	3219	1		T19	1		T6	1		T14	1
valid_sources[0x21]	2623	1		T15	1		T44	11		T40	44
valid_sources[0x22]	2489	1		T9	1		T79	4		T44	17
valid_sources[0x23]	2881	1		T44	8		T40	49		T43	21
valid_sources[0x24]	2505	1		T9	1		T44	13		T42	102
valid_sources[0x25]	2420	1		T14	8		T44	7		T42	6
valid_sources[0x26]	2604	1		T44	14		T42	22		T40	31
valid_sources[0x27]	2977	1		T44	12		T42	26		T40	38
valid_sources[0x28]	2738	1		T11	3		T14	1		T44	12
valid_sources[0x29]	3272	1		T11	7		T44	9		T42	3
valid_sources[0x2a]	2888	1		T7	1		T9	1		T44	13
valid_sources[0x2b]	2607	1		T44	10		T42	10		T40	46
valid_sources[0x2c]	2278	1		T6	1		T14	3		T44	9
valid_sources[0x2d]	2686	1		T28	2		T20	2		T44	9
valid_sources[0x2e]	3288	1		T14	1		T44	13		T42	19
valid_sources[0x2f]	2680	1		T14	1		T44	5		T42	17
valid_sources[0x30]	2581	1		T44	11		T40	32		T43	20
valid_sources[0x31]	2638	1		T44	7		T42	41		T40	28
valid_sources[0x32]	3047	1		T79	12		T44	13		T39	1
valid_sources[0x33]	3089	1		T28	2		T44	13		T42	9
valid_sources[0x34]	2637	1		T44	13		T42	15		T40	71
valid_sources[0x35]	2814	1		T9	1		T44	9		T42	6
valid_sources[0x36]	2619	1		T7	1		T44	6		T40	46
valid_sources[0x37]	2631	1		T44	4		T42	11		T40	30
valid_sources[0x38]	2704	1		T20	9		T44	9		T40	37
valid_sources[0x39]	3542	1		T6	1		T9	2		T44	4
valid_sources[0x3a]	3159	1		T44	13		T42	35		T40	60
valid_sources[0x3b]	2928	1		T44	9		T40	47		T78	10
valid_sources[0x3c]	2595	1		T36	14		T44	10		T40	55
valid_sources[0x3d]	3584	1		T14	1		T44	7		T40	40
valid_sources[0x3e]	2677	1		T6	1		T44	12		T40	17
valid_sources[0x3f]	2641	1		T9	1		T44	12		T42	4
valid_sources[0x40]	2516	1		T23	3		T79	1		T44	15
valid_sources[0x41]	2555	1		T9	1		T44	12		T42	12
valid_sources[0x42]	2653	1		T44	7		T40	65		T78	7
valid_sources[0x43]	2632	1		T44	15		T42	17		T40	43
valid_sources[0x44]	2810	1		T44	14		T42	2		T40	56
valid_sources[0x45]	2556	1		T44	10		T42	1		T40	25
valid_sources[0x46]	3035	1		T9	1		T24	1		T44	12
valid_sources[0x47]	2812	1		T7	2		T27	1		T44	15
valid_sources[0x48]	2710	1		T44	13		T42	10		T40	76
valid_sources[0x49]	2593	1		T14	5		T44	13		T42	11
valid_sources[0x4a]	2499	1		T9	2		T44	6		T40	24
valid_sources[0x4b]	2543	1		T19	1		T6	1		T44	19
valid_sources[0x4c]	2838	1		T44	7		T40	54		T43	20
valid_sources[0x4d]	2646	1		T14	1		T44	11		T42	25
valid_sources[0x4e]	2542	1		T44	10		T40	50		T43	14
valid_sources[0x4f]	2606	1		T6	1		T9	1		T44	14
valid_sources[0x50]	2548	1		T44	20		T40	39		T43	19
valid_sources[0x51]	2884	1		T44	4		T40	25		T78	14
valid_sources[0x52]	6267	1		T44	16		T42	26		T40	50
valid_sources[0x53]	2794	1		T9	2		T44	13		T42	7
valid_sources[0x54]	3262	1		T9	1		T27	1		T14	1
valid_sources[0x55]	2366	1		T44	15		T42	5		T40	43
valid_sources[0x56]	3691	1		T44	12		T42	19		T40	39
valid_sources[0x57]	2705	1		T44	11		T42	33		T40	18
valid_sources[0x58]	3512	1		T44	10		T40	22		T41	24
valid_sources[0x59]	2175	1		T44	15		T42	11		T40	39
valid_sources[0x5a]	2939	1		T6	1		T13	1		T14	3
valid_sources[0x5b]	2716	1		T6	1		T14	1		T24	1
valid_sources[0x5c]	2426	1		T27	1		T44	11		T42	23
valid_sources[0x5d]	2400	1		T9	3		T27	1		T10	6
valid_sources[0x5e]	2771	1		T44	14		T40	55		T43	5
valid_sources[0x5f]	2821	1		T6	1		T44	10		T40	27
valid_sources[0x60]	2686	1		T19	2		T6	1		T44	19
valid_sources[0x61]	2634	1		T9	3		T44	8		T42	12
valid_sources[0x62]	2883	1		T6	1		T14	2		T44	14
valid_sources[0x63]	2794	1		T6	2		T44	12		T40	38
valid_sources[0x64]	2646	1		T44	13		T42	6		T40	44
valid_sources[0x65]	2713	1		T14	7		T44	15		T42	8
valid_sources[0x66]	3153	1		T10	10		T14	1		T44	14
valid_sources[0x67]	2438	1		T44	15		T40	27		T41	8
valid_sources[0x68]	2635	1		T44	16		T42	7		T40	31
valid_sources[0x69]	3156	1		T44	13		T40	46		T43	42
valid_sources[0x6a]	2689	1		T44	9		T42	17		T40	40
valid_sources[0x6b]	2786	1		T6	1		T9	2		T44	8
valid_sources[0x6c]	2878	1		T7	1		T44	9		T40	36
valid_sources[0x6d]	2518	1		T6	1		T44	11		T42	55
valid_sources[0x6e]	2622	1		T15	1		T14	1		T44	13
valid_sources[0x6f]	2413	1		T6	2		T44	7		T42	7
valid_sources[0x70]	2369	1		T44	12		T42	22		T40	36
valid_sources[0x71]	2606	1		T44	6		T42	16		T40	39
valid_sources[0x72]	2834	1		T27	1		T44	26		T42	12
valid_sources[0x73]	3962	1		T9	1		T44	12		T42	8
valid_sources[0x74]	2464	1		T9	1		T44	20		T42	53
valid_sources[0x75]	2828	1		T20	1		T14	5		T140	1
valid_sources[0x76]	2949	1		T44	9		T42	19		T40	27
valid_sources[0x77]	2440	1		T6	1		T20	7		T44	16
valid_sources[0x78]	2944	1		T44	14		T42	24		T40	72
valid_sources[0x79]	2853	1		T6	1		T44	11		T42	4
valid_sources[0x7a]	2756	1		T14	1		T44	15		T42	16
valid_sources[0x7b]	2918	1		T44	10		T42	4		T40	50
valid_sources[0x7c]	3210	1		T44	13		T42	9		T40	80
valid_sources[0x7d]	2676	1		T44	12		T42	10		T40	28
valid_sources[0x7e]	2389	1		T7	1		T14	5		T44	9
valid_sources[0x7f]	2491	1		T20	5		T44	16		T40	31
valid_sources[0x80]	2802	1		T6	1		T44	11		T42	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

270265

1

T1

7

T5

4

T27

5

values[0x0]

all_enables

biggest_size

129523

1

T3

2

T7

3

T8

3

values[0x1]

all_enables

biggest_size

129769

1

T3

3

T7

1

T5

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4205	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18442	1		T2	4		T33	3		T34	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8447	1		T44	7		T39	33		T42	20
values[0x0]	6978	1		T2	5		T33	8		T34	1
values[0x1]	7222	1		T2	14		T33	8		T34	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3239	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19408	1		T2	6		T33	5		T34	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60	1		T89	2		T91	2		T105	9
valid_sources[0x01]	42	1		T40	1		T108	2		T116	2
valid_sources[0x02]	100	1		T100	1		T108	1		T104	2
valid_sources[0x03]	63	1		T89	1		T108	1		T92	3
valid_sources[0x04]	93	1		T39	4		T40	1		T100	2
valid_sources[0x05]	79	1		T141	1		T44	1		T40	2
valid_sources[0x06]	60	1		T46	1		T43	1		T78	2
valid_sources[0x07]	109	1		T40	1		T78	1		T97	1
valid_sources[0x08]	85	1		T142	1		T40	2		T100	5
valid_sources[0x09]	71	1		T43	2		T78	1		T100	1
valid_sources[0x0a]	76	1		T143	1		T144	2		T78	2
valid_sources[0x0b]	89	1		T145	1		T40	1		T100	3
valid_sources[0x0c]	111	1		T40	1		T91	1		T72	3
valid_sources[0x0d]	34	1		T146	1		T100	1		T108	1
valid_sources[0x0e]	124	1		T97	2		T90	9		T91	1
valid_sources[0x0f]	63	1		T147	1		T78	2		T100	1
valid_sources[0x10]	98	1		T148	1		T149	2		T108	2
valid_sources[0x11]	130	1		T47	14		T61	2		T39	2
valid_sources[0x12]	72	1		T65	1		T39	3		T40	1
valid_sources[0x13]	42	1		T141	2		T97	1		T108	3
valid_sources[0x14]	75	1		T78	1		T100	1		T108	3
valid_sources[0x15]	82	1		T100	2		T108	3		T115	1
valid_sources[0x16]	54	1		T100	1		T92	1		T128	3
valid_sources[0x17]	59	1		T40	2		T91	8		T108	5
valid_sources[0x18]	94	1		T150	1		T40	3		T100	2
valid_sources[0x19]	58	1		T151	1		T39	3		T40	2
valid_sources[0x1a]	63	1		T152	2		T78	1		T100	2
valid_sources[0x1b]	72	1		T33	3		T40	1		T97	1
valid_sources[0x1c]	102	1		T100	2		T91	1		T108	4
valid_sources[0x1d]	87	1		T147	1		T100	1		T101	2
valid_sources[0x1e]	52	1		T43	4		T108	5		T116	3
valid_sources[0x1f]	69	1		T143	1		T44	1		T39	7
valid_sources[0x20]	83	1		T153	1		T144	1		T78	1
valid_sources[0x21]	167	1		T40	1		T90	58		T72	21
valid_sources[0x22]	59	1		T154	3		T39	1		T40	1
valid_sources[0x23]	94	1		T69	9		T40	1		T97	1
valid_sources[0x24]	62	1		T40	2		T78	1		T97	1
valid_sources[0x25]	242	1		T40	1		T43	3		T78	1
valid_sources[0x26]	71	1		T152	2		T100	5		T91	2
valid_sources[0x27]	62	1		T90	5		T91	2		T108	3
valid_sources[0x28]	74	1		T108	5		T128	1		T106	2
valid_sources[0x29]	81	1		T40	1		T97	1		T89	2
valid_sources[0x2a]	88	1		T89	12		T100	3		T91	5
valid_sources[0x2b]	95	1		T143	1		T43	1		T78	1
valid_sources[0x2c]	137	1		T146	1		T44	1		T78	2
valid_sources[0x2d]	73	1		T64	1		T42	4		T40	1
valid_sources[0x2e]	49	1		T39	1		T40	1		T78	1
valid_sources[0x2f]	89	1		T130	5		T141	1		T39	1
valid_sources[0x30]	68	1		T155	1		T39	2		T40	1
valid_sources[0x31]	146	1		T147	1		T40	1		T90	18
valid_sources[0x32]	59	1		T141	1		T40	1		T100	2
valid_sources[0x33]	58	1		T89	2		T108	2		T104	2
valid_sources[0x34]	50	1		T100	1		T108	2		T104	1
valid_sources[0x35]	46	1		T100	1		T103	1		T104	1
valid_sources[0x36]	77	1		T97	1		T100	1		T91	5
valid_sources[0x37]	117	1		T35	17		T40	3		T89	14
valid_sources[0x38]	67	1		T100	1		T128	5		T116	1
valid_sources[0x39]	77	1		T152	3		T40	1		T97	2
valid_sources[0x3a]	69	1		T153	1		T60	1		T97	1
valid_sources[0x3b]	48	1		T153	1		T40	1		T97	2
valid_sources[0x3c]	54	1		T143	1		T40	1		T91	1
valid_sources[0x3d]	446	1		T91	5		T108	2		T116	1
valid_sources[0x3e]	53	1		T91	3		T108	4		T128	5
valid_sources[0x3f]	79	1		T90	15		T100	2		T91	1
valid_sources[0x40]	54	1		T155	1		T100	1		T91	1
valid_sources[0x41]	50	1		T156	1		T40	1		T91	2
valid_sources[0x42]	197	1		T157	2		T78	1		T97	2
valid_sources[0x43]	80	1		T129	10		T40	2		T99	3
valid_sources[0x44]	59	1		T147	1		T40	1		T100	1
valid_sources[0x45]	86	1		T61	1		T141	1		T39	1
valid_sources[0x46]	109	1		T40	2		T89	7		T108	2
valid_sources[0x47]	49	1		T61	1		T142	1		T108	2
valid_sources[0x48]	84	1		T40	2		T78	1		T100	3
valid_sources[0x49]	172	1		T40	1		T41	113		T78	1
valid_sources[0x4a]	70	1		T150	1		T40	2		T78	1
valid_sources[0x4b]	82	1		T150	1		T39	1		T40	1
valid_sources[0x4c]	89	1		T158	1		T78	2		T101	1
valid_sources[0x4d]	113	1		T157	3		T63	1		T90	44
valid_sources[0x4e]	88	1		T159	12		T43	1		T101	1
valid_sources[0x4f]	70	1		T89	4		T108	2		T104	1
valid_sources[0x50]	62	1		T128	1		T95	2		T106	2
valid_sources[0x51]	75	1		T40	1		T43	4		T100	1
valid_sources[0x52]	74	1		T39	5		T41	2		T97	1
valid_sources[0x53]	67	1		T41	1		T97	1		T108	5
valid_sources[0x54]	79	1		T65	2		T160	3		T101	1
valid_sources[0x55]	59	1		T65	1		T161	2		T89	1
valid_sources[0x56]	81	1		T64	1		T89	4		T100	1
valid_sources[0x57]	76	1		T147	1		T40	1		T97	1
valid_sources[0x58]	95	1		T141	2		T44	1		T40	2
valid_sources[0x59]	92	1		T145	1		T160	1		T40	1
valid_sources[0x5a]	109	1		T39	1		T78	1		T89	2
valid_sources[0x5b]	64	1		T144	1		T97	1		T100	1
valid_sources[0x5c]	103	1		T90	49		T101	3		T108	1
valid_sources[0x5d]	297	1		T61	1		T40	2		T97	2
valid_sources[0x5e]	67	1		T148	3		T44	1		T40	2
valid_sources[0x5f]	88	1		T97	1		T100	2		T91	6
valid_sources[0x60]	79	1		T39	4		T40	1		T97	1
valid_sources[0x61]	115	1		T149	3		T78	1		T90	1
valid_sources[0x62]	123	1		T155	2		T162	18		T97	1
valid_sources[0x63]	35	1		T64	1		T91	1		T108	1
valid_sources[0x64]	102	1		T97	1		T108	2		T106	1
valid_sources[0x65]	69	1		T39	3		T100	2		T91	2
valid_sources[0x66]	95	1		T40	1		T43	1		T89	14
valid_sources[0x67]	94	1		T163	1		T100	1		T72	25
valid_sources[0x68]	51	1		T46	1		T161	2		T100	1
valid_sources[0x69]	55	1		T163	2		T100	1		T108	3
valid_sources[0x6a]	74	1		T40	4		T100	4		T108	5
valid_sources[0x6b]	95	1		T144	1		T97	1		T89	6
valid_sources[0x6c]	92	1		T39	1		T40	2		T43	3
valid_sources[0x6d]	92	1		T143	1		T149	1		T97	1
valid_sources[0x6e]	69	1		T91	8		T108	2		T104	1
valid_sources[0x6f]	74	1		T61	1		T44	1		T43	3
valid_sources[0x70]	101	1		T39	1		T91	2		T92	1
valid_sources[0x71]	93	1		T97	1		T100	1		T108	6
valid_sources[0x72]	92	1		T160	1		T78	1		T97	2
valid_sources[0x73]	82	1		T38	12		T143	2		T161	1
valid_sources[0x74]	63	1		T40	1		T89	1		T100	1
valid_sources[0x75]	70	1		T40	1		T91	1		T108	2
valid_sources[0x76]	110	1		T40	2		T89	6		T91	2
valid_sources[0x77]	57	1		T61	1		T100	2		T108	1
valid_sources[0x78]	87	1		T46	1		T40	1		T91	4
valid_sources[0x79]	85	1		T40	1		T90	7		T100	2
valid_sources[0x7a]	47	1		T153	1		T39	2		T40	1
valid_sources[0x7b]	75	1		T44	1		T89	3		T100	2
valid_sources[0x7c]	87	1		T143	1		T44	1		T39	1
valid_sources[0x7d]	60	1		T33	1		T61	2		T40	1
valid_sources[0x7e]	69	1		T64	1		T65	1		T100	3
valid_sources[0x7f]	77	1		T164	3		T40	1		T97	2
valid_sources[0x80]	64	1		T33	4		T141	1		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6078

1

T44

7

T39

33

T42

20

values[0x0]

all_enables

biggest_size

6217

1

T2

2

T33

1

T35

2

values[0x1]

all_enables

biggest_size

6147

1

T2

2

T33

2

T34

1